From 339e3e340ee3e3d19514d0dde95eeef96402cfb7 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 20 Feb 2018 22:19:35 -0500 Subject: [PATCH] target-arm: Add comment about not implementing NSACR.RFR QEMU doesn't implement the NSACR.RFR bit, which is a permitted IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8. Add a comment to bad_mode_switch() to note that this is why FIQ is always a valid mode regardless of the CPU's Secure state. Backports commit 52ff951b4f63a29593650a15efdf82f63d6d962d from qemu --- qemu/target-arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index f5e6c0fb..dd32ce24 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -4517,6 +4517,9 @@ static int bad_mode_switch(CPUARMState *env, int mode) case ARM_CPU_MODE_UND: case ARM_CPU_MODE_IRQ: case ARM_CPU_MODE_FIQ: + /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 + * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) + */ return 0; case ARM_CPU_MODE_MON: return !arm_is_secure(env);