From 33e9ea3f106d036770bded4ca186f096fd79d47e Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Tue, 22 Jan 2019 19:50:34 -0500 Subject: [PATCH] target/mips: Provide R/W access to SAARI and SAAR CP0 registers Provide R/W access to SAARI and SAAR CP0 registers. Backports commit 5fb2dcd17921be71b55fb62d59a12992707d2d3e from qemu --- qemu/header_gen.py | 6 ++++ qemu/mips.h | 6 ++++ qemu/mips64.h | 6 ++++ qemu/mips64el.h | 6 ++++ qemu/mipsel.h | 6 ++++ qemu/target/mips/cpu.h | 1 + qemu/target/mips/helper.h | 6 ++++ qemu/target/mips/internal.h | 1 + qemu/target/mips/op_helper.c | 50 +++++++++++++++++++++++++++ qemu/target/mips/translate.c | 66 +++++++++++++++++++++++++++++++++--- 10 files changed, 150 insertions(+), 4 deletions(-) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index e3aa8b9b..b5222d46 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -4554,6 +4554,7 @@ mips_symbols = ( 'helper_dmaddu', 'helper_dmfc0_lladdr', 'helper_dmfc0_maar', + 'helper_dmfc0_saar', 'helper_dmfc0_tccontext', 'helper_dmfc0_tchalt', 'helper_dmfc0_tcrestart', @@ -4755,6 +4756,7 @@ mips_symbols = ( 'helper_mfc0_mvpconf1', 'helper_mfc0_mvpcontrol', 'helper_mfc0_random', + 'helper_mfc0_saar', 'helper_mfc0_tcbind', 'helper_mfc0_tccontext', 'helper_mfc0_tchalt', @@ -4765,6 +4767,7 @@ mips_symbols = ( 'helper_mfc0_watchhi', 'helper_mfc0_watchlo', 'helper_mfhc0_maar', + 'helper_mfhc0_saar', 'helper_mftacx', 'helper_mftc0_cause', 'helper_mftc0_configx', @@ -4996,6 +4999,8 @@ mips_symbols = ( 'helper_mtc0_pwctl', 'helper_mtc0_pwfield', 'helper_mtc0_pwsize', + 'helper_mtc0_saar', + 'helper_mtc0_saari', 'helper_mtc0_segctl0', 'helper_mtc0_segctl1', 'helper_mtc0_segctl2', @@ -5025,6 +5030,7 @@ mips_symbols = ( 'helper_mtc0_xcontext', 'helper_mtc0_yqmask', 'helper_mthc0_maar', + 'helper_mthc0_saar', 'helper_mthlip', 'helper_mttacx', 'helper_mttc0_cause', diff --git a/qemu/mips.h b/qemu/mips.h index 48996780..a36f08bc 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -3472,6 +3472,7 @@ #define helper_dmaddu helper_dmaddu_mips #define helper_dmfc0_lladdr helper_dmfc0_lladdr_mips #define helper_dmfc0_maar helper_dmfc0_maar_mips +#define helper_dmfc0_saar helper_dmfc0_saar_mips #define helper_dmfc0_tccontext helper_dmfc0_tccontext_mips #define helper_dmfc0_tchalt helper_dmfc0_tchalt_mips #define helper_dmfc0_tcrestart helper_dmfc0_tcrestart_mips @@ -3673,6 +3674,7 @@ #define helper_mfc0_mvpconf1 helper_mfc0_mvpconf1_mips #define helper_mfc0_mvpcontrol helper_mfc0_mvpcontrol_mips #define helper_mfc0_random helper_mfc0_random_mips +#define helper_mfc0_saar helper_mfc0_saar_mips #define helper_mfc0_tcbind helper_mfc0_tcbind_mips #define helper_mfc0_tccontext helper_mfc0_tccontext_mips #define helper_mfc0_tchalt helper_mfc0_tchalt_mips @@ -3683,6 +3685,7 @@ #define helper_mfc0_watchhi helper_mfc0_watchhi_mips #define helper_mfc0_watchlo helper_mfc0_watchlo_mips #define helper_mfhc0_maar helper_mfhc0_maar_mips +#define helper_mfhc0_saar helper_mfhc0_saar_mips #define helper_mftacx helper_mftacx_mips #define helper_mftc0_cause helper_mftc0_cause_mips #define helper_mftc0_configx helper_mftc0_configx_mips @@ -3914,6 +3917,8 @@ #define helper_mtc0_pwctl helper_mtc0_pwctl_mips #define helper_mtc0_pwfield helper_mtc0_pwfield_mips #define helper_mtc0_pwsize helper_mtc0_pwsize_mips +#define helper_mtc0_saar helper_mtc0_saar_mips +#define helper_mtc0_saari helper_mtc0_saari_mips #define helper_mtc0_segctl0 helper_mtc0_segctl0_mips #define helper_mtc0_segctl1 helper_mtc0_segctl1_mips #define helper_mtc0_segctl2 helper_mtc0_segctl2_mips @@ -3943,6 +3948,7 @@ #define helper_mtc0_xcontext helper_mtc0_xcontext_mips #define helper_mtc0_yqmask helper_mtc0_yqmask_mips #define helper_mthc0_maar helper_mthc0_maar_mips +#define helper_mthc0_saar helper_mthc0_saar_mips #define helper_mthlip helper_mthlip_mips #define helper_mttacx helper_mttacx_mips #define helper_mttc0_cause helper_mttc0_cause_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index 614b3d50..547ee6a7 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -3472,6 +3472,7 @@ #define helper_dmaddu helper_dmaddu_mips64 #define helper_dmfc0_lladdr helper_dmfc0_lladdr_mips64 #define helper_dmfc0_maar helper_dmfc0_maar_mips64 +#define helper_dmfc0_saar helper_dmfc0_saar_mips64 #define helper_dmfc0_tccontext helper_dmfc0_tccontext_mips64 #define helper_dmfc0_tchalt helper_dmfc0_tchalt_mips64 #define helper_dmfc0_tcrestart helper_dmfc0_tcrestart_mips64 @@ -3673,6 +3674,7 @@ #define helper_mfc0_mvpconf1 helper_mfc0_mvpconf1_mips64 #define helper_mfc0_mvpcontrol helper_mfc0_mvpcontrol_mips64 #define helper_mfc0_random helper_mfc0_random_mips64 +#define helper_mfc0_saar helper_mfc0_saar_mips64 #define helper_mfc0_tcbind helper_mfc0_tcbind_mips64 #define helper_mfc0_tccontext helper_mfc0_tccontext_mips64 #define helper_mfc0_tchalt helper_mfc0_tchalt_mips64 @@ -3683,6 +3685,7 @@ #define helper_mfc0_watchhi helper_mfc0_watchhi_mips64 #define helper_mfc0_watchlo helper_mfc0_watchlo_mips64 #define helper_mfhc0_maar helper_mfhc0_maar_mips64 +#define helper_mfhc0_saar helper_mfhc0_saar_mips64 #define helper_mftacx helper_mftacx_mips64 #define helper_mftc0_cause helper_mftc0_cause_mips64 #define helper_mftc0_configx helper_mftc0_configx_mips64 @@ -3914,6 +3917,8 @@ #define helper_mtc0_pwctl helper_mtc0_pwctl_mips64 #define helper_mtc0_pwfield helper_mtc0_pwfield_mips64 #define helper_mtc0_pwsize helper_mtc0_pwsize_mips64 +#define helper_mtc0_saar helper_mtc0_saar_mips64 +#define helper_mtc0_saari helper_mtc0_saari_mips64 #define helper_mtc0_segctl0 helper_mtc0_segctl0_mips64 #define helper_mtc0_segctl1 helper_mtc0_segctl1_mips64 #define helper_mtc0_segctl2 helper_mtc0_segctl2_mips64 @@ -3943,6 +3948,7 @@ #define helper_mtc0_xcontext helper_mtc0_xcontext_mips64 #define helper_mtc0_yqmask helper_mtc0_yqmask_mips64 #define helper_mthc0_maar helper_mthc0_maar_mips64 +#define helper_mthc0_saar helper_mthc0_saar_mips64 #define helper_mthlip helper_mthlip_mips64 #define helper_mttacx helper_mttacx_mips64 #define helper_mttc0_cause helper_mttc0_cause_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index 4eed0169..ca2e8a3b 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -3472,6 +3472,7 @@ #define helper_dmaddu helper_dmaddu_mips64el #define helper_dmfc0_lladdr helper_dmfc0_lladdr_mips64el #define helper_dmfc0_maar helper_dmfc0_maar_mips64el +#define helper_dmfc0_saar helper_dmfc0_saar_mips64el #define helper_dmfc0_tccontext helper_dmfc0_tccontext_mips64el #define helper_dmfc0_tchalt helper_dmfc0_tchalt_mips64el #define helper_dmfc0_tcrestart helper_dmfc0_tcrestart_mips64el @@ -3673,6 +3674,7 @@ #define helper_mfc0_mvpconf1 helper_mfc0_mvpconf1_mips64el #define helper_mfc0_mvpcontrol helper_mfc0_mvpcontrol_mips64el #define helper_mfc0_random helper_mfc0_random_mips64el +#define helper_mfc0_saar helper_mfc0_saar_mips64el #define helper_mfc0_tcbind helper_mfc0_tcbind_mips64el #define helper_mfc0_tccontext helper_mfc0_tccontext_mips64el #define helper_mfc0_tchalt helper_mfc0_tchalt_mips64el @@ -3683,6 +3685,7 @@ #define helper_mfc0_watchhi helper_mfc0_watchhi_mips64el #define helper_mfc0_watchlo helper_mfc0_watchlo_mips64el #define helper_mfhc0_maar helper_mfhc0_maar_mips64el +#define helper_mfhc0_saar helper_mfhc0_saar_mips64el #define helper_mftacx helper_mftacx_mips64el #define helper_mftc0_cause helper_mftc0_cause_mips64el #define helper_mftc0_configx helper_mftc0_configx_mips64el @@ -3914,6 +3917,8 @@ #define helper_mtc0_pwctl helper_mtc0_pwctl_mips64el #define helper_mtc0_pwfield helper_mtc0_pwfield_mips64el #define helper_mtc0_pwsize helper_mtc0_pwsize_mips64el +#define helper_mtc0_saar helper_mtc0_saar_mips64el +#define helper_mtc0_saari helper_mtc0_saari_mips64el #define helper_mtc0_segctl0 helper_mtc0_segctl0_mips64el #define helper_mtc0_segctl1 helper_mtc0_segctl1_mips64el #define helper_mtc0_segctl2 helper_mtc0_segctl2_mips64el @@ -3943,6 +3948,7 @@ #define helper_mtc0_xcontext helper_mtc0_xcontext_mips64el #define helper_mtc0_yqmask helper_mtc0_yqmask_mips64el #define helper_mthc0_maar helper_mthc0_maar_mips64el +#define helper_mthc0_saar helper_mthc0_saar_mips64el #define helper_mthlip helper_mthlip_mips64el #define helper_mttacx helper_mttacx_mips64el #define helper_mttc0_cause helper_mttc0_cause_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index f77c2896..b6285dc3 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -3472,6 +3472,7 @@ #define helper_dmaddu helper_dmaddu_mipsel #define helper_dmfc0_lladdr helper_dmfc0_lladdr_mipsel #define helper_dmfc0_maar helper_dmfc0_maar_mipsel +#define helper_dmfc0_saar helper_dmfc0_saar_mipsel #define helper_dmfc0_tccontext helper_dmfc0_tccontext_mipsel #define helper_dmfc0_tchalt helper_dmfc0_tchalt_mipsel #define helper_dmfc0_tcrestart helper_dmfc0_tcrestart_mipsel @@ -3673,6 +3674,7 @@ #define helper_mfc0_mvpconf1 helper_mfc0_mvpconf1_mipsel #define helper_mfc0_mvpcontrol helper_mfc0_mvpcontrol_mipsel #define helper_mfc0_random helper_mfc0_random_mipsel +#define helper_mfc0_saar helper_mfc0_saar_mipsel #define helper_mfc0_tcbind helper_mfc0_tcbind_mipsel #define helper_mfc0_tccontext helper_mfc0_tccontext_mipsel #define helper_mfc0_tchalt helper_mfc0_tchalt_mipsel @@ -3683,6 +3685,7 @@ #define helper_mfc0_watchhi helper_mfc0_watchhi_mipsel #define helper_mfc0_watchlo helper_mfc0_watchlo_mipsel #define helper_mfhc0_maar helper_mfhc0_maar_mipsel +#define helper_mfhc0_saar helper_mfhc0_saar_mipsel #define helper_mftacx helper_mftacx_mipsel #define helper_mftc0_cause helper_mftc0_cause_mipsel #define helper_mftc0_configx helper_mftc0_configx_mipsel @@ -3914,6 +3917,8 @@ #define helper_mtc0_pwctl helper_mtc0_pwctl_mipsel #define helper_mtc0_pwfield helper_mtc0_pwfield_mipsel #define helper_mtc0_pwsize helper_mtc0_pwsize_mipsel +#define helper_mtc0_saar helper_mtc0_saar_mipsel +#define helper_mtc0_saari helper_mtc0_saari_mipsel #define helper_mtc0_segctl0 helper_mtc0_segctl0_mipsel #define helper_mtc0_segctl1 helper_mtc0_segctl1_mipsel #define helper_mtc0_segctl2 helper_mtc0_segctl2_mipsel @@ -3943,6 +3948,7 @@ #define helper_mtc0_xcontext helper_mtc0_xcontext_mipsel #define helper_mtc0_yqmask helper_mtc0_yqmask_mipsel #define helper_mthc0_maar helper_mthc0_maar_mipsel +#define helper_mthc0_saar helper_mthc0_saar_mipsel #define helper_mthlip helper_mthlip_mipsel #define helper_mttacx helper_mttacx_mipsel #define helper_mttc0_cause helper_mttc0_cause_mipsel diff --git a/qemu/target/mips/cpu.h b/qemu/target/mips/cpu.h index a69530c6..c7711d7f 100644 --- a/qemu/target/mips/cpu.h +++ b/qemu/target/mips/cpu.h @@ -900,6 +900,7 @@ struct CPUMIPSState { uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ uint64_t insn_flags; /* Supported instruction set */ + int saarp; /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/qemu/target/mips/helper.h b/qemu/target/mips/helper.h index 31a2d164..1b7a8ef5 100644 --- a/qemu/target/mips/helper.h +++ b/qemu/target/mips/helper.h @@ -65,6 +65,8 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env) DEF_HELPER_1(mfc0_tcschefback, tl, env) DEF_HELPER_1(mftc0_tcschefback, tl, env) DEF_HELPER_1(mfc0_count, tl, env) +DEF_HELPER_1(mfc0_saar, tl, env) +DEF_HELPER_1(mfhc0_saar, tl, env) DEF_HELPER_1(mftc0_entryhi, tl, env) DEF_HELPER_1(mftc0_status, tl, env) DEF_HELPER_1(mftc0_cause, tl, env) @@ -87,6 +89,7 @@ DEF_HELPER_1(dmfc0_tcschefback, tl, env) DEF_HELPER_1(dmfc0_lladdr, tl, env) DEF_HELPER_1(dmfc0_maar, tl, env) DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) +DEF_HELPER_1(dmfc0_saar, tl, env) #endif /* TARGET_MIPS64 */ DEF_HELPER_2(mtc0_index, void, env, tl) @@ -131,6 +134,9 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl) DEF_HELPER_2(mtc0_hwrena, void, env, tl) DEF_HELPER_2(mtc0_pwctl, void, env, tl) DEF_HELPER_2(mtc0_count, void, env, tl) +DEF_HELPER_2(mtc0_saari, void, env, tl) +DEF_HELPER_2(mtc0_saar, void, env, tl) +DEF_HELPER_2(mthc0_saar, void, env, tl) DEF_HELPER_2(mtc0_entryhi, void, env, tl) DEF_HELPER_2(mttc0_entryhi, void, env, tl) DEF_HELPER_2(mtc0_compare, void, env, tl) diff --git a/qemu/target/mips/internal.h b/qemu/target/mips/internal.h index 4ff2c66a..92329b93 100644 --- a/qemu/target/mips/internal.h +++ b/qemu/target/mips/internal.h @@ -61,6 +61,7 @@ struct mips_def_t { target_ulong CP0_EBaseWG_rw_bitmask; uint64_t insn_flags; enum mips_mmu_types mmu_type; + int32_t SAARP; }; extern const struct mips_def_t mips_defs[]; diff --git a/qemu/target/mips/op_helper.c b/qemu/target/mips/op_helper.c index 9eb34de4..20ad1ff2 100644 --- a/qemu/target/mips/op_helper.c +++ b/qemu/target/mips/op_helper.c @@ -928,6 +928,22 @@ target_ulong helper_mfc0_count(CPUMIPSState *env) return (int32_t)cpu_mips_get_count(env); } +target_ulong helper_mfc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f]; + } + return 0; +} + +target_ulong helper_mfhc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32; + } + return 0; +} + target_ulong helper_mftc0_entryhi(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); @@ -1049,6 +1065,14 @@ target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel) { return env->CP0_WatchLo[sel]; } + +target_ulong helper_dmfc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return env->CP0_SAAR[env->CP0_SAARI & 0x3f]; + } + return 0; +} #endif /* TARGET_MIPS64 */ void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) @@ -1586,6 +1610,32 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) cpu_mips_store_count(env, arg1); } +void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target = arg1 & 0x3f; + if (target <= 1) { + env->CP0_SAARI = target; + } +} + +void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target = env->CP0_SAARI & 0x3f; + if (target < 2) { + env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL; + } +} + +void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target = env->CP0_SAARI & 0x3f; + if (target < 2) { + env->CP0_SAAR[target] = + (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) | + (env->CP0_SAAR[target] & 0x00000000ffffffffULL); + } +} + void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val, mask; diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index 1a00474c..c4c4296e 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -2513,6 +2513,7 @@ typedef struct DisasContext { bool mrp; bool nan2008; bool abs2008; + bool saar; // Unicorn engine struct uc_struct *uc; @@ -6680,6 +6681,17 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; + case CPO_REGISTER_09: + switch (sel) { + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mfhc0_saar(s, arg, s->cpu_env); + rn = "SAAR"; + break; + default: + goto cp0_unimplemented; + } + break; case CPO_REGISTER_17: switch (sel) { case 0: @@ -6753,6 +6765,16 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; + case CPO_REGISTER_09: + switch (sel) { + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mthc0_saar(s, s->cpu_env, arg); + rn = "SAAR"; + break; + default: + goto cp0_unimplemented; + } case CPO_REGISTER_17: switch (sel) { case 0: @@ -7134,7 +7156,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) ctx->base.is_jmp = DISAS_EXIT; rn = "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SAARI)); + rn = "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mfc0_saar(tcg_ctx, arg, tcg_ctx->cpu_env); + rn = "SAAR"; + break; default: goto cp0_unimplemented; } @@ -7837,7 +7868,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_helper_mtc0_count(tcg_ctx, tcg_ctx->cpu_env, arg); rn = "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saari(tcg_ctx, tcg_ctx->cpu_env, arg); + rn = "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saar(tcg_ctx, tcg_ctx->cpu_env, arg); + rn = "SAAR"; + break; default: goto cp0_unimplemented; } @@ -8577,7 +8617,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) ctx->base.is_jmp = DISAS_EXIT; rn = "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SAARI)); + rn = "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_dmfc0_saar(tcg_ctx, arg, tcg_ctx->cpu_env); + rn = "SAAR"; + break; default: goto cp0_unimplemented; } @@ -9263,7 +9312,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_helper_mtc0_count(tcg_ctx, tcg_ctx->cpu_env, arg); rn = "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saari(tcg_ctx, tcg_ctx->cpu_env, arg); + rn = "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saar(tcg_ctx, tcg_ctx->cpu_env, arg); + rn = "SAAR"; + break; default: goto cp0_unimplemented; }