From 3546558f66cec7d5e8a0a2ec81293f75304180f2 Mon Sep 17 00:00:00 2001 From: "Emilio G. Cota" Date: Wed, 28 Feb 2018 00:11:20 -0500 Subject: [PATCH] target-arm: emulate SWP with atomic_xchg helper Backports commit cf12bce088f22b92bf62ffa0d7f6a3e951e355a9 from qemu --- qemu/target-arm/translate.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/qemu/target-arm/translate.c b/qemu/target-arm/translate.c index 4ab7efea..b82c01c0 100644 --- a/qemu/target-arm/translate.c +++ b/qemu/target-arm/translate.c @@ -8946,25 +8946,27 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq } tcg_temp_free_i32(tcg_ctx, addr); } else { + TCGv taddr; + TCGMemOp opc = s->be_data; + /* SWP instruction */ rm = (insn) & 0xf; - /* ??? This is not really atomic. However we know - we never have multiple CPUs running in parallel, - so it is good enough. */ - addr = load_reg(s, rn); - tmp = load_reg(s, rm); - tmp2 = tcg_temp_new_i32(tcg_ctx); if (insn & (1 << 22)) { - gen_aa32_ld8u(s, tmp2, addr, get_mem_index(s)); - gen_aa32_st8(s, tmp, addr, get_mem_index(s)); + opc |= MO_UB; } else { - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + opc |= MO_UL | MO_ALIGN; } - tcg_temp_free_i32(tcg_ctx, tmp); + + addr = load_reg(s, rn); + taddr = gen_aa32_addr(s, addr, opc); tcg_temp_free_i32(tcg_ctx, addr); - store_reg(s, rd, tmp2); + + tmp = load_reg(s, rm); + tcg_gen_atomic_xchg_i32(tcg_ctx, tmp, taddr, tmp, + get_mem_index(s), opc); + tcg_temp_free(tcg_ctx, taddr); + store_reg(s, rd, tmp); } } } else {