From 36407da5864623f91dcd17f062a8ab0e984c3487 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 21 Mar 2020 16:35:04 -0400 Subject: [PATCH] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE When VHE is enabled, the exception level below EL2 is not EL1, but EL0, and so to identify the entry vector offset for exceptions targeting EL2 we need to look at the width of EL0, not of EL1. Backports commit cb092fbbaeb7b4e91b3f9c53150c8160f91577c7 from qemu --- qemu/target/arm/helper.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index f8d57d73..1a564445 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -8793,14 +8793,19 @@ static void arm_cpu_do_interrupt_aarch64_(CPUState *cs) * immediately lower than the target level is using AArch32 or AArch64 */ bool is_aa64 = false; + uint64_t hcr; switch (new_el) { case 3: is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; break; case 2: - is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0; - break; + hcr = arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { + is_aa64 = (hcr & HCR_RW) != 0; + break; + } + /* fall through */ case 1: is_aa64 = is_a64(env); break;