From 3b34b7f0f9b2968fa9b4df8102b6a2f09d11e2b4 Mon Sep 17 00:00:00 2001
From: Wei Huang <wei@redhat.com>
Date: Fri, 2 Mar 2018 07:50:04 -0500
Subject: [PATCH] target-arm: Add support for AArch64 PMU register
 PMXEVTYPER_EL0

In order to support Linux perf, which uses PMXEVTYPER register,
this patch adds read/write access support for PMXEVTYPER. The access
is CONSTRAINED UNPREDICTABLE when PMSELR is not 0x1f. Additionally
this patch adds support for PMXEVTYPER_EL0.

Backports commit fdb8665672ded05f650d18f8b62d5c8524b4385b from qemu
---
 qemu/target/arm/cpu.h    |  1 -
 qemu/target/arm/helper.c | 29 +++++++++++++++++++++++++----
 2 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h
index 94a2daa0..cab0927e 100644
--- a/qemu/target/arm/cpu.h
+++ b/qemu/target/arm/cpu.h
@@ -311,7 +311,6 @@ typedef struct CPUARMState {
         uint64_t c9_pmcr; /* performance monitor control register */
         uint64_t c9_pmcnten; /* perf monitor counter enables */
         uint32_t c9_pmovsr; /* perf monitor overflow status */
-        uint32_t c9_pmxevtyper; /* perf monitor event type */
         uint32_t c9_pmuserenr; /* perf monitor user enable */
         uint64_t c9_pmselr; /* perf monitor counter selection register */
         uint32_t c9_pminten; /* perf monitor interrupt enables */
diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c
index 455bdf2e..1c4e3acf 100644
--- a/qemu/target/arm/helper.c
+++ b/qemu/target/arm/helper.c
@@ -942,7 +942,25 @@ static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
                              uint64_t value)
 {
-    env->cp15.c9_pmxevtyper = value & 0xff;
+    /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
+     * PMSELR value is equal to or greater than the number of implemented
+     * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
+     */
+    if (env->cp15.c9_pmselr == 0x1f) {
+        pmccfiltr_write(env, ri, value);
+    }
+}
+
+static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
+     * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
+     */
+    if (env->cp15.c9_pmselr == 0x1f) {
+        return env->cp15.pmccfiltr_el0;
+    } else {
+        return 0;
+    }
 }
 
 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -1094,9 +1112,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { "PMCCFILTR_EL0", 0,14,15, 3,3,7, ARM_CP_STATE_AA64,
       ARM_CP_IO, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.pmccfiltr_el0), {0, 0},
       pmreg_access, NULL, pmccfiltr_write, },
-    { "PMXEVTYPER", 15,9,13, 0,0,1, 0,
-      0, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmxevtyper), {0, 0},
-      pmreg_access, NULL, pmxevtyper_write, NULL, raw_write },
+    { "PMXEVTYPER", 15,9,13, 0,0,1, 0, ARM_CP_NO_RAW,
+      PL0_RW, 0, NULL, 0, 0, {0, 0},
+      pmreg_access, pmxevtyper_read, pmxevtyper_write },
+    { "PMXEVTYPER_EL0", 0,9,13, 3,3,1, ARM_CP_STATE_AA64, ARM_CP_NO_RAW,
+      PL0_RW, 0, NULL, 0, 0, {0, 0},
+      pmreg_access, pmxevtyper_read, pmxevtyper_write },
     /* Unimplemented, RAZ/WI. */
     { "PMXEVCNTR", 15,9,13, 0,0,2, 0,
       ARM_CP_CONST, PL0_RW, 0, NULL, 0, 0, {0, 0},