From 3e35eee32751bff67cc64de3841847551f22559d Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 4 Mar 2018 21:01:48 -0500 Subject: [PATCH] target/arm: Make VTOR register banked for v8M Make the VTOR register banked if v8M security extensions are enabled. Backports commit 45db7ba681ede57113a67499840e69ee586bcdf2 from qemu --- qemu/target/arm/cpu.h | 2 +- qemu/target/arm/helper.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h index c2829415..1a6a8475 100644 --- a/qemu/target/arm/cpu.h +++ b/qemu/target/arm/cpu.h @@ -425,7 +425,7 @@ typedef struct CPUARMState { struct { uint32_t other_sp; - uint32_t vecbase; + uint32_t vecbase[2]; uint32_t basepri[2]; uint32_t control[2]; uint32_t ccr; /* Configuration and Control */ diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index e75faad1..734d2705 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -5325,7 +5325,7 @@ static uint32_t arm_v7m_load_vector(ARMCPU *cpu) CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; MemTxResult result; - hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4; + hwaddr vec = env->v7m.vecbase[env->v7m.secure] + env->v7m.exception * 4; uint32_t addr; addr = address_space_ldl(cs->as, vec,