From 3e786526cf9acba9fa12109e3d1d33b3328f8e05 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 25 Feb 2021 16:39:46 -0500 Subject: [PATCH] target/arm: Add gen_mte_checkN Replace existing uses of check_data_tbi in translate-a64.c that perform multiple logical memory access. Leave the helper blank for now to reduce the patch size. Backports commit 73ceeb0011b23bac8bd2c09ebe3c18d034aa69ce from qemu --- qemu/aarch64.h | 1 + qemu/aarch64eb.h | 1 + qemu/header_gen.py | 1 + qemu/target/arm/helper-a64.h | 1 + qemu/target/arm/mte_helper.c | 8 ++++ qemu/target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++------- 6 files changed, 68 insertions(+), 15 deletions(-) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index e436c136..3e6d488f 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -3584,6 +3584,7 @@ #define helper_msr_i_daifset helper_msr_i_daifset_aarch64 #define helper_msr_i_spsel helper_msr_i_spsel_aarch64 #define helper_mte_check1 helper_mte_check1_aarch64 +#define helper_mte_checkN helper_mte_checkN_aarch64 #define helper_neon_addlp_s16 helper_neon_addlp_s16_aarch64 #define helper_neon_addlp_s8 helper_neon_addlp_s8_aarch64 #define helper_neon_addlp_u16 helper_neon_addlp_u16_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index f77d6356..55f2a41b 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -3584,6 +3584,7 @@ #define helper_msr_i_daifset helper_msr_i_daifset_aarch64eb #define helper_msr_i_spsel helper_msr_i_spsel_aarch64eb #define helper_mte_check1 helper_mte_check1_aarch64eb +#define helper_mte_checkN helper_mte_checkN_aarch64eb #define helper_neon_addlp_s16 helper_neon_addlp_s16_aarch64eb #define helper_neon_addlp_s8 helper_neon_addlp_s8_aarch64eb #define helper_neon_addlp_u16 helper_neon_addlp_u16_aarch64eb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 34c0163f..bf96c51c 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3719,6 +3719,7 @@ aarch64_symbols = ( 'helper_msr_i_daifset', 'helper_msr_i_spsel', 'helper_mte_check1', + 'helper_mte_checkN', 'helper_neon_addlp_s16', 'helper_neon_addlp_s8', 'helper_neon_addlp_u16', diff --git a/qemu/target/arm/helper-a64.h b/qemu/target/arm/helper-a64.h index d99e2194..a1cf7bda 100644 --- a/qemu/target/arm/helper-a64.h +++ b/qemu/target/arm/helper-a64.h @@ -105,6 +105,7 @@ DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_3(mte_check1, TCG_CALL_NO_WG, i64, env, i32, i64) +DEF_HELPER_FLAGS_3(mte_checkN, TCG_CALL_NO_WG, i64, env, i32, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/qemu/target/arm/mte_helper.c b/qemu/target/arm/mte_helper.c index ec12768d..907a12b3 100644 --- a/qemu/target/arm/mte_helper.c +++ b/qemu/target/arm/mte_helper.c @@ -366,3 +366,11 @@ uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) { return ptr; } + +/* + * Perform an MTE checked access for multiple logical accesses. + */ +uint64_t HELPER(mte_checkN)(CPUARMState *env, uint32_t desc, uint64_t ptr) +{ + return ptr; +} diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 178f3faf..fc5e622c 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -422,6 +422,35 @@ static TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, false, get_mem_index(s)); } +/* + * For MTE, check multiple logical sequential accesses. + */ +static TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, + bool tag_checked, int log2_esize, int total_size) +{ + if (tag_checked && s->mte_active[0] && total_size != (1 << log2_esize)) { + TCGv_i32 tcg_desc; + TCGv_i64 ret; + int desc = 0; + TCGContext *tcg_ctx = s->uc->tcg_ctx; + + desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); + desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); + desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); + desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); + desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_esize); + desc = FIELD_DP32(desc, MTEDESC, TSIZE, total_size); + tcg_desc = tcg_const_i32(tcg_ctx, desc); + + ret = new_tmp_a64(s); + gen_helper_mte_checkN(tcg_ctx, ret, tcg_ctx->cpu_env, tcg_desc, addr); + tcg_temp_free_i32(tcg_ctx, tcg_desc); + + return ret; + } + return gen_mte_check1(s, addr, is_write, tag_checked, log2_esize); +} + typedef struct DisasCompare64 { TCGCond cond; TCGv_i64 value; @@ -3034,7 +3063,10 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) } } - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = gen_mte_checkN(s, dirty_addr, !is_load, + (wback || rn != 31) && !set_tag, + size, 2 << size); + if (is_vector) { if (is_load) { do_fp_ld(s, rt, clean_addr, size); @@ -3708,7 +3740,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; MemOp endian = s->be_data; - int ebytes; /* bytes per element */ + int total; /* total bytes */ int elements; /* elements per vector */ int rpt; /* num iterations */ int selem; /* structure elements */ @@ -3778,18 +3810,26 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) endian = MO_LE; } - /* Consecutive little-endian elements from a single register + total = rpt * selem * (is_q ? 16 : 8); + tcg_rn = cpu_reg_sp(s, rn); + + /* + * Issue the MTE check vs the logical repeat count, before we + * promote consecutive little-endian elements below. + */ + clean_addr = gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != 31, + size, total); + + /* + * Consecutive little-endian elements from a single register * can be promoted to a larger little-endian operation. */ if (selem == 1 && endian == MO_LE) { size = 3; } - ebytes = 1 << size; - elements = (is_q ? 16 : 8) / ebytes; + elements = (is_q ? 16 : 8) >> size; - tcg_rn = cpu_reg_sp(s, rn); - clean_addr = clean_data_tbi(s, tcg_rn); - tcg_ebytes = tcg_const_i64(tcg_ctx, ebytes); + tcg_ebytes = tcg_const_i64(tcg_ctx, 1 << size); for (r = 0; r < rpt; r++) { int e; @@ -3824,7 +3864,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) if (is_postidx) { if (rm == 31) { - tcg_gen_addi_i64(tcg_ctx, tcg_rn, tcg_rn, rpt * elements * selem * ebytes); + tcg_gen_addi_i64(tcg_ctx, tcg_rn, tcg_rn, total); } else { tcg_gen_add_i64(tcg_ctx, tcg_rn, tcg_rn, cpu_reg(s, rm)); } @@ -3871,7 +3911,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) int selem = (extract32(opc, 0, 1) << 1 | R) + 1; bool replicate = false; int index = is_q << 3 | S << 2 | size; - int ebytes, xs; + int xs, total; TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; if (extract32(insn, 31, 1)) { @@ -3925,16 +3965,17 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) return; } - ebytes = 1 << scale; - if (rn == 31) { gen_check_sp_alignment(s); } + total = selem << scale; tcg_rn = cpu_reg_sp(s, rn); - clean_addr = clean_data_tbi(s, tcg_rn); - tcg_ebytes = tcg_const_i64(tcg_ctx, ebytes); + clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31, + scale, total); + + tcg_ebytes = tcg_const_i64(tcg_ctx, 1 << scale); for (xs = 0; xs < selem; xs++) { if (replicate) { /* Load and replicate to all elements */ @@ -3961,7 +4002,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) if (is_postidx) { if (rm == 31) { - tcg_gen_addi_i64(tcg_ctx, tcg_rn, tcg_rn, selem * ebytes); + tcg_gen_addi_i64(tcg_ctx, tcg_rn, tcg_rn, total); } else { tcg_gen_add_i64(tcg_ctx, tcg_rn, tcg_rn, cpu_reg(s, rm)); }