From 3fe4cf353c33ff2d2269f8a1bd00034713315cd0 Mon Sep 17 00:00:00 2001
From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Date: Tue, 19 Mar 2019 04:55:50 -0400
Subject: [PATCH] target/riscv: Remove gen_jalr()

trans_jalr() is the only caller, so move the code into trans_jalr().

Backports commit 9e92c57d834cd50ab088d75510c3c720878eef13 from qemu
---
 qemu/target/riscv/insn_trans/trans_rvi.inc.c | 30 ++++++++++++++-
 qemu/target/riscv/translate.c                | 40 --------------------
 2 files changed, 29 insertions(+), 41 deletions(-)

diff --git a/qemu/target/riscv/insn_trans/trans_rvi.inc.c b/qemu/target/riscv/insn_trans/trans_rvi.inc.c
index 22c873a2..5d107fc3 100644
--- a/qemu/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/qemu/target/riscv/insn_trans/trans_rvi.inc.c
@@ -44,7 +44,35 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
 
 static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
 {
-    gen_jalr(ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+
+    /* no chaining with JALR */
+    TCGLabel *misaligned = NULL;
+    TCGv t0 = tcg_temp_new(tcg_ctx);
+
+
+    gen_get_gpr(ctx, tcg_ctx->cpu_pc_risc, a->rs1);
+    tcg_gen_addi_tl(tcg_ctx, tcg_ctx->cpu_pc_risc, tcg_ctx->cpu_pc_risc, a->imm);
+    tcg_gen_andi_tl(tcg_ctx, tcg_ctx->cpu_pc_risc, tcg_ctx->cpu_pc_risc, (target_ulong)-2);
+
+    if (!has_ext(ctx, RVC)) {
+        misaligned = gen_new_label(tcg_ctx);
+        tcg_gen_andi_tl(tcg_ctx, t0, tcg_ctx->cpu_pc_risc, 0x2);
+        tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, 0x0, misaligned);
+    }
+
+    if (a->rd != 0) {
+        tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr_risc[a->rd], ctx->pc_succ_insn);
+    }
+    tcg_gen_lookup_and_goto_ptr(tcg_ctx);
+
+    if (misaligned) {
+        gen_set_label(tcg_ctx, misaligned);
+        gen_exception_inst_addr_mis(ctx);
+    }
+    ctx->base.is_jmp = DISAS_NORETURN;
+
+    tcg_temp_free(tcg_ctx, t0);
     return true;
 }
 
diff --git a/qemu/target/riscv/translate.c b/qemu/target/riscv/translate.c
index 5fb559be..2725c767 100644
--- a/qemu/target/riscv/translate.c
+++ b/qemu/target/riscv/translate.c
@@ -547,46 +547,6 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_jalr(DisasContext *ctx, uint32_t opc, int rd, int rs1,
-                     target_long imm)
-{
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
-
-    /* no chaining with JALR */
-    TCGLabel *misaligned = NULL;
-    TCGv t0 = tcg_temp_new(tcg_ctx);
-
-    switch (opc) {
-    case OPC_RISC_JALR:
-        gen_get_gpr(ctx, tcg_ctx->cpu_pc_risc, rs1);
-        tcg_gen_addi_tl(tcg_ctx, tcg_ctx->cpu_pc_risc, tcg_ctx->cpu_pc_risc, imm);
-        tcg_gen_andi_tl(tcg_ctx, tcg_ctx->cpu_pc_risc, tcg_ctx->cpu_pc_risc, (target_ulong)-2);
-
-        if (!has_ext(ctx, RVC)) {
-            misaligned = gen_new_label(tcg_ctx);
-            tcg_gen_andi_tl(tcg_ctx, t0, tcg_ctx->cpu_pc_risc, 0x2);
-            tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, 0x0, misaligned);
-        }
-
-        if (rd != 0) {
-            tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr_risc[rd], ctx->pc_succ_insn);
-        }
-        tcg_gen_lookup_and_goto_ptr(tcg_ctx);
-
-        if (misaligned) {
-            gen_set_label(tcg_ctx, misaligned);
-            gen_exception_inst_addr_mis(ctx);
-        }
-        ctx->base.is_jmp = DISAS_NORETURN;
-        break;
-
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-    tcg_temp_free(tcg_ctx, t0);
-}
-
 static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
                        target_long bimm)
 {