diff --git a/qemu/aarch64.h b/qemu/aarch64.h
index 6beaf65b..cb89f218 100644
--- a/qemu/aarch64.h
+++ b/qemu/aarch64.h
@@ -3340,6 +3340,7 @@
 #define arm64_reg_reset arm64_reg_reset_aarch64
 #define arm64_reg_write arm64_reg_write_aarch64
 #define arm64_release arm64_release_aarch64
+#define arm_v7m_mmu_idx_all arm_v7m_mmu_idx_all_aarch64
 #define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_aarch64
 #define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_aarch64
 #define arm_hcr_el2_eff arm_hcr_el2_eff_aarch64
diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h
index d2056df3..053dc28b 100644
--- a/qemu/aarch64eb.h
+++ b/qemu/aarch64eb.h
@@ -3340,6 +3340,7 @@
 #define arm64_reg_reset arm64_reg_reset_aarch64eb
 #define arm64_reg_write arm64_reg_write_aarch64eb
 #define arm64_release arm64_release_aarch64eb
+#define arm_v7m_mmu_idx_all arm_v7m_mmu_idx_all_aarch64eb
 #define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_aarch64eb
 #define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_aarch64eb
 #define arm_hcr_el2_eff arm_hcr_el2_eff_aarch64eb
diff --git a/qemu/arm.h b/qemu/arm.h
index e4b75f9b..cefb7ead 100644
--- a/qemu/arm.h
+++ b/qemu/arm.h
@@ -3331,6 +3331,7 @@
 #define aa64_va_parameters aa64_va_parameters_arm
 #define aa64_va_parameters_both aa64_va_parameters_both_arm
 #define aarch64_translator_ops aarch64_translator_ops_arm
+#define arm_v7m_mmu_idx_all arm_v7m_mmu_idx_all_arm
 #define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_arm
 #define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_arm
 #define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_arm
diff --git a/qemu/armeb.h b/qemu/armeb.h
index 96c1644f..46efb048 100644
--- a/qemu/armeb.h
+++ b/qemu/armeb.h
@@ -3331,6 +3331,7 @@
 #define aa64_va_parameters aa64_va_parameters_armeb
 #define aa64_va_parameters_both aa64_va_parameters_both_armeb
 #define aarch64_translator_ops aarch64_translator_ops_armeb
+#define arm_v7m_mmu_idx_all arm_v7m_mmu_idx_all_armeb
 #define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_armeb
 #define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_armeb
 #define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_armeb
diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index 895bf3b8..06cdefad 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -3340,6 +3340,7 @@ arm_symbols = (
     'aa64_va_parameters',
     'aa64_va_parameters_both',
     'aarch64_translator_ops',
+    'arm_v7m_mmu_idx_all',
     'arm_v7m_mmu_idx_for_secstate',
     'arm_v7m_mmu_idx_for_secstate_and_priv',
     'ARM_REGS_STORAGE_SIZE',
@@ -3394,6 +3395,7 @@ aarch64_symbols = (
     'arm64_reg_reset',
     'arm64_reg_write',
     'arm64_release',
+    'arm_v7m_mmu_idx_all',
     'arm_v7m_mmu_idx_for_secstate',
     'arm_v7m_mmu_idx_for_secstate_and_priv',
     'arm_hcr_el2_eff',
diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h
index 6a77123e..3250c0e6 100644
--- a/qemu/target/arm/cpu.h
+++ b/qemu/target/arm/cpu.h
@@ -2868,6 +2868,13 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
     }
 }
 
+/*
+ * Return the MMU index for a v7M CPU with all relevant information
+ * manually specified.
+ */
+ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+                              bool secstate, bool priv, bool negpri);
+
 /* Return the MMU index for a v7M CPU in the specified security and
  * privilege state.
  */
diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c
index f697ce2d..d254544c 100644
--- a/qemu/target/arm/helper.c
+++ b/qemu/target/arm/helper.c
@@ -13023,8 +13023,8 @@ int fp_exception_el(CPUARMState *env, int cur_el)
     return 0;
 }
 
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
-                                                bool secstate, bool priv)
+ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+                              bool secstate, bool priv, bool negpri)
 {
     ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
 
@@ -13032,12 +13032,9 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
         mmu_idx |= ARM_MMU_IDX_M_PRIV;
     }
 
-// Unicorn: disabled
-#if 0
-    if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {
+    if (negpri) {
         mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
     }
-#endif
 
     if (secstate) {
         mmu_idx |= ARM_MMU_IDX_M_S;
@@ -13046,6 +13043,14 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
     return mmu_idx;
 }
 
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+                                                bool secstate, bool priv)
+{
+    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
+
+    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
+}
+
 /* Return the MMU index for a v7M CPU in the specified security state */
 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
 {