From 40afe1200829cb07a0c0d07074975bc6191a3f1d Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Sun, 22 Mar 2020 01:01:06 -0400 Subject: [PATCH] target/riscv: Add the Hypervisor extension Backports commit af1fa0039c799a350bcde07b3d8a71dfde07d11b from qemu --- qemu/target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h index b4377f41..bdd7bc90 100644 --- a/qemu/target/riscv/cpu.h +++ b/qemu/target/riscv/cpu.h @@ -71,6 +71,7 @@ #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') +#define RVH RV('H') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there