From 4114fb2c0e6e1d4cdc375d9d90edb2df5a8fb670 Mon Sep 17 00:00:00 2001 From: Nick Reilly Date: Fri, 2 Mar 2018 10:38:11 -0500 Subject: [PATCH] Add missing fp_access_check() to aarch64 crypto instructions The aarch64 crypto instructions for AES and SHA are missing the check for if the FPU is enabled. Backports commit a4f5c5b72380deeccd53a6890ea3782f10ca8054 from qemu --- qemu/target/arm/translate-a64.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 1c0d85e3..b64851ce 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -11079,6 +11079,10 @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn) return; } + if (!fp_access_check(s)) { + return; + } + /* Note that we convert the Vx register indexes into the * index within the vfp.regs[] array, so we can share the * helper with the AArch32 instructions. @@ -11144,6 +11148,10 @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) return; } + if (!fp_access_check(s)) { + return; + } + tcg_rd_regno = tcg_const_i32(tcg_ctx, rd << 1); tcg_rn_regno = tcg_const_i32(tcg_ctx, rn << 1); tcg_rm_regno = tcg_const_i32(tcg_ctx, rm << 1); @@ -11208,6 +11216,10 @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) return; } + if (!fp_access_check(s)) { + return; + } + tcg_rd_regno = tcg_const_i32(tcg_ctx, rd << 1); tcg_rn_regno = tcg_const_i32(tcg_ctx, rn << 1);