From 4128f3b2597a99e820ab4ddae4d6605b7f6145fc Mon Sep 17 00:00:00 2001 From: MerryMage Date: Thu, 11 Jan 2018 18:28:59 +0000 Subject: [PATCH] aarch64: Add FPCR and FPSR registers --- include/unicorn/arm64.h | 4 ++++ qemu/target-arm/unicorn_aarch64.c | 12 ++++++++++++ 2 files changed, 16 insertions(+) diff --git a/include/unicorn/arm64.h b/include/unicorn/arm64.h index 130d605e..31ba2499 100644 --- a/include/unicorn/arm64.h +++ b/include/unicorn/arm64.h @@ -292,6 +292,10 @@ typedef enum uc_arm64_reg { UC_ARM64_REG_TPIDR_EL1, UC_ARM64_REG_PSTATE, // PSTATE pseudoregister + + //> floating point control and status registers + UC_ARM64_REG_FPCR, + UC_ARM64_REG_FPSR, UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers diff --git a/qemu/target-arm/unicorn_aarch64.c b/qemu/target-arm/unicorn_aarch64.c index e255f306..0e92a378 100644 --- a/qemu/target-arm/unicorn_aarch64.c +++ b/qemu/target-arm/unicorn_aarch64.c @@ -109,6 +109,12 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co case UC_ARM64_REG_PSTATE: *(uint32_t *)value = pstate_read(&ARM_CPU(uc, mycpu)->env); break; + case UC_ARM64_REG_FPCR: + *(uint32_t *)value = vfp_get_fpcr(&ARM_CPU(uc, mycpu)->env); + break; + case UC_ARM64_REG_FPSR: + *(uint32_t *)value = vfp_get_fpsr(&ARM_CPU(uc, mycpu)->env); + break; } } } @@ -180,6 +186,12 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, case UC_ARM64_REG_PSTATE: pstate_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value); break; + case UC_ARM64_REG_FPCR: + vfp_set_fpcr(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value); + break; + case UC_ARM64_REG_FPSR: + vfp_set_fpsr(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value); + break; } } }