From 451683ee79d15847e8b69a94feac745753e8f7e9 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 15 May 2020 22:10:23 -0400 Subject: [PATCH] target/arm: Vectorize SABA/UABA Include 64-bit element size in preparation for SVE2. Backports commit cfdb2c0c95ae9205b0dd7f0f5e970cdec50fef20 from qemu --- qemu/aarch64.h | 16 ++-- qemu/aarch64eb.h | 16 ++-- qemu/arm.h | 16 ++-- qemu/armeb.h | 16 ++-- qemu/header_gen.py | 26 +++++-- qemu/m68k.h | 6 -- qemu/mips.h | 6 -- qemu/mips64.h | 6 -- qemu/mips64el.h | 6 -- qemu/mipsel.h | 6 -- qemu/powerpc.h | 6 -- qemu/riscv32.h | 6 -- qemu/riscv64.h | 6 -- qemu/sparc.h | 6 -- qemu/sparc64.h | 6 -- qemu/target/arm/helper.h | 17 ++-- qemu/target/arm/neon_helper.c | 10 --- qemu/target/arm/translate-a64.c | 17 ++-- qemu/target/arm/translate.c | 134 ++++++++++++++++++++++++++++++-- qemu/target/arm/translate.h | 5 ++ qemu/target/arm/vec_helper.c | 24 ++++++ qemu/x86_64.h | 6 -- 22 files changed, 234 insertions(+), 129 deletions(-) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 6fb69de2..cedc63f0 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_aarch64 #define helper_msr_banked helper_msr_banked_aarch64 #define helper_neon_abd_f32 helper_neon_abd_f32_aarch64 -#define helper_neon_abd_s16 helper_neon_abd_s16_aarch64 -#define helper_neon_abd_s32 helper_neon_abd_s32_aarch64 -#define helper_neon_abd_s8 helper_neon_abd_s8_aarch64 -#define helper_neon_abd_u16 helper_neon_abd_u16_aarch64 -#define helper_neon_abd_u32 helper_neon_abd_u32_aarch64 -#define helper_neon_abd_u8 helper_neon_abd_u8_aarch64 #define helper_neon_abdl_s16 helper_neon_abdl_s16_aarch64 #define helper_neon_abdl_s32 helper_neon_abdl_s32_aarch64 #define helper_neon_abdl_s64 helper_neon_abdl_s64_aarch64 @@ -3425,6 +3419,7 @@ #define gen_gvec_cmtst gen_gvec_cmtst_aarch64 #define gen_gvec_mla gen_gvec_mla_aarch64 #define gen_gvec_mls gen_gvec_mls_aarch64 +#define gen_gvec_saba gen_gvec_saba_aarch64 #define gen_gvec_sabd gen_gvec_sabd_aarch64 #define gen_gvec_sli gen_gvec_sli_aarch64 #define gen_gvec_sqadd_qc gen_gvec_sqadd_qc_aarch64 @@ -3436,6 +3431,7 @@ #define gen_gvec_srsra gen_gvec_srsra_aarch64 #define gen_gvec_sshl gen_gvec_sshl_aarch64 #define gen_gvec_ssra gen_gvec_ssra_aarch64 +#define gen_gvec_uaba gen_gvec_uaba_aarch64 #define gen_gvec_uabd gen_gvec_uabd_aarch64 #define gen_gvec_uqadd_qc gen_gvec_uqadd_qc_aarch64 #define gen_gvec_uqsub_qc gen_gvec_uqsub_qc_aarch64 @@ -3497,6 +3493,10 @@ #define helper_gvec_rsqrts_d helper_gvec_rsqrts_d_aarch64 #define helper_gvec_rsqrts_h helper_gvec_rsqrts_h_aarch64 #define helper_gvec_rsqrts_s helper_gvec_rsqrts_s_aarch64 +#define helper_gvec_saba_b helper_gvec_saba_b_aarch64 +#define helper_gvec_saba_d helper_gvec_saba_d_aarch64 +#define helper_gvec_saba_h helper_gvec_saba_h_aarch64 +#define helper_gvec_saba_s helper_gvec_saba_s_aarch64 #define helper_gvec_sabd_b helper_gvec_sabd_b_aarch64 #define helper_gvec_sabd_d helper_gvec_sabd_d_aarch64 #define helper_gvec_sabd_h helper_gvec_sabd_h_aarch64 @@ -3521,6 +3521,10 @@ #define helper_gvec_ssra_d helper_gvec_ssra_d_aarch64 #define helper_gvec_ssra_h helper_gvec_ssra_h_aarch64 #define helper_gvec_ssra_s helper_gvec_ssra_s_aarch64 +#define helper_gvec_uaba_b helper_gvec_uaba_b_aarch64 +#define helper_gvec_uaba_d helper_gvec_uaba_d_aarch64 +#define helper_gvec_uaba_h helper_gvec_uaba_h_aarch64 +#define helper_gvec_uaba_s helper_gvec_uaba_s_aarch64 #define helper_gvec_uabd_b helper_gvec_uabd_b_aarch64 #define helper_gvec_uabd_d helper_gvec_uabd_d_aarch64 #define helper_gvec_uabd_h helper_gvec_uabd_h_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index ba650363..6c6673d4 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_aarch64eb #define helper_msr_banked helper_msr_banked_aarch64eb #define helper_neon_abd_f32 helper_neon_abd_f32_aarch64eb -#define helper_neon_abd_s16 helper_neon_abd_s16_aarch64eb -#define helper_neon_abd_s32 helper_neon_abd_s32_aarch64eb -#define helper_neon_abd_s8 helper_neon_abd_s8_aarch64eb -#define helper_neon_abd_u16 helper_neon_abd_u16_aarch64eb -#define helper_neon_abd_u32 helper_neon_abd_u32_aarch64eb -#define helper_neon_abd_u8 helper_neon_abd_u8_aarch64eb #define helper_neon_abdl_s16 helper_neon_abdl_s16_aarch64eb #define helper_neon_abdl_s32 helper_neon_abdl_s32_aarch64eb #define helper_neon_abdl_s64 helper_neon_abdl_s64_aarch64eb @@ -3425,6 +3419,7 @@ #define gen_gvec_cmtst gen_gvec_cmtst_aarch64eb #define gen_gvec_mla gen_gvec_mla_aarch64eb #define gen_gvec_mls gen_gvec_mls_aarch64eb +#define gen_gvec_saba gen_gvec_saba_aarch64eb #define gen_gvec_sabd gen_gvec_sabd_aarch64eb #define gen_gvec_sli gen_gvec_sli_aarch64eb #define gen_gvec_sqadd_qc gen_gvec_sqadd_qc_aarch64eb @@ -3436,6 +3431,7 @@ #define gen_gvec_srsra gen_gvec_srsra_aarch64eb #define gen_gvec_sshl gen_gvec_sshl_aarch64eb #define gen_gvec_ssra gen_gvec_ssra_aarch64eb +#define gen_gvec_uaba gen_gvec_uaba_aarch64eb #define gen_gvec_uabd gen_gvec_uabd_aarch64eb #define gen_gvec_uqadd_qc gen_gvec_uqadd_qc_aarch64eb #define gen_gvec_uqsub_qc gen_gvec_uqsub_qc_aarch64eb @@ -3497,6 +3493,10 @@ #define helper_gvec_rsqrts_d helper_gvec_rsqrts_d_aarch64eb #define helper_gvec_rsqrts_h helper_gvec_rsqrts_h_aarch64eb #define helper_gvec_rsqrts_s helper_gvec_rsqrts_s_aarch64eb +#define helper_gvec_saba_b helper_gvec_saba_b_aarch64eb +#define helper_gvec_saba_d helper_gvec_saba_d_aarch64eb +#define helper_gvec_saba_h helper_gvec_saba_h_aarch64eb +#define helper_gvec_saba_s helper_gvec_saba_s_aarch64eb #define helper_gvec_sabd_b helper_gvec_sabd_b_aarch64eb #define helper_gvec_sabd_d helper_gvec_sabd_d_aarch64eb #define helper_gvec_sabd_h helper_gvec_sabd_h_aarch64eb @@ -3521,6 +3521,10 @@ #define helper_gvec_ssra_d helper_gvec_ssra_d_aarch64eb #define helper_gvec_ssra_h helper_gvec_ssra_h_aarch64eb #define helper_gvec_ssra_s helper_gvec_ssra_s_aarch64eb +#define helper_gvec_uaba_b helper_gvec_uaba_b_aarch64eb +#define helper_gvec_uaba_d helper_gvec_uaba_d_aarch64eb +#define helper_gvec_uaba_h helper_gvec_uaba_h_aarch64eb +#define helper_gvec_uaba_s helper_gvec_uaba_s_aarch64eb #define helper_gvec_uabd_b helper_gvec_uabd_b_aarch64eb #define helper_gvec_uabd_d helper_gvec_uabd_d_aarch64eb #define helper_gvec_uabd_h helper_gvec_uabd_h_aarch64eb diff --git a/qemu/arm.h b/qemu/arm.h index b52325a0..899634b7 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_arm #define helper_msr_banked helper_msr_banked_arm #define helper_neon_abd_f32 helper_neon_abd_f32_arm -#define helper_neon_abd_s16 helper_neon_abd_s16_arm -#define helper_neon_abd_s32 helper_neon_abd_s32_arm -#define helper_neon_abd_s8 helper_neon_abd_s8_arm -#define helper_neon_abd_u16 helper_neon_abd_u16_arm -#define helper_neon_abd_u32 helper_neon_abd_u32_arm -#define helper_neon_abd_u8 helper_neon_abd_u8_arm #define helper_neon_abdl_s16 helper_neon_abdl_s16_arm #define helper_neon_abdl_s32 helper_neon_abdl_s32_arm #define helper_neon_abdl_s64 helper_neon_abdl_s64_arm @@ -3410,6 +3404,7 @@ #define gen_gvec_cmtst gen_gvec_cmtst_arm #define gen_gvec_mla gen_gvec_mla_arm #define gen_gvec_mls gen_gvec_mls_arm +#define gen_gvec_saba gen_gvec_saba_arm #define gen_gvec_sabd gen_gvec_sabd_arm #define gen_gvec_sli gen_gvec_sli_arm #define gen_gvec_sqadd_qc gen_gvec_sqadd_qc_arm @@ -3421,6 +3416,7 @@ #define gen_gvec_srsra gen_gvec_srsra_arm #define gen_gvec_sshl gen_gvec_sshl_arm #define gen_gvec_ssra gen_gvec_ssra_arm +#define gen_gvec_uaba gen_gvec_uaba_arm #define gen_gvec_uabd gen_gvec_uabd_arm #define gen_gvec_uqadd_qc gen_gvec_uqadd_qc_arm #define gen_gvec_uqsub_qc gen_gvec_uqsub_qc_arm @@ -3434,6 +3430,10 @@ #define gen_ushl_i32 gen_ushl_i32_arm #define gen_ushl_i64 gen_ushl_i64_arm #define helper_fjcvtzs helper_fjcvtzs_arm +#define helper_gvec_saba_b helper_gvec_saba_b_arm +#define helper_gvec_saba_d helper_gvec_saba_d_arm +#define helper_gvec_saba_h helper_gvec_saba_h_arm +#define helper_gvec_saba_s helper_gvec_saba_s_arm #define helper_gvec_sabd_b helper_gvec_sabd_b_arm #define helper_gvec_sabd_d helper_gvec_sabd_d_arm #define helper_gvec_sabd_h helper_gvec_sabd_h_arm @@ -3458,6 +3458,10 @@ #define helper_gvec_ssra_d helper_gvec_ssra_d_arm #define helper_gvec_ssra_h helper_gvec_ssra_h_arm #define helper_gvec_ssra_s helper_gvec_ssra_s_arm +#define helper_gvec_uaba_b helper_gvec_uaba_b_arm +#define helper_gvec_uaba_d helper_gvec_uaba_d_arm +#define helper_gvec_uaba_h helper_gvec_uaba_h_arm +#define helper_gvec_uaba_s helper_gvec_uaba_s_arm #define helper_gvec_uabd_b helper_gvec_uabd_b_arm #define helper_gvec_uabd_d helper_gvec_uabd_d_arm #define helper_gvec_uabd_h helper_gvec_uabd_h_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index 57e465d7..cf364fbf 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_armeb #define helper_msr_banked helper_msr_banked_armeb #define helper_neon_abd_f32 helper_neon_abd_f32_armeb -#define helper_neon_abd_s16 helper_neon_abd_s16_armeb -#define helper_neon_abd_s32 helper_neon_abd_s32_armeb -#define helper_neon_abd_s8 helper_neon_abd_s8_armeb -#define helper_neon_abd_u16 helper_neon_abd_u16_armeb -#define helper_neon_abd_u32 helper_neon_abd_u32_armeb -#define helper_neon_abd_u8 helper_neon_abd_u8_armeb #define helper_neon_abdl_s16 helper_neon_abdl_s16_armeb #define helper_neon_abdl_s32 helper_neon_abdl_s32_armeb #define helper_neon_abdl_s64 helper_neon_abdl_s64_armeb @@ -3410,6 +3404,7 @@ #define gen_gvec_cmtst gen_gvec_cmtst_armeb #define gen_gvec_mla gen_gvec_mla_armeb #define gen_gvec_mls gen_gvec_mls_armeb +#define gen_gvec_saba gen_gvec_saba_armeb #define gen_gvec_sabd gen_gvec_sabd_armeb #define gen_gvec_sli gen_gvec_sli_armeb #define gen_gvec_sqadd_qc gen_gvec_sqadd_qc_armeb @@ -3421,6 +3416,7 @@ #define gen_gvec_srsra gen_gvec_srsra_armeb #define gen_gvec_sshl gen_gvec_sshl_armeb #define gen_gvec_ssra gen_gvec_ssra_armeb +#define gen_gvec_uaba gen_gvec_uaba_armeb #define gen_gvec_uabd gen_gvec_uabd_armeb #define gen_gvec_uqadd_qc gen_gvec_uqadd_qc_armeb #define gen_gvec_uqsub_qc gen_gvec_uqsub_qc_armeb @@ -3434,6 +3430,10 @@ #define gen_ushl_i32 gen_ushl_i32_armeb #define gen_ushl_i64 gen_ushl_i64_armeb #define helper_fjcvtzs helper_fjcvtzs_armeb +#define helper_gvec_saba_b helper_gvec_saba_b_armeb +#define helper_gvec_saba_d helper_gvec_saba_d_armeb +#define helper_gvec_saba_h helper_gvec_saba_h_armeb +#define helper_gvec_saba_s helper_gvec_saba_s_armeb #define helper_gvec_sabd_b helper_gvec_sabd_b_armeb #define helper_gvec_sabd_d helper_gvec_sabd_d_armeb #define helper_gvec_sabd_h helper_gvec_sabd_h_armeb @@ -3458,6 +3458,10 @@ #define helper_gvec_ssra_d helper_gvec_ssra_d_armeb #define helper_gvec_ssra_h helper_gvec_ssra_h_armeb #define helper_gvec_ssra_s helper_gvec_ssra_s_armeb +#define helper_gvec_uaba_b helper_gvec_uaba_b_armeb +#define helper_gvec_uaba_d helper_gvec_uaba_d_armeb +#define helper_gvec_uaba_h helper_gvec_uaba_h_armeb +#define helper_gvec_uaba_s helper_gvec_uaba_s_armeb #define helper_gvec_uabd_b helper_gvec_uabd_b_armeb #define helper_gvec_uabd_d helper_gvec_uabd_d_armeb #define helper_gvec_uabd_h helper_gvec_uabd_h_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index c490243b..e431ab72 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -1473,12 +1473,6 @@ symbols = ( 'helper_msa_st_w', 'helper_msr_banked', 'helper_neon_abd_f32', - 'helper_neon_abd_s16', - 'helper_neon_abd_s32', - 'helper_neon_abd_s8', - 'helper_neon_abd_u16', - 'helper_neon_abd_u32', - 'helper_neon_abd_u8', 'helper_neon_abdl_s16', 'helper_neon_abdl_s32', 'helper_neon_abdl_s64', @@ -3419,6 +3413,7 @@ arm_symbols = ( 'gen_gvec_cmtst', 'gen_gvec_mla', 'gen_gvec_mls', + 'gen_gvec_saba', 'gen_gvec_sabd', 'gen_gvec_sli', 'gen_gvec_sqadd_qc', @@ -3430,6 +3425,7 @@ arm_symbols = ( 'gen_gvec_srsra', 'gen_gvec_sshl', 'gen_gvec_ssra', + 'gen_gvec_uaba', 'gen_gvec_uabd', 'gen_gvec_uqadd_qc', 'gen_gvec_uqsub_qc', @@ -3443,6 +3439,10 @@ arm_symbols = ( 'gen_ushl_i32', 'gen_ushl_i64', 'helper_fjcvtzs', + 'helper_gvec_saba_b', + 'helper_gvec_saba_d', + 'helper_gvec_saba_h', + 'helper_gvec_saba_s', 'helper_gvec_sabd_b', 'helper_gvec_sabd_d', 'helper_gvec_sabd_h', @@ -3467,6 +3467,10 @@ arm_symbols = ( 'helper_gvec_ssra_d', 'helper_gvec_ssra_h', 'helper_gvec_ssra_s', + 'helper_gvec_uaba_b', + 'helper_gvec_uaba_d', + 'helper_gvec_uaba_h', + 'helper_gvec_uaba_s', 'helper_gvec_uabd_b', 'helper_gvec_uabd_d', 'helper_gvec_uabd_h', @@ -3548,6 +3552,7 @@ aarch64_symbols = ( 'gen_gvec_cmtst', 'gen_gvec_mla', 'gen_gvec_mls', + 'gen_gvec_saba', 'gen_gvec_sabd', 'gen_gvec_sli', 'gen_gvec_sqadd_qc', @@ -3559,6 +3564,7 @@ aarch64_symbols = ( 'gen_gvec_srsra', 'gen_gvec_sshl', 'gen_gvec_ssra', + 'gen_gvec_uaba', 'gen_gvec_uabd', 'gen_gvec_uqadd_qc', 'gen_gvec_uqsub_qc', @@ -3620,6 +3626,10 @@ aarch64_symbols = ( 'helper_gvec_rsqrts_d', 'helper_gvec_rsqrts_h', 'helper_gvec_rsqrts_s', + 'helper_gvec_saba_b', + 'helper_gvec_saba_d', + 'helper_gvec_saba_h', + 'helper_gvec_saba_s', 'helper_gvec_sabd_b', 'helper_gvec_sabd_d', 'helper_gvec_sabd_h', @@ -3644,6 +3654,10 @@ aarch64_symbols = ( 'helper_gvec_ssra_d', 'helper_gvec_ssra_h', 'helper_gvec_ssra_s', + 'helper_gvec_uaba_b', + 'helper_gvec_uaba_d', + 'helper_gvec_uaba_h', + 'helper_gvec_uaba_s', 'helper_gvec_uabd_b', 'helper_gvec_uabd_d', 'helper_gvec_uabd_h', diff --git a/qemu/m68k.h b/qemu/m68k.h index 1128bdc1..46a435b0 100644 --- a/qemu/m68k.h +++ b/qemu/m68k.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_m68k #define helper_msr_banked helper_msr_banked_m68k #define helper_neon_abd_f32 helper_neon_abd_f32_m68k -#define helper_neon_abd_s16 helper_neon_abd_s16_m68k -#define helper_neon_abd_s32 helper_neon_abd_s32_m68k -#define helper_neon_abd_s8 helper_neon_abd_s8_m68k -#define helper_neon_abd_u16 helper_neon_abd_u16_m68k -#define helper_neon_abd_u32 helper_neon_abd_u32_m68k -#define helper_neon_abd_u8 helper_neon_abd_u8_m68k #define helper_neon_abdl_s16 helper_neon_abdl_s16_m68k #define helper_neon_abdl_s32 helper_neon_abdl_s32_m68k #define helper_neon_abdl_s64 helper_neon_abdl_s64_m68k diff --git a/qemu/mips.h b/qemu/mips.h index c5c28918..78f77c0b 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_mips #define helper_msr_banked helper_msr_banked_mips #define helper_neon_abd_f32 helper_neon_abd_f32_mips -#define helper_neon_abd_s16 helper_neon_abd_s16_mips -#define helper_neon_abd_s32 helper_neon_abd_s32_mips -#define helper_neon_abd_s8 helper_neon_abd_s8_mips -#define helper_neon_abd_u16 helper_neon_abd_u16_mips -#define helper_neon_abd_u32 helper_neon_abd_u32_mips -#define helper_neon_abd_u8 helper_neon_abd_u8_mips #define helper_neon_abdl_s16 helper_neon_abdl_s16_mips #define helper_neon_abdl_s32 helper_neon_abdl_s32_mips #define helper_neon_abdl_s64 helper_neon_abdl_s64_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index 4427f34b..b8c27d62 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_mips64 #define helper_msr_banked helper_msr_banked_mips64 #define helper_neon_abd_f32 helper_neon_abd_f32_mips64 -#define helper_neon_abd_s16 helper_neon_abd_s16_mips64 -#define helper_neon_abd_s32 helper_neon_abd_s32_mips64 -#define helper_neon_abd_s8 helper_neon_abd_s8_mips64 -#define helper_neon_abd_u16 helper_neon_abd_u16_mips64 -#define helper_neon_abd_u32 helper_neon_abd_u32_mips64 -#define helper_neon_abd_u8 helper_neon_abd_u8_mips64 #define helper_neon_abdl_s16 helper_neon_abdl_s16_mips64 #define helper_neon_abdl_s32 helper_neon_abdl_s32_mips64 #define helper_neon_abdl_s64 helper_neon_abdl_s64_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index 99a852d2..e6408917 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_mips64el #define helper_msr_banked helper_msr_banked_mips64el #define helper_neon_abd_f32 helper_neon_abd_f32_mips64el -#define helper_neon_abd_s16 helper_neon_abd_s16_mips64el -#define helper_neon_abd_s32 helper_neon_abd_s32_mips64el -#define helper_neon_abd_s8 helper_neon_abd_s8_mips64el -#define helper_neon_abd_u16 helper_neon_abd_u16_mips64el -#define helper_neon_abd_u32 helper_neon_abd_u32_mips64el -#define helper_neon_abd_u8 helper_neon_abd_u8_mips64el #define helper_neon_abdl_s16 helper_neon_abdl_s16_mips64el #define helper_neon_abdl_s32 helper_neon_abdl_s32_mips64el #define helper_neon_abdl_s64 helper_neon_abdl_s64_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index f170a67a..983a598f 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_mipsel #define helper_msr_banked helper_msr_banked_mipsel #define helper_neon_abd_f32 helper_neon_abd_f32_mipsel -#define helper_neon_abd_s16 helper_neon_abd_s16_mipsel -#define helper_neon_abd_s32 helper_neon_abd_s32_mipsel -#define helper_neon_abd_s8 helper_neon_abd_s8_mipsel -#define helper_neon_abd_u16 helper_neon_abd_u16_mipsel -#define helper_neon_abd_u32 helper_neon_abd_u32_mipsel -#define helper_neon_abd_u8 helper_neon_abd_u8_mipsel #define helper_neon_abdl_s16 helper_neon_abdl_s16_mipsel #define helper_neon_abdl_s32 helper_neon_abdl_s32_mipsel #define helper_neon_abdl_s64 helper_neon_abdl_s64_mipsel diff --git a/qemu/powerpc.h b/qemu/powerpc.h index 55baa8fb..a44420a4 100644 --- a/qemu/powerpc.h +++ b/qemu/powerpc.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_powerpc #define helper_msr_banked helper_msr_banked_powerpc #define helper_neon_abd_f32 helper_neon_abd_f32_powerpc -#define helper_neon_abd_s16 helper_neon_abd_s16_powerpc -#define helper_neon_abd_s32 helper_neon_abd_s32_powerpc -#define helper_neon_abd_s8 helper_neon_abd_s8_powerpc -#define helper_neon_abd_u16 helper_neon_abd_u16_powerpc -#define helper_neon_abd_u32 helper_neon_abd_u32_powerpc -#define helper_neon_abd_u8 helper_neon_abd_u8_powerpc #define helper_neon_abdl_s16 helper_neon_abdl_s16_powerpc #define helper_neon_abdl_s32 helper_neon_abdl_s32_powerpc #define helper_neon_abdl_s64 helper_neon_abdl_s64_powerpc diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 33a332bb..35ea0161 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_riscv32 #define helper_msr_banked helper_msr_banked_riscv32 #define helper_neon_abd_f32 helper_neon_abd_f32_riscv32 -#define helper_neon_abd_s16 helper_neon_abd_s16_riscv32 -#define helper_neon_abd_s32 helper_neon_abd_s32_riscv32 -#define helper_neon_abd_s8 helper_neon_abd_s8_riscv32 -#define helper_neon_abd_u16 helper_neon_abd_u16_riscv32 -#define helper_neon_abd_u32 helper_neon_abd_u32_riscv32 -#define helper_neon_abd_u8 helper_neon_abd_u8_riscv32 #define helper_neon_abdl_s16 helper_neon_abdl_s16_riscv32 #define helper_neon_abdl_s32 helper_neon_abdl_s32_riscv32 #define helper_neon_abdl_s64 helper_neon_abdl_s64_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 5339956e..b9779511 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_riscv64 #define helper_msr_banked helper_msr_banked_riscv64 #define helper_neon_abd_f32 helper_neon_abd_f32_riscv64 -#define helper_neon_abd_s16 helper_neon_abd_s16_riscv64 -#define helper_neon_abd_s32 helper_neon_abd_s32_riscv64 -#define helper_neon_abd_s8 helper_neon_abd_s8_riscv64 -#define helper_neon_abd_u16 helper_neon_abd_u16_riscv64 -#define helper_neon_abd_u32 helper_neon_abd_u32_riscv64 -#define helper_neon_abd_u8 helper_neon_abd_u8_riscv64 #define helper_neon_abdl_s16 helper_neon_abdl_s16_riscv64 #define helper_neon_abdl_s32 helper_neon_abdl_s32_riscv64 #define helper_neon_abdl_s64 helper_neon_abdl_s64_riscv64 diff --git a/qemu/sparc.h b/qemu/sparc.h index 4a3e8585..69998a55 100644 --- a/qemu/sparc.h +++ b/qemu/sparc.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_sparc #define helper_msr_banked helper_msr_banked_sparc #define helper_neon_abd_f32 helper_neon_abd_f32_sparc -#define helper_neon_abd_s16 helper_neon_abd_s16_sparc -#define helper_neon_abd_s32 helper_neon_abd_s32_sparc -#define helper_neon_abd_s8 helper_neon_abd_s8_sparc -#define helper_neon_abd_u16 helper_neon_abd_u16_sparc -#define helper_neon_abd_u32 helper_neon_abd_u32_sparc -#define helper_neon_abd_u8 helper_neon_abd_u8_sparc #define helper_neon_abdl_s16 helper_neon_abdl_s16_sparc #define helper_neon_abdl_s32 helper_neon_abdl_s32_sparc #define helper_neon_abdl_s64 helper_neon_abdl_s64_sparc diff --git a/qemu/sparc64.h b/qemu/sparc64.h index fcf99c11..363701e3 100644 --- a/qemu/sparc64.h +++ b/qemu/sparc64.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_sparc64 #define helper_msr_banked helper_msr_banked_sparc64 #define helper_neon_abd_f32 helper_neon_abd_f32_sparc64 -#define helper_neon_abd_s16 helper_neon_abd_s16_sparc64 -#define helper_neon_abd_s32 helper_neon_abd_s32_sparc64 -#define helper_neon_abd_s8 helper_neon_abd_s8_sparc64 -#define helper_neon_abd_u16 helper_neon_abd_u16_sparc64 -#define helper_neon_abd_u32 helper_neon_abd_u32_sparc64 -#define helper_neon_abd_u8 helper_neon_abd_u8_sparc64 #define helper_neon_abdl_s16 helper_neon_abdl_s16_sparc64 #define helper_neon_abdl_s32 helper_neon_abdl_s32_sparc64 #define helper_neon_abdl_s64 helper_neon_abdl_s64_sparc64 diff --git a/qemu/target/arm/helper.h b/qemu/target/arm/helper.h index d0a35d7d..1a97d32d 100644 --- a/qemu/target/arm/helper.h +++ b/qemu/target/arm/helper.h @@ -280,13 +280,6 @@ DEF_HELPER_2(neon_pmax_s8, i32, i32, i32) DEF_HELPER_2(neon_pmax_u16, i32, i32, i32) DEF_HELPER_2(neon_pmax_s16, i32, i32, i32) -DEF_HELPER_2(neon_abd_u8, i32, i32, i32) -DEF_HELPER_2(neon_abd_s8, i32, i32, i32) -DEF_HELPER_2(neon_abd_u16, i32, i32, i32) -DEF_HELPER_2(neon_abd_s16, i32, i32, i32) -DEF_HELPER_2(neon_abd_u32, i32, i32, i32) -DEF_HELPER_2(neon_abd_s32, i32, i32, i32) - DEF_HELPER_2(neon_shl_u16, i32, i32, i32) DEF_HELPER_2(neon_shl_s16, i32, i32, i32) DEF_HELPER_2(neon_rshl_u8, i32, i32, i32) @@ -737,6 +730,16 @@ DEF_HELPER_FLAGS_4(gvec_uabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_uabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_uabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_saba_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_saba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_saba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_saba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_uaba_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uaba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uaba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uaba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + #ifdef TARGET_ARM #define helper_clz helper_clz_arm #define gen_helper_clz gen_helper_clz_arm diff --git a/qemu/target/arm/neon_helper.c b/qemu/target/arm/neon_helper.c index 1cdccd6c..0b3b2fd3 100644 --- a/qemu/target/arm/neon_helper.c +++ b/qemu/target/arm/neon_helper.c @@ -577,16 +577,6 @@ NEON_POP(pmax_s16, neon_s16, 2) NEON_POP(pmax_u16, neon_u16, 2) #undef NEON_FN -#define NEON_FN(dest, src1, src2) \ - dest = (src1 > src2) ? (src1 - src2) : (src2 - src1) -NEON_VOP(abd_s8, neon_s8, 4) -NEON_VOP(abd_u8, neon_u8, 4) -NEON_VOP(abd_s16, neon_s16, 2) -NEON_VOP(abd_u16, neon_u16, 2) -NEON_VOP(abd_s32, neon_s32, 1) -NEON_VOP(abd_u32, neon_u32, 1) -#undef NEON_FN - #define NEON_FN(dest, src1, src2) do { \ int8_t tmp; \ tmp = (int8_t)src2; \ diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 81b44365..23f4ab3a 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -11487,6 +11487,13 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sabd, size); } return; + case 0xf: /* SABA, UABA */ + if (u) { + gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uaba, size); + } else { + gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_saba, size); + } + return; case 0x10: /* ADD, SUB */ if (u) { gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size); @@ -11619,16 +11626,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) genenvfn = fns[size][u]; break; } - case 0xf: /* SABA, UABA */ - { - static NeonGenTwoOpFn * const fns[3][2] = { - { gen_helper_neon_abd_s8, gen_helper_neon_abd_u8 }, - { gen_helper_neon_abd_s16, gen_helper_neon_abd_u16 }, - { gen_helper_neon_abd_s32, gen_helper_neon_abd_u32 }, - }; - genfn = fns[size][u]; - break; - } case 0x16: /* SQDMULH, SQRDMULH */ { static NeonGenTwoOpEnvFn * const fns[2][2] = { diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c index 7a54bf86..dfde0a8c 100644 --- a/qemu/target/arm/translate.c +++ b/qemu/target/arm/translate.c @@ -5348,6 +5348,124 @@ void gen_gvec_uabd(TCGContext *s, unsigned vece, uint32_t rd_ofs, uint32_t rn_of tcg_gen_gvec_3(s, rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]); } +static void gen_saba_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t = tcg_temp_new_i32(s); + gen_sabd_i32(s, t, a, b); + tcg_gen_add_i32(s, d, d, t); + tcg_temp_free_i32(s, t); +} + +static void gen_saba_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t = tcg_temp_new_i64(s); + gen_sabd_i64(s, t, a, b); + tcg_gen_add_i64(s, d, d, t); + tcg_temp_free_i64(s, t); +} + +static void gen_saba_vec(TCGContext *s, unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t = tcg_temp_new_vec_matching(s, d); + gen_sabd_vec(s, vece, t, a, b); + tcg_gen_add_vec(s, vece, d, d, t); + tcg_temp_free_vec(s, t); +} + +void gen_gvec_saba(TCGContext *s, unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, + uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz) +{ + static const TCGOpcode vecop_list[] = { + INDEX_op_sub_vec, INDEX_op_add_vec, + INDEX_op_smin_vec, INDEX_op_smax_vec, 0 + }; + static const GVecGen3 ops[4] = { + { .fniv = gen_saba_vec, + .fno = gen_helper_gvec_saba_b, + .opt_opc = vecop_list, + .load_dest = true, + .vece = MO_8 }, + { .fniv = gen_saba_vec, + .fno = gen_helper_gvec_saba_h, + .opt_opc = vecop_list, + .load_dest = true, + .vece = MO_16 }, + { .fni4 = gen_saba_i32, + .fniv = gen_saba_vec, + .fno = gen_helper_gvec_saba_s, + .opt_opc = vecop_list, + .load_dest = true, + .vece = MO_32 }, + { .fni8 = gen_saba_i64, + .fniv = gen_saba_vec, + .fno = gen_helper_gvec_saba_d, + .prefer_i64 = TCG_TARGET_REG_BITS == 64, + .opt_opc = vecop_list, + .load_dest = true, + .vece = MO_64 }, + }; + tcg_gen_gvec_3(s, rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]); +} + +static void gen_uaba_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t = tcg_temp_new_i32(s); + gen_uabd_i32(s, t, a, b); + tcg_gen_add_i32(s, d, d, t); + tcg_temp_free_i32(s, t); +} + +static void gen_uaba_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t = tcg_temp_new_i64(s); + gen_uabd_i64(s, t, a, b); + tcg_gen_add_i64(s, d, d, t); + tcg_temp_free_i64(s, t); +} + +static void gen_uaba_vec(TCGContext *s, unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t = tcg_temp_new_vec_matching(s, d); + gen_uabd_vec(s, vece, t, a, b); + tcg_gen_add_vec(s, vece, d, d, t); + tcg_temp_free_vec(s, t); +} + +void gen_gvec_uaba(TCGContext *s, unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, + uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz) +{ + static const TCGOpcode vecop_list[] = { + INDEX_op_sub_vec, INDEX_op_add_vec, + INDEX_op_umin_vec, INDEX_op_umax_vec, 0 + }; + static const GVecGen3 ops[4] = { + { .fniv = gen_uaba_vec, + .fno = gen_helper_gvec_uaba_b, + .opt_opc = vecop_list, + .load_dest = true, + .vece = MO_8 }, + { .fniv = gen_uaba_vec, + .fno = gen_helper_gvec_uaba_h, + .opt_opc = vecop_list, + .load_dest = true, + .vece = MO_16 }, + { .fni4 = gen_uaba_i32, + .fniv = gen_uaba_vec, + .fno = gen_helper_gvec_uaba_s, + .opt_opc = vecop_list, + .load_dest = true, + .vece = MO_32 }, + { .fni8 = gen_uaba_i64, + .fniv = gen_uaba_vec, + .fno = gen_helper_gvec_uaba_d, + .prefer_i64 = TCG_TARGET_REG_BITS == 64, + .opt_opc = vecop_list, + .load_dest = true, + .vece = MO_64 }, + }; + tcg_gen_gvec_3(s, rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]); +} + /* Translate a NEON data processing instruction. Return nonzero if the instruction is invalid. We process data in a mixture of 32-bit and 64-bit chunks. @@ -5493,6 +5611,16 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } return 0; + case NEON_3R_VABA: + if (u) { + gen_gvec_uaba(tcg_ctx, size, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + } else { + gen_gvec_saba(tcg_ctx, size, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + } + return 0; + case NEON_3R_VADD_VSUB: case NEON_3R_LOGIC: case NEON_3R_VMAX: @@ -5637,12 +5765,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VQRSHL: GEN_NEON_INTEGER_OP_ENV(qrshl); break; - case NEON_3R_VABA: - GEN_NEON_INTEGER_OP(abd); - tcg_temp_free_i32(tcg_ctx, tmp2); - tmp2 = neon_load_reg(s, rd, pass); - gen_neon_add(s, size, tmp, tmp2); - break; case NEON_3R_VPMAX: GEN_NEON_INTEGER_OP(pmax); break; diff --git a/qemu/target/arm/translate.h b/qemu/target/arm/translate.h index d6a2315d..1bcfb490 100644 --- a/qemu/target/arm/translate.h +++ b/qemu/target/arm/translate.h @@ -349,6 +349,11 @@ void gen_gvec_sabd(TCGContext *s, unsigned vece, uint32_t rd_ofs, uint32_t rn_of void gen_gvec_uabd(TCGContext *s, unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); +void gen_gvec_saba(TCGContext *s, unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, + uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); +void gen_gvec_uaba(TCGContext *s, unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, + uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); + /* * Forward to the isar_feature_* tests given a DisasContext pointer. */ diff --git a/qemu/target/arm/vec_helper.c b/qemu/target/arm/vec_helper.c index 7139c300..a3db18af 100644 --- a/qemu/target/arm/vec_helper.c +++ b/qemu/target/arm/vec_helper.c @@ -1431,3 +1431,27 @@ DO_ABD(gvec_uabd_s, uint32_t) DO_ABD(gvec_uabd_d, uint64_t) #undef DO_ABD + +#define DO_ABA(NAME, TYPE) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ +{ \ + intptr_t i, opr_sz = simd_oprsz(desc); \ + TYPE *d = vd, *n = vn, *m = vm; \ + \ + for (i = 0; i < opr_sz / sizeof(TYPE); ++i) { \ + d[i] += n[i] < m[i] ? m[i] - n[i] : n[i] - m[i]; \ + } \ + clear_tail(d, opr_sz, simd_maxsz(desc)); \ +} + +DO_ABA(gvec_saba_b, int8_t) +DO_ABA(gvec_saba_h, int16_t) +DO_ABA(gvec_saba_s, int32_t) +DO_ABA(gvec_saba_d, int64_t) + +DO_ABA(gvec_uaba_b, uint8_t) +DO_ABA(gvec_uaba_h, uint16_t) +DO_ABA(gvec_uaba_s, uint32_t) +DO_ABA(gvec_uaba_d, uint64_t) + +#undef DO_ABA diff --git a/qemu/x86_64.h b/qemu/x86_64.h index 65ec9368..72eac9e8 100644 --- a/qemu/x86_64.h +++ b/qemu/x86_64.h @@ -1467,12 +1467,6 @@ #define helper_msa_st_w helper_msa_st_w_x86_64 #define helper_msr_banked helper_msr_banked_x86_64 #define helper_neon_abd_f32 helper_neon_abd_f32_x86_64 -#define helper_neon_abd_s16 helper_neon_abd_s16_x86_64 -#define helper_neon_abd_s32 helper_neon_abd_s32_x86_64 -#define helper_neon_abd_s8 helper_neon_abd_s8_x86_64 -#define helper_neon_abd_u16 helper_neon_abd_u16_x86_64 -#define helper_neon_abd_u32 helper_neon_abd_u32_x86_64 -#define helper_neon_abd_u8 helper_neon_abd_u8_x86_64 #define helper_neon_abdl_s16 helper_neon_abdl_s16_x86_64 #define helper_neon_abdl_s32 helper_neon_abdl_s32_x86_64 #define helper_neon_abdl_s64 helper_neon_abdl_s64_x86_64