From 4544aa4134c2d6c1c7b65dfdecfdda15d30e7ef3 Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Sat, 17 Feb 2018 14:41:27 -0500 Subject: [PATCH] target-mips: Set Config5.XNP for R6 cores Set Config5.XNP for R6 cores to indicate the extended LL/SC family of instructions NOT present. Backports commit 35ac9e342e008e3d47ef18d33a6977fdb99de9cd from qemu --- qemu/target-mips/translate_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qemu/target-mips/translate_init.c b/qemu/target-mips/translate_init.c index 5f454b96..521d97c8 100644 --- a/qemu/target-mips/translate_init.c +++ b/qemu/target-mips/translate_init.c @@ -553,7 +553,7 @@ static const mips_def_t mips_defs[] = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | (3 << CP0C4_IE) | (1U << CP0C4_M), 0, - MIPS_CONFIG5 | (1 << CP0C5_LLB), + MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB), (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | (1 << CP0C5_UFE), 0, 0, @@ -788,7 +788,7 @@ static const mips_def_t mips_defs[] = (1 << CP0C3_RXI) | (1 << CP0C3_LPA), MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | (0xfc << CP0C4_KScrExist), - MIPS_CONFIG5 | (1 << CP0C5_LLB), + MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB), (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | (1 << CP0C5_UFE), 0,