diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c
index 5f253acc..2ae16ff1 100644
--- a/qemu/target-arm/helper.c
+++ b/qemu/target-arm/helper.c
@@ -3079,8 +3079,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
       PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.scr_el3), {0, 0},
       NULL, NULL, scr_write },
     { "SCR", 15,1,1, 0,0,0, 0,ARM_CP_ALIAS,
-      PL3_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3), {0, 0},
-      NULL, NULL, scr_write, NULL, NULL, NULL },
+      PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3), {0, 0},
+      access_trap_aa32s_el1, NULL, scr_write, NULL, NULL, NULL },
     { "MDCR_EL3", 0,1,3, 3,6,1, ARM_CP_STATE_AA64, 0,
       PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mdcr_el3) },
     { "SDCR", 15,1,3, 0,0,1, 0, ARM_CP_ALIAS,
@@ -3094,8 +3094,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
     { "NSACR", 15,1,1, 0,0,2, 0,0,
       PL3_W | PL1_R, 0, NULL, 0, offsetof(CPUARMState, cp15.nsacr) },
     { "MVBAR", 15,12,0, 0,0,1, 0,0,
-      PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0},
-      NULL, NULL, vbar_write },
+      PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0},
+      access_trap_aa32s_el1, NULL, vbar_write },
     { "SCTLR_EL3", 0,1,0, 3,6,0, ARM_CP_STATE_AA64,
       ARM_CP_ALIAS, /* reset handled by AArch32 view */
       PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sctlr_el[3]), {0, 0},