From 45524449283a9ee0bde69cd25fd2036623af9e7e Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 20 Feb 2018 11:10:34 -0500 Subject: [PATCH] target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR The registers MVBAR and SCR should have the behaviour of trapping to EL3 if accessed from Secure EL1, but we were incorrectly implementing them to UNDEF (which would trap to EL1). Fix this by using the new access_trap_aa32s_el1() access function. Backports commit efe4a274083f61484a8f1478d93f229d43aa8095 from qemu --- qemu/target-arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index 5f253acc..2ae16ff1 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -3079,8 +3079,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.scr_el3), {0, 0}, NULL, NULL, scr_write }, { "SCR", 15,1,1, 0,0,0, 0,ARM_CP_ALIAS, - PL3_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3), {0, 0}, - NULL, NULL, scr_write, NULL, NULL, NULL }, + PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3), {0, 0}, + access_trap_aa32s_el1, NULL, scr_write, NULL, NULL, NULL }, { "MDCR_EL3", 0,1,3, 3,6,1, ARM_CP_STATE_AA64, 0, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mdcr_el3) }, { "SDCR", 15,1,3, 0,0,1, 0, ARM_CP_ALIAS, @@ -3094,8 +3094,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { { "NSACR", 15,1,1, 0,0,2, 0,0, PL3_W | PL1_R, 0, NULL, 0, offsetof(CPUARMState, cp15.nsacr) }, { "MVBAR", 15,12,0, 0,0,1, 0,0, - PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0}, - NULL, NULL, vbar_write }, + PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0}, + access_trap_aa32s_el1, NULL, vbar_write }, { "SCTLR_EL3", 0,1,0, 3,6,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS, /* reset handled by AArch32 view */ PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sctlr_el[3]), {0, 0},