diff --git a/qemu/target-arm/cpu.h b/qemu/target-arm/cpu.h
index 94793198..e5db3f9d 100644
--- a/qemu/target-arm/cpu.h
+++ b/qemu/target-arm/cpu.h
@@ -183,6 +183,7 @@ typedef struct CPUARMState {
         uint64_t c1_sys; /* System control register.  */
         uint64_t c1_coproc; /* Coprocessor access register.  */
         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
+        uint32_t nsacr; /* Non-secure access control register. */
         uint64_t ttbr0_el1; /* MMU translation table base 0. */
         uint64_t ttbr1_el1; /* MMU translation table base 1. */
         uint64_t c2_control; /* MMU translation table base control.  */
diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c
index 8f3259b2..c175ca69 100644
--- a/qemu/target-arm/helper.c
+++ b/qemu/target-arm/helper.c
@@ -1994,6 +1994,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
     { "SCR", 15,1,1, 0,0,0, 0,
       ARM_CP_NO_MIGRATE, PL3_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3), {0, 0},
       NULL, NULL, scr_write, NULL, NULL, arm_cp_reset_ignore },
+      /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
+    { "NSACR", 15,1,1, 0,0,2, 0,0,
+      PL3_W | PL1_R, 0, NULL, 0,
+      offsetof(CPUARMState, cp15.nsacr), },
     REGINFO_SENTINEL
 };