From 468e2849cd54e85f298f20620b88129584e62476 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 1 Mar 2018 23:02:26 -0500 Subject: [PATCH] target/arm: Implement DBGVCR32_EL2 system register The DBGVCR_EL2 system register is needed to run a 32-bit EL1 guest under a Linux EL2 64-bit hypervisor. Its only purpose is to provide AArch64 with access to the state of the DBGVCR AArch32 register. Since we only have a dummy DBGVCR, implement a corresponding dummy DBGVCR32_EL2. Backports commit 4d2ec4da1c2d60c9fd8bad137506870c2f980410 from qemu --- qemu/target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 279498b9..06079c6a 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -3548,6 +3548,9 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { { "DBGVCR", 14,0,7, 0,0,0, 0, ARM_CP_NOP, PL1_RW, 0, NULL, 0, 0, {0, 0}, access_tda }, + { "DBGVCR32_EL2", 0,0,7, 2,4,0, ARM_CP_STATE_AA64, ARM_CP_NOP, + PL2_RW, 0, NULL, 0, 0, {0, 0}, + access_tda }, /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications * Channel but Linux may try to access this register. The 32-bit * alias is DBGDCCINT.