From 47b45f1bc29415b7644d8cce1f3f052b37609331 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 6 Oct 2018 03:45:49 -0400 Subject: [PATCH] arm: Take DisasContext as a parameter instead of TCGContext where applicable This is more future-friendly with qemu, as it's more generic. --- qemu/target/arm/translate-a64.c | 127 +++++----- qemu/target/arm/translate-a64.h | 2 +- qemu/target/arm/translate-sve.c | 30 +-- qemu/target/arm/translate.c | 425 +++++++++++++++++--------------- qemu/target/arm/translate.h | 11 +- 5 files changed, 309 insertions(+), 286 deletions(-) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 0d9797ce..05381414 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -347,11 +347,12 @@ typedef struct DisasCompare64 { TCGv_i64 value; } DisasCompare64; -static void a64_test_cc(TCGContext *tcg_ctx, DisasCompare64 *c64, int cc) +static void a64_test_cc(DisasContext *s, DisasCompare64 *c64, int cc) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; DisasCompare c32; - arm_test_cc(tcg_ctx, &c32, cc); + arm_test_cc(s, &c32, cc); /* Sign-extend the 32-bit value so that the GE/LT comparisons work * properly. The NE/EQ comparisons are also fine with this choice. */ @@ -359,11 +360,13 @@ static void a64_test_cc(TCGContext *tcg_ctx, DisasCompare64 *c64, int cc) c64->value = tcg_temp_new_i64(tcg_ctx); tcg_gen_ext_i32_i64(tcg_ctx, c64->value, c32.value); - arm_free_cc(tcg_ctx, &c32); + arm_free_cc(s, &c32); } -static void a64_free_cc(TCGContext *tcg_ctx, DisasCompare64 *c64) +static void a64_free_cc(DisasContext *s, DisasCompare64 *c64) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; + tcg_temp_free_i64(tcg_ctx, c64->value); } @@ -682,8 +685,9 @@ static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) tcg_temp_free_i64(tcg_ctx, tmp); } -TCGv_ptr get_fpstatus_ptr(TCGContext *tcg_ctx, bool is_f16) +TCGv_ptr get_fpstatus_ptr(DisasContext *s, bool is_f16) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_ptr statusptr = tcg_temp_new_ptr(tcg_ctx); int offset; @@ -791,7 +795,7 @@ static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn, { TCGContext *tcg_ctx = s->uc->tcg_ctx; - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, is_fp16); + TCGv_ptr fpst = get_fpstatus_ptr(s, is_fp16); tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), vec_full_reg_offset(s, rm), fpst, @@ -802,17 +806,20 @@ static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn, /* Set ZF and NF based on a 64 bit result. This is alas fiddlier * than the 32 bit equivalent. */ -static inline void gen_set_NZ64(TCGContext *tcg_ctx, TCGv_i64 result) +static inline void gen_set_NZ64(DisasContext *s, TCGv_i64 result) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; tcg_gen_extr_i64_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_NF, result); tcg_gen_or_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_ZF, tcg_ctx->cpu_NF); } /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */ -static inline void gen_logic_CC(TCGContext *tcg_ctx, int sf, TCGv_i64 result) +static inline void gen_logic_CC(DisasContext *s, int sf, TCGv_i64 result) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; + if (sf) { - gen_set_NZ64(tcg_ctx, result); + gen_set_NZ64(s, result); } else { tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_ZF, result); tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_NF, tcg_ctx->cpu_ZF); @@ -836,7 +843,7 @@ static void gen_add_CC(DisasContext *s, int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_CF, flag); - gen_set_NZ64(tcg_ctx, result); + gen_set_NZ64(s, result); tcg_gen_xor_i64(tcg_ctx, flag, result, t0); tcg_gen_xor_i64(tcg_ctx, tmp, t0, t1); @@ -881,7 +888,7 @@ static void gen_sub_CC(DisasContext *s, int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv flag = tcg_temp_new_i64(tcg_ctx); tcg_gen_sub_i64(tcg_ctx, result, t0, t1); - gen_set_NZ64(tcg_ctx, result); + gen_set_NZ64(s, result); tcg_gen_setcond_i64(tcg_ctx, TCG_COND_GEU, flag, t0, t1); tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_CF, flag); @@ -947,7 +954,7 @@ static void gen_adc_CC(DisasContext *s, int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv tcg_gen_add2_i64(tcg_ctx, result, cf_64, t0, tmp, cf_64, tmp); tcg_gen_add2_i64(tcg_ctx, result, cf_64, result, cf_64, t1, tmp); tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_CF, cf_64); - gen_set_NZ64(tcg_ctx, result); + gen_set_NZ64(s, result); tcg_gen_xor_i64(tcg_ctx, vf_64, result, t0); tcg_gen_xor_i64(tcg_ctx, tmp, t0, t1); @@ -1514,7 +1521,7 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn) if (cond < 0x0e) { /* genuinely conditional branches */ TCGLabel *label_match = gen_new_label(tcg_ctx); - arm_gen_test_cc(tcg_ctx, cond, label_match); + arm_gen_test_cc(s, cond, label_match); gen_goto_tb(s, 0, s->pc); gen_set_label(tcg_ctx, label_match); gen_goto_tb(s, 1, addr); @@ -3616,7 +3623,7 @@ static void disas_logic_imm(DisasContext *s, uint32_t insn) } if (opc == 3) { /* ANDS */ - gen_logic_CC(tcg_ctx, sf, tcg_rd); + gen_logic_CC(s, sf, tcg_rd); } } @@ -3995,7 +4002,7 @@ static void disas_logic_reg(DisasContext *s, uint32_t insn) } if (opc == 3) { - gen_logic_CC(tcg_ctx, sf, tcg_rd); + gen_logic_CC(s, sf, tcg_rd); } } @@ -4313,9 +4320,9 @@ static void disas_cc(DisasContext *s, uint32_t insn) /* Set T0 = !COND. */ tcg_t0 = tcg_temp_new_i32(tcg_ctx); - arm_test_cc(tcg_ctx, &c, cond); + arm_test_cc(s, &c, cond); tcg_gen_setcondi_i32(tcg_ctx, tcg_invert_cond(c.cond), tcg_t0, c.value, 0); - arm_free_cc(tcg_ctx, &c); + arm_free_cc(s, &c); /* Load the arguments for the new comparison. */ if (is_imm) { @@ -4414,7 +4421,7 @@ static void disas_cond_select(DisasContext *s, uint32_t insn) tcg_rd = cpu_reg(s, rd); - a64_test_cc(tcg_ctx, &c, cond); + a64_test_cc(s, &c, cond); zero = tcg_const_i64(tcg_ctx, 0); if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) { @@ -4438,7 +4445,7 @@ static void disas_cond_select(DisasContext *s, uint32_t insn) } tcg_temp_free_i64(tcg_ctx, zero); - a64_free_cc(tcg_ctx, &c); + a64_free_cc(s, &c); if (!sf) { tcg_gen_ext32u_i64(tcg_ctx, tcg_rd, tcg_rd); @@ -4806,7 +4813,7 @@ static void handle_fp_compare(DisasContext *s, int size, { TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i64 tcg_flags = tcg_temp_new_i64(tcg_ctx); - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, size == MO_16); + TCGv_ptr fpst = get_fpstatus_ptr(s, size == MO_16); if (size == MO_64) { TCGv_i64 tcg_vn, tcg_vm; @@ -4966,7 +4973,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn) if (cond < 0x0e) { /* not always */ TCGLabel *label_match = gen_new_label(tcg_ctx); label_continue = gen_new_label(tcg_ctx); - arm_gen_test_cc(tcg_ctx, cond, label_match); + arm_gen_test_cc(s, cond, label_match); /* nomatch: */ tcg_flags = tcg_const_i64(tcg_ctx, nzcv << 28); gen_set_nzcv(tcg_ctx, tcg_flags); @@ -5036,12 +5043,12 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) read_vec_element(s, t_true, rn, 0, sz); read_vec_element(s, t_false, rm, 0, sz); - a64_test_cc(tcg_ctx, &c, cond); + a64_test_cc(s, &c, cond); t_zero = tcg_const_i64(tcg_ctx, 0); tcg_gen_movcond_i64(tcg_ctx, c.cond, t_true, c.value, t_zero, t_true, t_false); tcg_temp_free_i64(tcg_ctx, t_zero); tcg_temp_free_i64(tcg_ctx, t_false); - a64_free_cc(tcg_ctx, &c); + a64_free_cc(s, &c); /* Note that sregs & hregs write back zeros to the high bits, and we've already done the zero-extension. */ @@ -5068,7 +5075,7 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) tcg_gen_xori_i32(tcg_ctx, tcg_res, tcg_op, 0x8000); break; case 0x3: /* FSQRT */ - fpst = get_fpstatus_ptr(tcg_ctx, true); + fpst = get_fpstatus_ptr(s, true); gen_helper_sqrt_f16(tcg_ctx, tcg_res, tcg_op, fpst); break; case 0x8: /* FRINTN */ @@ -5078,7 +5085,7 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) case 0xc: /* FRINTA */ { TCGv_i32 tcg_rmode = tcg_const_i32(tcg_ctx, arm_rmode_to_sf(opcode & 7)); - fpst = get_fpstatus_ptr(tcg_ctx, true); + fpst = get_fpstatus_ptr(s, true); gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, fpst); gen_helper_advsimd_rinth(tcg_ctx, tcg_res, tcg_op, fpst); @@ -5088,11 +5095,11 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) break; } case 0xe: /* FRINTX */ - fpst = get_fpstatus_ptr(tcg_ctx, true); + fpst = get_fpstatus_ptr(s, true); gen_helper_advsimd_rinth_exact(tcg_ctx, tcg_res, tcg_op, fpst); break; case 0xf: /* FRINTI */ - fpst = get_fpstatus_ptr(tcg_ctx, true); + fpst = get_fpstatus_ptr(s, true); gen_helper_advsimd_rinth(tcg_ctx, tcg_res, tcg_op, fpst); break; default: @@ -5116,7 +5123,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) TCGv_i32 tcg_op; TCGv_i32 tcg_res; - fpst = get_fpstatus_ptr(tcg_ctx, false); + fpst = get_fpstatus_ptr(s, false); tcg_op = read_fp_sreg(s, rn); tcg_res = tcg_temp_new_i32(tcg_ctx); @@ -5179,7 +5186,7 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) return; } - fpst = get_fpstatus_ptr(tcg_ctx, false); + fpst = get_fpstatus_ptr(s, false); tcg_op = read_fp_dreg(s, rn); tcg_res = tcg_temp_new_i64(tcg_ctx); @@ -5242,8 +5249,8 @@ static void handle_fp_fcvt(DisasContext *s, int opcode, } else { /* Single to half */ TCGv_i32 tcg_rd = tcg_temp_new_i32(tcg_ctx); - TCGv_i32 ahp = get_ahp_flag(tcg_ctx); - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false); + TCGv_i32 ahp = get_ahp_flag(s); + TCGv_ptr fpst = get_fpstatus_ptr(s, false); gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tcg_rd, tcg_rn, fpst, ahp); /* write_fp_sreg is OK here because top half of tcg_rd is zero */ @@ -5263,8 +5270,8 @@ static void handle_fp_fcvt(DisasContext *s, int opcode, /* Double to single */ gen_helper_vfp_fcvtsd(tcg_ctx, tcg_rd, tcg_rn, tcg_ctx->cpu_env); } else { - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false); - TCGv_i32 ahp = get_ahp_flag(tcg_ctx); + TCGv_ptr fpst = get_fpstatus_ptr(s, false); + TCGv_i32 ahp = get_ahp_flag(s); /* Double to half */ gen_helper_vfp_fcvt_f64_to_f16(tcg_ctx, tcg_rd, tcg_rn, fpst, ahp); /* write_fp_sreg is OK here because top half of tcg_rd is zero */ @@ -5279,8 +5286,8 @@ static void handle_fp_fcvt(DisasContext *s, int opcode, case 0x3: { TCGv_i32 tcg_rn = read_fp_sreg(s, rn); - TCGv_ptr tcg_fpst = get_fpstatus_ptr(tcg_ctx, false); - TCGv_i32 tcg_ahp = get_ahp_flag(tcg_ctx); + TCGv_ptr tcg_fpst = get_fpstatus_ptr(s, false); + TCGv_i32 tcg_ahp = get_ahp_flag(s); tcg_gen_ext16u_i32(tcg_ctx, tcg_rn, tcg_rn); if (dtype == 0) { /* Half to single */ @@ -5386,7 +5393,7 @@ static void handle_fp_2src_single(DisasContext *s, int opcode, TCGv_ptr fpst; tcg_res = tcg_temp_new_i32(tcg_ctx); - fpst = get_fpstatus_ptr(tcg_ctx, false); + fpst = get_fpstatus_ptr(s, false); tcg_op1 = read_fp_sreg(s, rn); tcg_op2 = read_fp_sreg(s, rm); @@ -5440,7 +5447,7 @@ static void handle_fp_2src_double(DisasContext *s, int opcode, TCGv_ptr fpst; tcg_res = tcg_temp_new_i64(tcg_ctx); - fpst = get_fpstatus_ptr(tcg_ctx, false); + fpst = get_fpstatus_ptr(s, false); tcg_op1 = read_fp_dreg(s, rn); tcg_op2 = read_fp_dreg(s, rm); @@ -5495,7 +5502,7 @@ static void handle_fp_2src_half(DisasContext *s, int opcode, TCGv_ptr fpst; tcg_res = tcg_temp_new_i32(tcg_ctx); - fpst = get_fpstatus_ptr(tcg_ctx, true); + fpst = get_fpstatus_ptr(s, true); tcg_op1 = read_fp_hreg(s, rn); tcg_op2 = read_fp_hreg(s, rm); @@ -5594,7 +5601,7 @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1, TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 tcg_op1, tcg_op2, tcg_op3; TCGv_i32 tcg_res = tcg_temp_new_i32(tcg_ctx); - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false); + TCGv_ptr fpst = get_fpstatus_ptr(s, false); tcg_op1 = read_fp_sreg(s, rn); tcg_op2 = read_fp_sreg(s, rm); @@ -5633,7 +5640,7 @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i64 tcg_op1, tcg_op2, tcg_op3; TCGv_i64 tcg_res = tcg_temp_new_i64(tcg_ctx); - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false); + TCGv_ptr fpst = get_fpstatus_ptr(s, false); tcg_op1 = read_fp_dreg(s, rn); tcg_op2 = read_fp_dreg(s, rm); @@ -5673,7 +5680,7 @@ static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1, TCGv_i32 tcg_op1, tcg_op2, tcg_op3; TCGv_i32 tcg_res = tcg_temp_new_i32(tcg_ctx); - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, true); + TCGv_ptr fpst = get_fpstatus_ptr(s, true); tcg_op1 = read_fp_hreg(s, rn); tcg_op2 = read_fp_hreg(s, rm); @@ -5840,7 +5847,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, TCGv_i32 tcg_shift, tcg_single; TCGv_i64 tcg_double; - tcg_fpstatus = get_fpstatus_ptr(tcg_ctx, type == 3); + tcg_fpstatus = get_fpstatus_ptr(s, type == 3); tcg_shift = tcg_const_i32(tcg_ctx, 64 - scale); @@ -6706,7 +6713,7 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) * Note that correct NaN propagation requires that we do these * operations in exactly the order specified by the pseudocode. */ - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, size == MO_16); + TCGv_ptr fpst = get_fpstatus_ptr(s, size == MO_16); int fpopcode = opcode | is_min << 4 | is_u << 5; int vmap = (1 << elements) - 1; TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize, @@ -7218,7 +7225,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) return; } - fpst = get_fpstatus_ptr(tcg_ctx, size == MO_16); + fpst = get_fpstatus_ptr(s, size == MO_16); break; default: unallocated_encoding(s); @@ -7737,7 +7744,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, int fracbits, int size) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - TCGv_ptr tcg_fpst = get_fpstatus_ptr(tcg_ctx, size == MO_16); + TCGv_ptr tcg_fpst = get_fpstatus_ptr(s, size == MO_16); TCGv_i32 tcg_shift = NULL; TCGMemOp mop = size | (is_signed ? MO_SIGN : 0); @@ -7919,7 +7926,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, assert(!(is_scalar && is_q)); tcg_rmode = tcg_const_i32(tcg_ctx, arm_rmode_to_sf(FPROUNDING_ZERO)); - tcg_fpstatus = get_fpstatus_ptr(tcg_ctx, size == MO_16); + tcg_fpstatus = get_fpstatus_ptr(s, size == MO_16); gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, tcg_fpstatus); fracbits = (16 << size) - immhb; tcg_shift = tcg_const_i32(tcg_ctx, fracbits); @@ -8283,7 +8290,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements, { TCGContext *tcg_ctx = s->uc->tcg_ctx; int pass; - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false); + TCGv_ptr fpst = get_fpstatus_ptr(s, false); for (pass = 0; pass < elements; pass++) { if (size) { @@ -8678,7 +8685,7 @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, return; } - fpst = get_fpstatus_ptr(tcg_ctx, true); + fpst = get_fpstatus_ptr(s, true); tcg_op1 = read_fp_hreg(s, rn); tcg_op2 = read_fp_hreg(s, rm); @@ -8930,7 +8937,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, return; } - fpst = get_fpstatus_ptr(tcg_ctx, size == MO_16); + fpst = get_fpstatus_ptr(s, size == MO_16); if (is_double) { TCGv_i64 tcg_op = tcg_temp_new_i64(tcg_ctx); @@ -9061,7 +9068,7 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode, { TCGContext *tcg_ctx = s->uc->tcg_ctx; bool is_double = (size == 3); - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false); + TCGv_ptr fpst = get_fpstatus_ptr(s, false); if (is_double) { TCGv_i64 tcg_op = tcg_temp_new_i64(tcg_ctx); @@ -9203,8 +9210,8 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar, } else { TCGv_i32 tcg_lo = tcg_temp_new_i32(tcg_ctx); TCGv_i32 tcg_hi = tcg_temp_new_i32(tcg_ctx); - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false); - TCGv_i32 ahp = get_ahp_flag(tcg_ctx); + TCGv_ptr fpst = get_fpstatus_ptr(s, false); + TCGv_i32 ahp = get_ahp_flag(s); tcg_gen_extr_i64_i32(tcg_ctx, tcg_lo, tcg_hi, tcg_op); gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tcg_lo, tcg_lo, fpst, ahp); @@ -9467,7 +9474,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) if (is_fcvt) { tcg_rmode = tcg_const_i32(tcg_ctx, arm_rmode_to_sf(rmode)); - tcg_fpstatus = get_fpstatus_ptr(tcg_ctx, false); + tcg_fpstatus = get_fpstatus_ptr(s, false); gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, tcg_fpstatus); } else { tcg_rmode = NULL; @@ -10672,7 +10679,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode, /* Floating point operations need fpst */ if (opcode >= 0x58) { - fpst = get_fpstatus_ptr(tcg_ctx, false); + fpst = get_fpstatus_ptr(s, false); } else { fpst = NULL; } @@ -11406,7 +11413,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) break; } - fpst = get_fpstatus_ptr(tcg_ctx, true); + fpst = get_fpstatus_ptr(s, true); if (pairwise) { int maxpass = is_q ? 8 : 4; @@ -11716,8 +11723,8 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, /* 16 -> 32 bit fp conversion */ int srcelt = is_q ? 4 : 0; TCGv_i32 tcg_res[4]; - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false); - TCGv_i32 ahp = get_ahp_flag(tcg_ctx); + TCGv_ptr fpst = get_fpstatus_ptr(s, false); + TCGv_i32 ahp = get_ahp_flag(s); for (pass = 0; pass < 4; pass++) { tcg_res[pass] = tcg_temp_new_i32(tcg_ctx); @@ -12181,7 +12188,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } if (need_fpstatus || need_rmode) { - tcg_fpstatus = get_fpstatus_ptr(tcg_ctx, false); + tcg_fpstatus = get_fpstatus_ptr(s, false); } else { tcg_fpstatus = NULL; } @@ -12621,7 +12628,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) } if (need_rmode || need_fpst) { - tcg_fpstatus = get_fpstatus_ptr(tcg_ctx, true); + tcg_fpstatus = get_fpstatus_ptr(s, true); } if (need_rmode) { @@ -12920,7 +12927,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } if (is_fp) { - fpst = get_fpstatus_ptr(tcg_ctx, is_fp16); + fpst = get_fpstatus_ptr(s, is_fp16); } else { fpst = NULL; } diff --git a/qemu/target/arm/translate-a64.h b/qemu/target/arm/translate-a64.h index 0e246ef7..34284c8c 100644 --- a/qemu/target/arm/translate-a64.h +++ b/qemu/target/arm/translate-a64.h @@ -36,7 +36,7 @@ TCGv_i64 cpu_reg_sp(DisasContext *s, int reg); TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf); TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf); void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v); -TCGv_ptr get_fpstatus_ptr(TCGContext *, bool); +TCGv_ptr get_fpstatus_ptr(DisasContext *, bool); bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, unsigned int imms, unsigned int immr); uint64_t vfp_expand_imm(int size, uint8_t imm8); diff --git a/qemu/target/arm/translate-sve.c b/qemu/target/arm/translate-sve.c index ddb03df3..dbde4052 100644 --- a/qemu/target/arm/translate-sve.c +++ b/qemu/target/arm/translate-sve.c @@ -3627,7 +3627,7 @@ static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a, uint32_t insn) if (sve_access_check(s)) { TCGContext *tcg_ctx = s->uc->tcg_ctx; unsigned vsz = vec_full_reg_size(s); - TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16); + TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16); tcg_gen_gvec_4_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3654,7 +3654,7 @@ static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a, uint32_t insn) if (sve_access_check(s)) { TCGContext *tcg_ctx = s->uc->tcg_ctx; unsigned vsz = vec_full_reg_size(s); - TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16); + TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16); tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3687,7 +3687,7 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a, tcg_gen_addi_ptr(tcg_ctx, t_zn, tcg_ctx->cpu_env, vec_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(tcg_ctx, t_pg, tcg_ctx->cpu_env, pred_full_reg_offset(s, a->pg)); - status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16); + status = get_fpstatus_ptr(s, a->esz == MO_16); fn(tcg_ctx, temp, t_zn, t_pg, status, t_desc); tcg_temp_free_ptr(tcg_ctx, t_zn); @@ -3730,7 +3730,7 @@ static void do_zz_fp(DisasContext *s, arg_rr_esz *a, gen_helper_gvec_2_ptr *fn) { TCGContext *tcg_ctx = s->uc->tcg_ctx; unsigned vsz = vec_full_reg_size(s); - TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16); + TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16); tcg_gen_gvec_2_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), @@ -3779,7 +3779,7 @@ static void do_ppz_fp(DisasContext *s, arg_rpr_esz *a, { TCGContext *tcg_ctx = s->uc->tcg_ctx; unsigned vsz = vec_full_reg_size(s); - TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16); + TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16); tcg_gen_gvec_3_ptr(tcg_ctx, pred_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), @@ -3832,7 +3832,7 @@ static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a, uint32_t insn) if (sve_access_check(s)) { TCGContext *tcg_ctx = s->uc->tcg_ctx; unsigned vsz = vec_full_reg_size(s); - TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16); + TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16); tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3873,7 +3873,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a, uint32_t insn) t_pg = tcg_temp_new_ptr(tcg_ctx); tcg_gen_addi_ptr(tcg_ctx, t_rm, tcg_ctx->cpu_env, vec_full_reg_offset(s, a->rm)); tcg_gen_addi_ptr(tcg_ctx, t_pg, tcg_ctx->cpu_env, pred_full_reg_offset(s, a->pg)); - t_fpst = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16); + t_fpst = get_fpstatus_ptr(s, a->esz == MO_16); t_desc = tcg_const_i32(tcg_ctx, simd_desc(vsz, vsz, 0)); fns[a->esz - 1](tcg_ctx, t_val, t_val, t_rm, t_pg, t_fpst, t_desc); @@ -3901,7 +3901,7 @@ static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a, if (sve_access_check(s)) { TCGContext *tcg_ctx = s->uc->tcg_ctx; unsigned vsz = vec_full_reg_size(s); - TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16); + TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16); tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3944,7 +3944,7 @@ static bool do_zpzz_fp(DisasContext *s, arg_rprr_esz *a, if (sve_access_check(s)) { TCGContext *tcg_ctx = s->uc->tcg_ctx; unsigned vsz = vec_full_reg_size(s); - TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16); + TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16); tcg_gen_gvec_4_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3997,7 +3997,7 @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16, tcg_gen_addi_ptr(tcg_ctx, t_zn, tcg_ctx->cpu_env, vec_full_reg_offset(s, zn)); tcg_gen_addi_ptr(tcg_ctx, t_pg, tcg_ctx->cpu_env, pred_full_reg_offset(s, pg)); - status = get_fpstatus_ptr(tcg_ctx, is_fp16); + status = get_fpstatus_ptr(s, is_fp16); desc = tcg_const_i32(tcg_ctx, simd_desc(vsz, vsz, 0)); fn(tcg_ctx, t_zd, t_zn, t_pg, scalar, status, desc); @@ -4064,7 +4064,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *a, if (sve_access_check(s)) { TCGContext *tcg_ctx = s->uc->tcg_ctx; unsigned vsz = vec_full_reg_size(s); - TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16); + TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16); tcg_gen_gvec_4_ptr(tcg_ctx, pred_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -4110,7 +4110,7 @@ static bool trans_FCADD(DisasContext *s, arg_FCADD *a, uint32_t insn) if (sve_access_check(s)) { TCGContext *tcg_ctx = s->uc->tcg_ctx; unsigned vsz = vec_full_reg_size(s); - TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16); + TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16); tcg_gen_gvec_4_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -4221,7 +4221,7 @@ static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a, uint32_t insn) if (sve_access_check(s)) { TCGContext *tcg_ctx = s->uc->tcg_ctx; unsigned vsz = vec_full_reg_size(s); - TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16); + TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16); tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -4243,7 +4243,7 @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg, if (sve_access_check(s)) { TCGContext *tcg_ctx = s->uc->tcg_ctx; unsigned vsz = vec_full_reg_size(s); - TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, is_fp16); + TCGv_ptr status = get_fpstatus_ptr(s, is_fp16); tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), pred_full_reg_offset(s, pg), @@ -4390,7 +4390,7 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, int mode) TCGContext *tcg_ctx = s->uc->tcg_ctx; unsigned vsz = vec_full_reg_size(s); TCGv_i32 tmode = tcg_const_i32(tcg_ctx, mode); - TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16); + TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16); gen_helper_set_rmode(tcg_ctx, tmode, tmode, status); diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c index a8a12fa1..34bfb0aa 100644 --- a/qemu/target/arm/translate.c +++ b/qemu/target/arm/translate.c @@ -180,8 +180,10 @@ static inline TCGv_i32 load_cpu_offset(struct uc_struct *uc, int offset) #define load_cpu_field(uc, name) load_cpu_offset(uc, offsetof(CPUARMState, name)) -static inline void store_cpu_offset(TCGContext *tcg_ctx, TCGv_i32 var, int offset) +static inline void store_cpu_offset(DisasContext *s, TCGv_i32 var, int offset) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; + tcg_gen_st_i32(tcg_ctx, var, tcg_ctx->cpu_env, offset); tcg_temp_free_i32(tcg_ctx, var); } @@ -818,8 +820,9 @@ static void gen_thumb2_parallel_addsub(DisasContext *s, int op1, int op2, TCGv_i * Generate a conditional based on ARM condition code cc. * This is common between ARM and Aarch64 targets. */ -void arm_test_cc(TCGContext *tcg_ctx, DisasCompare *cmp, int cc) +void arm_test_cc(DisasContext *s, DisasCompare *cmp, int cc) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 value; TCGCond cond; bool global = true; @@ -904,24 +907,28 @@ void arm_test_cc(TCGContext *tcg_ctx, DisasCompare *cmp, int cc) cmp->value_global = global; } -void arm_free_cc(TCGContext *tcg_ctx, DisasCompare *cmp) +void arm_free_cc(DisasContext *s, DisasCompare *cmp) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; + if (!cmp->value_global) { tcg_temp_free_i32(tcg_ctx, cmp->value); } } -void arm_jump_cc(TCGContext *tcg_ctx, DisasCompare *cmp, TCGLabel *label) +void arm_jump_cc(DisasContext *s, DisasCompare *cmp, TCGLabel *label) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; + tcg_gen_brcondi_i32(tcg_ctx, cmp->cond, cmp->value, 0, label); } -void arm_gen_test_cc(TCGContext *tcg_ctx, int cc, TCGLabel *label) +void arm_gen_test_cc(DisasContext *s, int cc, TCGLabel *label) { DisasCompare cmp; - arm_test_cc(tcg_ctx, &cmp, cc); - arm_jump_cc(tcg_ctx, &cmp, label); - arm_free_cc(tcg_ctx, &cmp); + arm_test_cc(s, &cmp, cc); + arm_jump_cc(s, &cmp, label); + arm_free_cc(s, &cmp); } static const uint8_t table_logic_cc[16] = { @@ -951,7 +958,7 @@ static inline void gen_set_condexec(DisasContext *s) uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1); TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx); tcg_gen_movi_i32(tcg_ctx, tmp, val); - store_cpu_field(tcg_ctx, tmp, condexec_bits); + store_cpu_field(s, tmp, condexec_bits); } } @@ -986,7 +993,7 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var) s->base.is_jmp = DISAS_JUMP; tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_R[15], var, ~1); tcg_gen_andi_i32(tcg_ctx, var, var, 1); - store_cpu_field(tcg_ctx, var, thumb); + store_cpu_field(s, var, thumb); } /* Set PC and Thumb state from var. var is marked as dead. @@ -1629,31 +1636,36 @@ neon_reg_offset (int reg, int n) return vfp_reg_offset(0, sreg); } -static TCGv_i32 neon_load_reg(TCGContext *tcg_ctx, int reg, int pass) +static TCGv_i32 neon_load_reg(DisasContext *s, int reg, int pass) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx); tcg_gen_ld_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, neon_reg_offset(reg, pass)); return tmp; } -static void neon_store_reg(TCGContext *tcg_ctx, int reg, int pass, TCGv_i32 var) +static void neon_store_reg(DisasContext *s, int reg, int pass, TCGv_i32 var) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; tcg_gen_st_i32(tcg_ctx, var, tcg_ctx->cpu_env, neon_reg_offset(reg, pass)); tcg_temp_free_i32(tcg_ctx, var); } -static inline void neon_load_reg64(TCGContext *tcg_ctx, TCGv_i64 var, int reg) +static inline void neon_load_reg64(DisasContext *s, TCGv_i64 var, int reg) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; tcg_gen_ld_i64(tcg_ctx, var, tcg_ctx->cpu_env, vfp_reg_offset(1, reg)); } -static inline void neon_store_reg64(TCGContext *tcg_ctx, TCGv_i64 var, int reg) +static inline void neon_store_reg64(DisasContext *s, TCGv_i64 var, int reg) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; tcg_gen_st_i64(tcg_ctx, var, tcg_ctx->cpu_env, vfp_reg_offset(1, reg)); } -static TCGv_ptr vfp_reg_ptr(TCGContext *tcg_ctx, bool dp, int reg) +static TCGv_ptr vfp_reg_ptr(DisasContext *s, bool dp, int reg) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_ptr ret = tcg_temp_new_ptr(tcg_ctx); tcg_gen_addi_ptr(tcg_ctx, ret, tcg_ctx->cpu_env, vfp_reg_offset(dp, reg)); return ret; @@ -1840,7 +1852,7 @@ static void gen_op_iwmmxt_set_mup(DisasContext *s) TCGv_i32 tmp; tmp = load_cpu_field(s->uc, iwmmxt.cregs[ARM_IWMMXT_wCon]); tcg_gen_ori_i32(tcg_ctx, tmp, tmp, 2); - store_cpu_field(tcg_ctx, tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); + store_cpu_field(s, tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); } static void gen_op_iwmmxt_set_cup(DisasContext *s) @@ -1849,7 +1861,7 @@ static void gen_op_iwmmxt_set_cup(DisasContext *s) TCGv_i32 tmp; tmp = load_cpu_field(s->uc, iwmmxt.cregs[ARM_IWMMXT_wCon]); tcg_gen_ori_i32(tcg_ctx, tmp, tmp, 1); - store_cpu_field(tcg_ctx, tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); + store_cpu_field(s, tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); } static void gen_op_iwmmxt_setpsr_nz(DisasContext *s) @@ -1857,7 +1869,7 @@ static void gen_op_iwmmxt_setpsr_nz(DisasContext *s) TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx); gen_helper_iwmmxt_setpsr_nz(tcg_ctx, tmp, s->M0); - store_cpu_field(tcg_ctx, tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]); + store_cpu_field(s, tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]); } static inline void gen_op_iwmmxt_addl_M0_wRn(DisasContext *s, int rn) @@ -3487,7 +3499,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) } if (insn & ARM_CP_RW_BIT) { /* vfp->arm */ - tmp = neon_load_reg(tcg_ctx, rn, pass); + tmp = neon_load_reg(s, rn, pass); switch (size) { case 0: if (offset) @@ -3529,26 +3541,26 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) for (n = 0; n <= pass * 2; n++) { tmp2 = tcg_temp_new_i32(tcg_ctx); tcg_gen_mov_i32(tcg_ctx, tmp2, tmp); - neon_store_reg(tcg_ctx, rn, n, tmp2); + neon_store_reg(s, rn, n, tmp2); } - neon_store_reg(tcg_ctx, rn, n, tmp); + neon_store_reg(s, rn, n, tmp); } else { /* VMOV */ switch (size) { case 0: - tmp2 = neon_load_reg(tcg_ctx, rn, pass); + tmp2 = neon_load_reg(s, rn, pass); tcg_gen_deposit_i32(tcg_ctx, tmp, tmp2, tmp, offset, 8); tcg_temp_free_i32(tcg_ctx, tmp2); break; case 1: - tmp2 = neon_load_reg(tcg_ctx, rn, pass); + tmp2 = neon_load_reg(s, rn, pass); tcg_gen_deposit_i32(tcg_ctx, tmp, tmp2, tmp, offset, 16); tcg_temp_free_i32(tcg_ctx, tmp2); break; case 2: break; } - neon_store_reg(tcg_ctx, rn, pass, tmp); + neon_store_reg(s, rn, pass, tmp); } } } else { /* !dp */ @@ -3646,7 +3658,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) * For now, keep the EN bit only */ tmp = load_reg(s, rd); tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 1 << 30); - store_cpu_field(tcg_ctx, tmp, vfp.xregs[rn]); + store_cpu_field(s, tmp, vfp.xregs[rn]); gen_lookup_tb(s); break; case ARM_VFP_FPINST: @@ -3655,7 +3667,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) return 1; } tmp = load_reg(s, rd); - store_cpu_field(tcg_ctx, tmp, vfp.xregs[rn]); + store_cpu_field(s, tmp, vfp.xregs[rn]); break; default: return 1; @@ -3946,7 +3958,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */ { TCGv_ptr fpst = get_fpstatus_ptr(s, false); - TCGv_i32 ahp_mode = get_ahp_flag(tcg_ctx); + TCGv_i32 ahp_mode = get_ahp_flag(s); tmp = gen_vfp_mrs(s); tcg_gen_ext16u_i32(tcg_ctx, tmp, tmp); if (dp) { @@ -3964,7 +3976,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) case 5: /* vcvtt.f32.f16, vcvtt.f64.f16 */ { TCGv_ptr fpst = get_fpstatus_ptr(s, false); - TCGv_i32 ahp = get_ahp_flag(tcg_ctx); + TCGv_i32 ahp = get_ahp_flag(s); tmp = gen_vfp_mrs(s); tcg_gen_shri_i32(tcg_ctx, tmp, tmp, 16); if (dp) { @@ -3982,7 +3994,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) case 6: /* vcvtb.f16.f32, vcvtb.f16.f64 */ { TCGv_ptr fpst = get_fpstatus_ptr(s, false); - TCGv_i32 ahp = get_ahp_flag(tcg_ctx); + TCGv_i32 ahp = get_ahp_flag(s); tmp = tcg_temp_new_i32(tcg_ctx); if (dp) { @@ -4005,7 +4017,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) case 7: /* vcvtt.f16.f32, vcvtt.f16.f64 */ { TCGv_ptr fpst = get_fpstatus_ptr(s, false); - TCGv_i32 ahp = get_ahp_flag(tcg_ctx); + TCGv_i32 ahp = get_ahp_flag(s); tmp = tcg_temp_new_i32(tcg_ctx); if (dp) { gen_helper_vfp_fcvt_f64_to_f16(tcg_ctx, tmp, s->F0d, @@ -4473,7 +4485,7 @@ static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv_i32 t0) tcg_gen_andi_i32(tcg_ctx, tmp, tmp, ~mask); tcg_gen_andi_i32(tcg_ctx, t0, t0, mask); tcg_gen_or_i32(tcg_ctx, tmp, tmp, t0); - store_cpu_field(tcg_ctx, tmp, spsr); + store_cpu_field(s, tmp, spsr); } else { gen_set_cpsr(s, t0, mask); } @@ -4850,45 +4862,47 @@ static inline void gen_neon_rsb(DisasContext *s, int size, TCGv_i32 t0, TCGv_i32 default: return 1; \ }} while (0) -static TCGv_i32 neon_load_scratch(TCGContext *tcg_ctx, int scratch) +static TCGv_i32 neon_load_scratch(DisasContext *s, int scratch) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx); tcg_gen_ld_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPUARMState, vfp.scratch[scratch])); return tmp; } -static void neon_store_scratch(TCGContext *tcg_ctx, int scratch, TCGv_i32 var) +static void neon_store_scratch(DisasContext *s, int scratch, TCGv_i32 var) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; tcg_gen_st_i32(tcg_ctx, var, tcg_ctx->cpu_env, offsetof(CPUARMState, vfp.scratch[scratch])); tcg_temp_free_i32(tcg_ctx, var); } static inline TCGv_i32 neon_get_scalar(DisasContext *s, int size, int reg) { - TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 tmp; if (size == 1) { - tmp = neon_load_reg(tcg_ctx, reg & 7, reg >> 4); + tmp = neon_load_reg(s, reg & 7, reg >> 4); if (reg & 8) { gen_neon_dup_high16(s, tmp); } else { gen_neon_dup_low16(s, tmp); } } else { - tmp = neon_load_reg(tcg_ctx, reg & 15, reg >> 4); + tmp = neon_load_reg(s, reg & 15, reg >> 4); } return tmp; } -static int gen_neon_unzip(TCGContext *tcg_ctx, int rd, int rm, int size, int q) +static int gen_neon_unzip(DisasContext *s, int rd, int rm, int size, int q) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_ptr pd, pm; - + if (!q && size == 2) { return 1; } - pd = vfp_reg_ptr(tcg_ctx, true, rd); - pm = vfp_reg_ptr(tcg_ctx, true, rm); + pd = vfp_reg_ptr(s, true, rd); + pm = vfp_reg_ptr(s, true, rm); if (q) { switch (size) { case 0: @@ -4920,15 +4934,16 @@ static int gen_neon_unzip(TCGContext *tcg_ctx, int rd, int rm, int size, int q) return 0; } -static int gen_neon_zip(TCGContext *tcg_ctx, int rd, int rm, int size, int q) +static int gen_neon_zip(DisasContext *s, int rd, int rm, int size, int q) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_ptr pd, pm; if (!q && size == 2) { return 1; } - pd = vfp_reg_ptr(tcg_ctx, true, rd); - pm = vfp_reg_ptr(tcg_ctx, true, rm); + pd = vfp_reg_ptr(s, true, rd); + pm = vfp_reg_ptr(s, true, rm); if (q) { switch (size) { case 0: @@ -4960,8 +4975,9 @@ static int gen_neon_zip(TCGContext *tcg_ctx, int rd, int rm, int size, int q) return 0; } -static void gen_neon_trn_u8(TCGContext *tcg_ctx, TCGv_i32 t0, TCGv_i32 t1) +static void gen_neon_trn_u8(DisasContext *s, TCGv_i32 t0, TCGv_i32 t1) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 rd, tmp; rd = tcg_temp_new_i32(tcg_ctx); @@ -4982,8 +4998,9 @@ static void gen_neon_trn_u8(TCGContext *tcg_ctx, TCGv_i32 t0, TCGv_i32 t1) tcg_temp_free_i32(tcg_ctx, rd); } -static void gen_neon_trn_u16(TCGContext *tcg_ctx, TCGv_i32 t0, TCGv_i32 t1) +static void gen_neon_trn_u16(DisasContext *s, TCGv_i32 t0, TCGv_i32 t1) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 rd, tmp; rd = tcg_temp_new_i32(tcg_ctx); @@ -5099,9 +5116,9 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) tmp64 = tcg_temp_new_i64(tcg_ctx); if (load) { gen_aa32_ld64(s, tmp64, addr, get_mem_index(s)); - neon_store_reg64(tcg_ctx, tmp64, rd); + neon_store_reg64(s, tmp64, rd); } else { - neon_load_reg64(tcg_ctx, tmp64, rd); + neon_load_reg64(s, tmp64, rd); gen_aa32_st64(s, tmp64, addr, get_mem_index(s)); } tcg_temp_free_i64(tcg_ctx, tmp64); @@ -5112,9 +5129,9 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) if (load) { tmp = tcg_temp_new_i32(tcg_ctx); gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - neon_store_reg(tcg_ctx, rd, pass, tmp); + neon_store_reg(s, rd, pass, tmp); } else { - tmp = neon_load_reg(tcg_ctx, rd, pass); + tmp = neon_load_reg(s, rd, pass); gen_aa32_st32(s, tmp, addr, get_mem_index(s)); tcg_temp_free_i32(tcg_ctx, tmp); } @@ -5130,9 +5147,9 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) tcg_gen_shli_i32(tcg_ctx, tmp2, tmp2, 16); tcg_gen_or_i32(tcg_ctx, tmp, tmp, tmp2); tcg_temp_free_i32(tcg_ctx, tmp2); - neon_store_reg(tcg_ctx, rd, pass, tmp); + neon_store_reg(s, rd, pass, tmp); } else { - tmp = neon_load_reg(tcg_ctx, rd, pass); + tmp = neon_load_reg(s, rd, pass); tmp2 = tcg_temp_new_i32(tcg_ctx); tcg_gen_shri_i32(tcg_ctx, tmp2, tmp, 16); gen_aa32_st16(s, tmp, addr, get_mem_index(s)); @@ -5157,9 +5174,9 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tcg_ctx, tmp); } } - neon_store_reg(tcg_ctx, rd, pass, tmp2); + neon_store_reg(s, rd, pass, tmp2); } else { - tmp2 = neon_load_reg(tcg_ctx, rd, pass); + tmp2 = neon_load_reg(s, rd, pass); for (n = 0; n < 4; n++) { tmp = tcg_temp_new_i32(tcg_ctx); if (n == 0) { @@ -5303,14 +5320,14 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) abort(); } if (size != 2) { - tmp2 = neon_load_reg(tcg_ctx, rd, pass); + tmp2 = neon_load_reg(s, rd, pass); tcg_gen_deposit_i32(tcg_ctx, tmp, tmp2, tmp, shift, size ? 16 : 8); tcg_temp_free_i32(tcg_ctx, tmp2); } - neon_store_reg(tcg_ctx, rd, pass, tmp); + neon_store_reg(s, rd, pass, tmp); } else { /* Store */ - tmp = neon_load_reg(tcg_ctx, rd, pass); + tmp = neon_load_reg(s, rd, pass); if (shift) tcg_gen_shri_i32(tcg_ctx, tmp, tmp, shift); switch (size) { @@ -5883,9 +5900,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)) { return 1; } - ptr1 = vfp_reg_ptr(tcg_ctx, true, rd); - ptr2 = vfp_reg_ptr(tcg_ctx, true, rn); - ptr3 = vfp_reg_ptr(tcg_ctx, true, rm); + ptr1 = vfp_reg_ptr(s, true, rd); + ptr2 = vfp_reg_ptr(s, true, rn); + ptr3 = vfp_reg_ptr(s, true, rm); tmp4 = tcg_const_i32(tcg_ctx, size); gen_helper_crypto_sha1_3reg(tcg_ctx, ptr1, ptr2, ptr3, tmp4); tcg_temp_free_i32(tcg_ctx, tmp4); @@ -5893,9 +5910,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA256) || size == 3) { return 1; } - ptr1 = vfp_reg_ptr(tcg_ctx, true, rd); - ptr2 = vfp_reg_ptr(tcg_ctx, true, rn); - ptr3 = vfp_reg_ptr(tcg_ctx, true, rm); + ptr1 = vfp_reg_ptr(s, true, rd); + ptr2 = vfp_reg_ptr(s, true, rn); + ptr3 = vfp_reg_ptr(s, true, rm); switch (size) { case 0: gen_helper_crypto_sha256h(tcg_ctx, ptr1, ptr2, ptr3); @@ -5950,8 +5967,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) if (size == 3 && op != NEON_3R_LOGIC) { /* 64-bit element instructions. */ for (pass = 0; pass < (q ? 2 : 1); pass++) { - neon_load_reg64(tcg_ctx, s->V0, rn + pass); - neon_load_reg64(tcg_ctx, s->V1, rm + pass); + neon_load_reg64(s, s->V0, rn + pass); + neon_load_reg64(s, s->V1, rm + pass); switch (op) { case NEON_3R_VQADD: if (u) { @@ -6013,7 +6030,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) default: abort(); } - neon_store_reg64(tcg_ctx, s->V0, rd + pass); + neon_store_reg64(s, s->V0, rd + pass); } return 0; } @@ -6084,16 +6101,16 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) if (pairwise) { /* Pairwise. */ if (pass < 1) { - tmp = neon_load_reg(tcg_ctx, rn, 0); - tmp2 = neon_load_reg(tcg_ctx, rn, 1); + tmp = neon_load_reg(s, rn, 0); + tmp2 = neon_load_reg(s, rn, 1); } else { - tmp = neon_load_reg(tcg_ctx, rm, 0); - tmp2 = neon_load_reg(tcg_ctx, rm, 1); + tmp = neon_load_reg(s, rm, 0); + tmp2 = neon_load_reg(s, rm, 1); } } else { /* Elementwise. */ - tmp = neon_load_reg(tcg_ctx, rn, pass); - tmp2 = neon_load_reg(tcg_ctx, rm, pass); + tmp = neon_load_reg(s, rn, pass); + tmp2 = neon_load_reg(s, rm, pass); } switch (op) { case NEON_3R_VHADD: @@ -6123,17 +6140,17 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_gen_xor_i32(tcg_ctx, tmp, tmp, tmp2); break; case 5: /* VBSL */ - tmp3 = neon_load_reg(tcg_ctx, rd, pass); + tmp3 = neon_load_reg(s, rd, pass); gen_neon_bsl(s, tmp, tmp, tmp2, tmp3); tcg_temp_free_i32(tcg_ctx, tmp3); break; case 6: /* VBIT */ - tmp3 = neon_load_reg(tcg_ctx, rd, pass); + tmp3 = neon_load_reg(s, rd, pass); gen_neon_bsl(s, tmp, tmp, tmp3, tmp2); tcg_temp_free_i32(tcg_ctx, tmp3); break; case 7: /* VBIF */ - tmp3 = neon_load_reg(tcg_ctx, rd, pass); + tmp3 = neon_load_reg(s, rd, pass); gen_neon_bsl(s, tmp, tmp3, tmp, tmp2); tcg_temp_free_i32(tcg_ctx, tmp3); break; @@ -6175,7 +6192,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VABA: GEN_NEON_INTEGER_OP(abd); tcg_temp_free_i32(tcg_ctx, tmp2); - tmp2 = neon_load_reg(tcg_ctx, rd, pass); + tmp2 = neon_load_reg(s, rd, pass); gen_neon_add(s, size, tmp, tmp2); break; case NEON_3R_VADD_VSUB: @@ -6215,7 +6232,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) default: abort(); } tcg_temp_free_i32(tcg_ctx, tmp2); - tmp2 = neon_load_reg(tcg_ctx, rd, pass); + tmp2 = neon_load_reg(s, rd, pass); if (u) { /* VMLS */ gen_neon_rsb(s, size, tmp, tmp2); } else { /* VMLA */ @@ -6297,7 +6314,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) gen_helper_vfp_muls(tcg_ctx, tmp, tmp, tmp2, fpstatus); if (!u) { tcg_temp_free_i32(tcg_ctx, tmp2); - tmp2 = neon_load_reg(tcg_ctx, rd, pass); + tmp2 = neon_load_reg(s, rd, pass); if (size == 0) { gen_helper_vfp_adds(tcg_ctx, tmp, tmp, tmp2, fpstatus); } else { @@ -6366,7 +6383,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) { /* VFMA, VFMS: fused multiply-add */ TCGv_ptr fpstatus = get_fpstatus_ptr(s, 1); - TCGv_i32 tmp3 = neon_load_reg(tcg_ctx, rd, pass); + TCGv_i32 tmp3 = neon_load_reg(s, rd, pass); if (size) { /* VFMS */ gen_helper_vfp_negs(tcg_ctx, tmp, tmp); @@ -6385,16 +6402,16 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) straight into the destination register. For pairwise operations we have to be careful to avoid clobbering the source operands. */ if (pairwise && rd == rm) { - neon_store_scratch(tcg_ctx, pass, tmp); + neon_store_scratch(s, pass, tmp); } else { - neon_store_reg(tcg_ctx, rd, pass, tmp); + neon_store_reg(s, rd, pass, tmp); } } /* for pass */ if (pairwise && rd == rm) { for (pass = 0; pass < (q ? 4 : 2); pass++) { - tmp = neon_load_scratch(tcg_ctx, pass); - neon_store_reg(tcg_ctx, rd, pass, tmp); + tmp = neon_load_scratch(s, pass); + neon_store_reg(s, rd, pass, tmp); } } /* End of 3 register same size operations. */ @@ -6454,7 +6471,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) for (pass = 0; pass < count; pass++) { if (size == 3) { - neon_load_reg64(tcg_ctx, s->V0, rm + pass); + neon_load_reg64(s, s->V0, rm + pass); tcg_gen_movi_i64(tcg_ctx, s->V1, imm); switch (op) { case 0: /* VSHR */ @@ -6491,11 +6508,11 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } if (op == 1 || op == 3) { /* Accumulate. */ - neon_load_reg64(tcg_ctx, s->V1, rd + pass); + neon_load_reg64(s, s->V1, rd + pass); tcg_gen_add_i64(tcg_ctx, s->V0, s->V0, s->V1); } else if (op == 4 || (op == 5 && u)) { /* Insert */ - neon_load_reg64(tcg_ctx, s->V1, rd + pass); + neon_load_reg64(s, s->V1, rd + pass); uint64_t mask; if (shift < -63 || shift > 63) { mask = 0; @@ -6509,10 +6526,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_gen_andi_i64(tcg_ctx, s->V1, s->V1, ~mask); tcg_gen_or_i64(tcg_ctx, s->V0, s->V0, s->V1); } - neon_store_reg64(tcg_ctx, s->V0, rd + pass); + neon_store_reg64(s, s->V0, rd + pass); } else { /* size < 3 */ /* Operands in T0 and T1. */ - tmp = neon_load_reg(tcg_ctx, rm, pass); + tmp = neon_load_reg(s, rm, pass); tmp2 = tcg_temp_new_i32(tcg_ctx); tcg_gen_movi_i32(tcg_ctx, tmp2, imm); switch (op) { @@ -6559,7 +6576,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) if (op == 1 || op == 3) { /* Accumulate. */ - tmp2 = neon_load_reg(tcg_ctx, rd, pass); + tmp2 = neon_load_reg(s, rd, pass); gen_neon_add(s, size, tmp, tmp2); tcg_temp_free_i32(tcg_ctx, tmp2); } else if (op == 4 || (op == 5 && u)) { @@ -6593,13 +6610,13 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) default: abort(); } - tmp2 = neon_load_reg(tcg_ctx, rd, pass); + tmp2 = neon_load_reg(s, rd, pass); tcg_gen_andi_i32(tcg_ctx, tmp, tmp, mask); tcg_gen_andi_i32(tcg_ctx, tmp2, tmp2, ~mask); tcg_gen_or_i32(tcg_ctx, tmp, tmp, tmp2); tcg_temp_free_i32(tcg_ctx, tmp2); } - neon_store_reg(tcg_ctx, rd, pass, tmp); + neon_store_reg(s, rd, pass, tmp); } } /* for pass */ } else if (op < 10) { @@ -6613,8 +6630,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) size++; if (size == 3) { tmp64 = tcg_const_i64(tcg_ctx, shift); - neon_load_reg64(tcg_ctx, s->V0, rm); - neon_load_reg64(tcg_ctx, s->V1, rm + 1); + neon_load_reg64(s, s->V0, rm); + neon_load_reg64(s, s->V1, rm + 1); for (pass = 0; pass < 2; pass++) { TCGv_i64 in; if (pass == 0) { @@ -6637,7 +6654,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } tmp = tcg_temp_new_i32(tcg_ctx); gen_neon_narrow_op(s, op == 8, u, size - 1, tmp, s->V0); - neon_store_reg(tcg_ctx, rd, pass, tmp); + neon_store_reg(s, rd, pass, tmp); } /* for pass */ tcg_temp_free_i64(tcg_ctx, tmp64); } else { @@ -6649,18 +6666,18 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) imm = (uint32_t)shift; } tmp2 = tcg_const_i32(tcg_ctx, imm); - tmp4 = neon_load_reg(tcg_ctx, rm + 1, 0); - tmp5 = neon_load_reg(tcg_ctx, rm + 1, 1); + tmp4 = neon_load_reg(s, rm + 1, 0); + tmp5 = neon_load_reg(s, rm + 1, 1); for (pass = 0; pass < 2; pass++) { if (pass == 0) { - tmp = neon_load_reg(tcg_ctx, rm, 0); + tmp = neon_load_reg(s, rm, 0); } else { tmp = tmp4; } gen_neon_shift_narrow(s, size, tmp, tmp2, q, input_unsigned); if (pass == 0) { - tmp3 = neon_load_reg(tcg_ctx, rm, 1); + tmp3 = neon_load_reg(s, rm, 1); } else { tmp3 = tmp5; } @@ -6671,7 +6688,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tcg_ctx, tmp3); tmp = tcg_temp_new_i32(tcg_ctx); gen_neon_narrow_op(s, op == 8, u, size - 1, tmp, s->V0); - neon_store_reg(tcg_ctx, rd, pass, tmp); + neon_store_reg(s, rd, pass, tmp); } /* for pass */ tcg_temp_free_i32(tcg_ctx, tmp2); } @@ -6680,8 +6697,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) if (q || (rd & 1)) { return 1; } - tmp = neon_load_reg(tcg_ctx, rm, 0); - tmp2 = neon_load_reg(tcg_ctx, rm, 1); + tmp = neon_load_reg(s, rm, 0); + tmp2 = neon_load_reg(s, rm, 1); for (pass = 0; pass < 2; pass++) { if (pass == 1) tmp = tmp2; @@ -6716,7 +6733,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_gen_andi_i64(tcg_ctx, s->V0, s->V0, ~imm64); } } - neon_store_reg64(tcg_ctx, s->V0, rd + pass); + neon_store_reg64(s, s->V0, rd + pass); } } else if (op >= 14) { /* VCVT fixed-point. */ @@ -6802,7 +6819,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) for (pass = 0; pass < (q ? 4 : 2); pass++) { if (op & 1 && op < 12) { - tmp = neon_load_reg(tcg_ctx, rd, pass); + tmp = neon_load_reg(s, rd, pass); if (invert) { /* The immediate value has already been inverted, so BIC becomes AND. */ @@ -6826,7 +6843,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_gen_movi_i32(tcg_ctx, tmp, imm); } } - neon_store_reg(tcg_ctx, rd, pass, tmp); + neon_store_reg(s, rd, pass, tmp); } } } else { /* (insn & 0x00800010 == 0x00800000) */ @@ -6891,12 +6908,12 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_rn = tcg_temp_new_i64(tcg_ctx); tcg_rm = tcg_temp_new_i64(tcg_ctx); tcg_rd = tcg_temp_new_i64(tcg_ctx); - neon_load_reg64(tcg_ctx, tcg_rn, rn); - neon_load_reg64(tcg_ctx, tcg_rm, rm); + neon_load_reg64(s, tcg_rn, rn); + neon_load_reg64(s, tcg_rm, rm); gen_helper_neon_pmull_64_lo(tcg_ctx, tcg_rd, tcg_rn, tcg_rm); - neon_store_reg64(tcg_ctx, tcg_rd, rd); + neon_store_reg64(s, tcg_rd, rd); gen_helper_neon_pmull_64_hi(tcg_ctx, tcg_rd, tcg_rn, tcg_rm); - neon_store_reg64(tcg_ctx, tcg_rd, rd + 1); + neon_store_reg64(s, tcg_rd, rd + 1); tcg_temp_free_i64(tcg_ctx, tcg_rn); tcg_temp_free_i64(tcg_ctx, tcg_rm); tcg_temp_free_i64(tcg_ctx, tcg_rd); @@ -6907,35 +6924,35 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) always aligned so will never overlap with wide destinations in problematic ways. */ if (rd == rm && !src2_wide) { - tmp = neon_load_reg(tcg_ctx, rm, 1); - neon_store_scratch(tcg_ctx, 2, tmp); + tmp = neon_load_reg(s, rm, 1); + neon_store_scratch(s, 2, tmp); } else if (rd == rn && !src1_wide) { - tmp = neon_load_reg(tcg_ctx, rn, 1); - neon_store_scratch(tcg_ctx, 2, tmp); + tmp = neon_load_reg(s, rn, 1); + neon_store_scratch(s, 2, tmp); } tmp3 = NULL; for (pass = 0; pass < 2; pass++) { if (src1_wide) { - neon_load_reg64(tcg_ctx, s->V0, rn + pass); + neon_load_reg64(s, s->V0, rn + pass); tmp = NULL; } else { if (pass == 1 && rd == rn) { - tmp = neon_load_scratch(tcg_ctx, 2); + tmp = neon_load_scratch(s, 2); } else { - tmp = neon_load_reg(tcg_ctx, rn, pass); + tmp = neon_load_reg(s, rn, pass); } if (prewiden) { gen_neon_widen(s, s->V0, tmp, size, u); } } if (src2_wide) { - neon_load_reg64(tcg_ctx, s->V1, rm + pass); + neon_load_reg64(s, s->V1, rm + pass); tmp2 = NULL; } else { if (pass == 1 && rd == rm) { - tmp2 = neon_load_scratch(tcg_ctx, 2); + tmp2 = neon_load_scratch(s, 2); } else { - tmp2 = neon_load_reg(tcg_ctx, rm, pass); + tmp2 = neon_load_reg(s, rm, pass); } if (prewiden) { gen_neon_widen(s, s->V1, tmp2, size, u); @@ -6988,10 +7005,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) if (op == 13) { /* VQDMULL */ gen_neon_addl_saturate(s, s->V0, s->V0, size); - neon_store_reg64(tcg_ctx, s->V0, rd + pass); + neon_store_reg64(s, s->V0, rd + pass); } else if (op == 5 || (op >= 8 && op <= 11)) { /* Accumulate. */ - neon_load_reg64(tcg_ctx, s->V1, rd + pass); + neon_load_reg64(s, s->V1, rd + pass); switch (op) { case 10: /* VMLSL */ gen_neon_negl(s, s->V0, size); @@ -7009,7 +7026,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) default: abort(); } - neon_store_reg64(tcg_ctx, s->V0, rd + pass); + neon_store_reg64(s, s->V0, rd + pass); } else if (op == 4 || op == 6) { /* Narrowing operation. */ tmp = tcg_temp_new_i32(tcg_ctx); @@ -7046,12 +7063,12 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) if (pass == 0) { tmp3 = tmp; } else { - neon_store_reg(tcg_ctx, rd, 0, tmp3); - neon_store_reg(tcg_ctx, rd, 1, tmp); + neon_store_reg(s, rd, 0, tmp3); + neon_store_reg(s, rd, 1, tmp); } } else { /* Write back the result. */ - neon_store_reg64(tcg_ctx, s->V0, rd + pass); + neon_store_reg64(s, s->V0, rd + pass); } } } else { @@ -7079,10 +7096,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) return 1; } tmp = neon_get_scalar(s, size, rm); - neon_store_scratch(tcg_ctx, 0, tmp); + neon_store_scratch(s, 0, tmp); for (pass = 0; pass < (u ? 4 : 2); pass++) { - tmp = neon_load_scratch(tcg_ctx, 0); - tmp2 = neon_load_reg(tcg_ctx, rn, pass); + tmp = neon_load_scratch(s, 0); + tmp2 = neon_load_reg(s, rn, pass); if (op == 12) { if (size == 1) { gen_helper_neon_qdmulh_s16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2); @@ -7110,7 +7127,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tcg_ctx, tmp2); if (op < 8) { /* Accumulate. */ - tmp2 = neon_load_reg(tcg_ctx, rd, pass); + tmp2 = neon_load_reg(s, rd, pass); switch (op) { case 0: gen_neon_add(s, size, tmp, tmp2); @@ -7137,7 +7154,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } tcg_temp_free_i32(tcg_ctx, tmp2); } - neon_store_reg(tcg_ctx, rd, pass, tmp); + neon_store_reg(s, rd, pass, tmp); } break; case 3: /* VQDMLAL scalar */ @@ -7158,18 +7175,18 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) * deletes it during pass 0. */ tmp4 = tcg_temp_new_i32(tcg_ctx); tcg_gen_mov_i32(tcg_ctx, tmp4, tmp2); - tmp3 = neon_load_reg(tcg_ctx, rn, 1); + tmp3 = neon_load_reg(s, rn, 1); for (pass = 0; pass < 2; pass++) { if (pass == 0) { - tmp = neon_load_reg(tcg_ctx, rn, 0); + tmp = neon_load_reg(s, rn, 0); } else { tmp = tmp3; tmp2 = tmp4; } gen_neon_mull(s, s->V0, tmp, tmp2, size, u); if (op != 11) { - neon_load_reg64(tcg_ctx, s->V1, rd + pass); + neon_load_reg64(s, s->V1, rd + pass); } switch (op) { case 6: @@ -7194,7 +7211,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) default: abort(); } - neon_store_reg64(tcg_ctx, s->V0, rd + pass); + neon_store_reg64(s, s->V0, rd + pass); } break; case 14: /* VQRDMLAH scalar */ @@ -7224,11 +7241,11 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tmp2 = neon_get_scalar(s, size, rm); for (pass = 0; pass < (u ? 4 : 2); pass++) { - tmp = neon_load_reg(tcg_ctx, rn, pass); - tmp3 = neon_load_reg(tcg_ctx, rd, pass); + tmp = neon_load_reg(s, rn, pass); + tmp3 = neon_load_reg(s, rd, pass); fn(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2, tmp3); tcg_temp_free_i32(tcg_ctx, tmp3); - neon_store_reg(tcg_ctx, rd, pass, tmp); + neon_store_reg(s, rd, pass, tmp); } tcg_temp_free_i32(tcg_ctx, tmp2); } @@ -7250,31 +7267,31 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } if (imm == 0) { - neon_load_reg64(tcg_ctx, s->V0, rn); + neon_load_reg64(s, s->V0, rn); if (q) { - neon_load_reg64(tcg_ctx, s->V1, rn + 1); + neon_load_reg64(s, s->V1, rn + 1); } } else if (imm == 8) { - neon_load_reg64(tcg_ctx, s->V0, rn + 1); + neon_load_reg64(s, s->V0, rn + 1); if (q) { - neon_load_reg64(tcg_ctx, s->V1, rm); + neon_load_reg64(s, s->V1, rm); } } else if (q) { tmp64 = tcg_temp_new_i64(tcg_ctx); if (imm < 8) { - neon_load_reg64(tcg_ctx, s->V0, rn); - neon_load_reg64(tcg_ctx, tmp64, rn + 1); + neon_load_reg64(s, s->V0, rn); + neon_load_reg64(s, tmp64, rn + 1); } else { - neon_load_reg64(tcg_ctx, s->V0, rn + 1); - neon_load_reg64(tcg_ctx, tmp64, rm); + neon_load_reg64(s, s->V0, rn + 1); + neon_load_reg64(s, tmp64, rm); } tcg_gen_shri_i64(tcg_ctx, s->V0, s->V0, (imm & 7) * 8); tcg_gen_shli_i64(tcg_ctx, s->V1, tmp64, 64 - ((imm & 7) * 8)); tcg_gen_or_i64(tcg_ctx, s->V0, s->V0, s->V1); if (imm < 8) { - neon_load_reg64(tcg_ctx, s->V1, rm); + neon_load_reg64(s, s->V1, rm); } else { - neon_load_reg64(tcg_ctx, s->V1, rm + 1); + neon_load_reg64(s, s->V1, rm + 1); imm -= 8; } tcg_gen_shli_i64(tcg_ctx, s->V1, s->V1, 64 - (imm * 8)); @@ -7283,15 +7300,15 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_ctx, tmp64); } else { /* BUGFIX */ - neon_load_reg64(tcg_ctx, s->V0, rn); + neon_load_reg64(s, s->V0, rn); tcg_gen_shri_i64(tcg_ctx, s->V0, s->V0, imm * 8); - neon_load_reg64(tcg_ctx, s->V1, rm); + neon_load_reg64(s, s->V1, rm); tcg_gen_shli_i64(tcg_ctx, s->V1, s->V1, 64 - (imm * 8)); tcg_gen_or_i64(tcg_ctx, s->V0, s->V0, s->V1); } - neon_store_reg64(tcg_ctx, s->V0, rd); + neon_store_reg64(s, s->V0, rd); if (q) { - neon_store_reg64(tcg_ctx, s->V1, rd + 1); + neon_store_reg64(s, s->V1, rd + 1); } } else if ((insn & (1 << 11)) == 0) { /* Two register misc. */ @@ -7312,33 +7329,33 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) switch (op) { case NEON_2RM_VREV64: for (pass = 0; pass < (q ? 2 : 1); pass++) { - tmp = neon_load_reg(tcg_ctx, rm, pass * 2); - tmp2 = neon_load_reg(tcg_ctx, rm, pass * 2 + 1); + tmp = neon_load_reg(s, rm, pass * 2); + tmp2 = neon_load_reg(s, rm, pass * 2 + 1); switch (size) { case 0: tcg_gen_bswap32_i32(tcg_ctx, tmp, tmp); break; case 1: gen_swap_half(s, tmp); break; case 2: /* no-op */ break; default: abort(); } - neon_store_reg(tcg_ctx, rd, pass * 2 + 1, tmp); + neon_store_reg(s, rd, pass * 2 + 1, tmp); if (size == 2) { - neon_store_reg(tcg_ctx, rd, pass * 2, tmp2); + neon_store_reg(s, rd, pass * 2, tmp2); } else { switch (size) { case 0: tcg_gen_bswap32_i32(tcg_ctx, tmp2, tmp2); break; case 1: gen_swap_half(s, tmp2); break; default: abort(); } - neon_store_reg(tcg_ctx, rd, pass * 2, tmp2); + neon_store_reg(s, rd, pass * 2, tmp2); } } break; case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U: case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U: for (pass = 0; pass < q + 1; pass++) { - tmp = neon_load_reg(tcg_ctx, rm, pass * 2); + tmp = neon_load_reg(s, rm, pass * 2); gen_neon_widen(s, s->V0, tmp, size, op & 1); - tmp = neon_load_reg(tcg_ctx, rm, pass * 2 + 1); + tmp = neon_load_reg(s, rm, pass * 2 + 1); gen_neon_widen(s, s->V1, tmp, size, op & 1); switch (size) { case 0: gen_helper_neon_paddl_u16(tcg_ctx, CPU_V001); break; @@ -7348,32 +7365,32 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } if (op >= NEON_2RM_VPADAL) { /* Accumulate. */ - neon_load_reg64(tcg_ctx, s->V1, rd + pass); + neon_load_reg64(s, s->V1, rd + pass); gen_neon_addl(s, size); } - neon_store_reg64(tcg_ctx, s->V0, rd + pass); + neon_store_reg64(s, s->V0, rd + pass); } break; case NEON_2RM_VTRN: if (size == 2) { int n; for (n = 0; n < (q ? 4 : 2); n += 2) { - tmp = neon_load_reg(tcg_ctx, rm, n); - tmp2 = neon_load_reg(tcg_ctx, rd, n + 1); - neon_store_reg(tcg_ctx, rm, n, tmp2); - neon_store_reg(tcg_ctx, rd, n + 1, tmp); + tmp = neon_load_reg(s, rm, n); + tmp2 = neon_load_reg(s, rd, n + 1); + neon_store_reg(s, rm, n, tmp2); + neon_store_reg(s, rd, n + 1, tmp); } } else { goto elementwise; } break; case NEON_2RM_VUZP: - if (gen_neon_unzip(tcg_ctx, rd, rm, size, q)) { + if (gen_neon_unzip(s, rd, rm, size, q)) { return 1; } break; case NEON_2RM_VZIP: - if (gen_neon_zip(tcg_ctx, rd, rm, size, q)) { + if (gen_neon_zip(s, rd, rm, size, q)) { return 1; } break; @@ -7384,15 +7401,15 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } tmp2 = NULL; for (pass = 0; pass < 2; pass++) { - neon_load_reg64(tcg_ctx, s->V0, rm + pass); + neon_load_reg64(s, s->V0, rm + pass); tmp = tcg_temp_new_i32(tcg_ctx); gen_neon_narrow_op(s, op == NEON_2RM_VMOVN, q, size, tmp, s->V0); if (pass == 0) { tmp2 = tmp; } else { - neon_store_reg(tcg_ctx, rd, 0, tmp2); - neon_store_reg(tcg_ctx, rd, 1, tmp); + neon_store_reg(s, rd, 0, tmp2); + neon_store_reg(s, rd, 1, tmp); } } break; @@ -7400,14 +7417,14 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) if (q || (rd & 1)) { return 1; } - tmp = neon_load_reg(tcg_ctx, rm, 0); - tmp2 = neon_load_reg(tcg_ctx, rm, 1); + tmp = neon_load_reg(s, rm, 0); + tmp2 = neon_load_reg(s, rm, 1); for (pass = 0; pass < 2; pass++) { if (pass == 1) tmp = tmp2; gen_neon_widen(s, s->V0, tmp, size, 1); tcg_gen_shli_i64(tcg_ctx, s->V0, s->V0, 8 << size); - neon_store_reg64(tcg_ctx, s->V0, rd + pass); + neon_store_reg64(s, s->V0, rd + pass); } break; case NEON_2RM_VCVT_F16_F32: @@ -7422,7 +7439,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tmp = tcg_temp_new_i32(tcg_ctx); tmp2 = tcg_temp_new_i32(tcg_ctx); fpst = get_fpstatus_ptr(s, true); - ahp = get_ahp_flag(tcg_ctx); + ahp = get_ahp_flag(s); tcg_gen_ld_f32(tcg_ctx, s->F0s, tcg_ctx->cpu_env, neon_reg_offset(rm, 0)); gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tmp, s->F0s, fpst, ahp); tcg_gen_ld_f32(tcg_ctx, s->F0s, tcg_ctx->cpu_env, neon_reg_offset(rm, 1)); @@ -7432,12 +7449,12 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_gen_ld_f32(tcg_ctx, s->F0s, tcg_ctx->cpu_env, neon_reg_offset(rm, 2)); gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tmp, s->F0s, fpst, ahp); tcg_gen_ld_f32(tcg_ctx, s->F0s, tcg_ctx->cpu_env, neon_reg_offset(rm, 3)); - neon_store_reg(tcg_ctx, rd, 0, tmp2); + neon_store_reg(s, rd, 0, tmp2); tmp2 = tcg_temp_new_i32(tcg_ctx); gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tmp2, s->F0s, fpst, ahp); tcg_gen_shli_i32(tcg_ctx, tmp2, tmp2, 16); tcg_gen_or_i32(tcg_ctx, tmp2, tmp2, tmp); - neon_store_reg(tcg_ctx, rd, 1, tmp2); + neon_store_reg(s, rd, 1, tmp2); tcg_temp_free_i32(tcg_ctx, tmp); tcg_temp_free_i32(tcg_ctx, ahp); tcg_temp_free_ptr(tcg_ctx, fpst); @@ -7453,10 +7470,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) return 1; } fpst = get_fpstatus_ptr(s, true); - ahp = get_ahp_flag(tcg_ctx); + ahp = get_ahp_flag(s); tmp3 = tcg_temp_new_i32(tcg_ctx); - tmp = neon_load_reg(tcg_ctx, rm, 0); - tmp2 = neon_load_reg(tcg_ctx, rm, 1); + tmp = neon_load_reg(s, rm, 0); + tmp2 = neon_load_reg(s, rm, 1); tcg_gen_ext16u_i32(tcg_ctx, tmp3, tmp); gen_helper_vfp_fcvt_f16_to_f32(tcg_ctx, s->F0s, tmp3, fpst, ahp); tcg_gen_st_f32(tcg_ctx, s->F0s, tcg_ctx->cpu_env, neon_reg_offset(rd, 0)); @@ -7481,8 +7498,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) || ((rm | rd) & 1)) { return 1; } - ptr1 = vfp_reg_ptr(tcg_ctx, true, rd); - ptr2 = vfp_reg_ptr(tcg_ctx, true, rm); + ptr1 = vfp_reg_ptr(s, true, rd); + ptr2 = vfp_reg_ptr(s, true, rm); /* Bit 6 is the lowest opcode bit; it distinguishes between * encryption (AESE/AESMC) and decryption (AESD/AESIMC) @@ -7503,8 +7520,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) || ((rm | rd) & 1)) { return 1; } - ptr1 = vfp_reg_ptr(tcg_ctx, true, rd); - ptr2 = vfp_reg_ptr(tcg_ctx, true, rm); + ptr1 = vfp_reg_ptr(s, true, rd); + ptr2 = vfp_reg_ptr(s, true, rm); gen_helper_crypto_sha1h(tcg_ctx, ptr1, ptr2); @@ -7523,8 +7540,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } else if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)) { return 1; } - ptr1 = vfp_reg_ptr(tcg_ctx, true, rd); - ptr2 = vfp_reg_ptr(tcg_ctx, true, rm); + ptr1 = vfp_reg_ptr(s, true, rd); + ptr2 = vfp_reg_ptr(s, true, rm); if (q) { gen_helper_crypto_sha256su0(tcg_ctx, ptr1, ptr2); } else { @@ -7541,7 +7558,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) neon_reg_offset(rm, pass)); tmp = NULL; } else { - tmp = neon_load_reg(tcg_ctx, rm, pass); + tmp = neon_load_reg(s, rm, pass); } switch (op) { case NEON_2RM_VREV32: @@ -7705,17 +7722,17 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) gen_vfp_neg(s, 0); break; case NEON_2RM_VSWP: - tmp2 = neon_load_reg(tcg_ctx, rd, pass); - neon_store_reg(tcg_ctx, rm, pass, tmp2); + tmp2 = neon_load_reg(s, rd, pass); + neon_store_reg(s, rm, pass, tmp2); break; case NEON_2RM_VTRN: - tmp2 = neon_load_reg(tcg_ctx, rd, pass); + tmp2 = neon_load_reg(s, rd, pass); switch (size) { - case 0: gen_neon_trn_u8(tcg_ctx, tmp, tmp2); break; - case 1: gen_neon_trn_u16(tcg_ctx, tmp, tmp2); break; + case 0: gen_neon_trn_u8(s, tmp, tmp2); break; + case 1: gen_neon_trn_u16(s, tmp, tmp2); break; default: abort(); } - neon_store_reg(tcg_ctx, rm, pass, tmp2); + neon_store_reg(s, rm, pass, tmp2); break; case NEON_2RM_VRINTN: case NEON_2RM_VRINTA: @@ -7834,7 +7851,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_gen_st_f32(tcg_ctx, s->F0s, tcg_ctx->cpu_env, neon_reg_offset(rd, pass)); } else { - neon_store_reg(tcg_ctx, rd, pass, tmp); + neon_store_reg(s, rd, pass, tmp); } } break; @@ -7850,28 +7867,28 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } n <<= 3; if (insn & (1 << 6)) { - tmp = neon_load_reg(tcg_ctx, rd, 0); + tmp = neon_load_reg(s, rd, 0); } else { tmp = tcg_temp_new_i32(tcg_ctx); tcg_gen_movi_i32(tcg_ctx, tmp, 0); } - tmp2 = neon_load_reg(tcg_ctx, rm, 0); - ptr1 = vfp_reg_ptr(tcg_ctx, true, rn); + tmp2 = neon_load_reg(s, rm, 0); + ptr1 = vfp_reg_ptr(s, true, rn); tmp5 = tcg_const_i32(tcg_ctx, n); gen_helper_neon_tbl(tcg_ctx, tmp2, tmp2, tmp, ptr1, tmp5); tcg_temp_free_i32(tcg_ctx, tmp); if (insn & (1 << 6)) { - tmp = neon_load_reg(tcg_ctx, rd, 1); + tmp = neon_load_reg(s, rd, 1); } else { tmp = tcg_temp_new_i32(tcg_ctx); tcg_gen_movi_i32(tcg_ctx, tmp, 0); } - tmp3 = neon_load_reg(tcg_ctx, rm, 1); + tmp3 = neon_load_reg(s, rm, 1); gen_helper_neon_tbl(tcg_ctx, tmp3, tmp3, tmp, ptr1, tmp5); tcg_temp_free_i32(tcg_ctx, tmp5); tcg_temp_free_ptr(tcg_ctx, ptr1); - neon_store_reg(tcg_ctx, rd, 0, tmp2); - neon_store_reg(tcg_ctx, rd, 1, tmp3); + neon_store_reg(s, rd, 0, tmp2); + neon_store_reg(s, rd, 1, tmp3); tcg_temp_free_i32(tcg_ctx, tmp); } else if ((insn & 0x380) == 0) { /* VDUP */ @@ -7879,9 +7896,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) return 1; } if (insn & (1 << 19)) { - tmp = neon_load_reg(tcg_ctx, rm, 1); + tmp = neon_load_reg(s, rm, 1); } else { - tmp = neon_load_reg(tcg_ctx, rm, 0); + tmp = neon_load_reg(s, rm, 0); } if (insn & (1 << 16)) { gen_neon_dup_u8(s, tmp, ((insn >> 17) & 3) * 8); @@ -7894,7 +7911,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) for (pass = 0; pass < (q ? 4 : 2); pass++) { tmp2 = tcg_temp_new_i32(tcg_ctx); tcg_gen_mov_i32(tcg_ctx, tmp2, tmp); - neon_store_reg(tcg_ctx, rd, pass, tmp2); + neon_store_reg(s, rd, pass, tmp2); } tcg_temp_free_i32(tcg_ctx, tmp); } else { @@ -8286,7 +8303,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tcg_ctx, tmp); } else { TCGv_i32 tmp = load_reg(s, rt); - store_cpu_offset(tcg_ctx, tmp, ri->fieldoffset); + store_cpu_offset(s, tmp, ri->fieldoffset); } } } @@ -8660,10 +8677,8 @@ static void arm_gen_condlabel(DisasContext *s) /* Skip this instruction if the ARM condition is false */ static void arm_skip_unless(DisasContext *s, uint32_t cond) { - TCGContext *tcg_ctx = s->uc->tcg_ctx; - arm_gen_condlabel(s); - arm_gen_test_cc(tcg_ctx, cond ^ 1, s->condlabel); + arm_gen_test_cc(s, cond ^ 1, s->condlabel); } static void disas_arm_insn(DisasContext *s, unsigned int insn) @@ -12738,7 +12753,7 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) if (dc->condexec_mask || dc->condexec_cond) { TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx); tcg_gen_movi_i32(tcg_ctx, tmp, 0); - store_cpu_field(tcg_ctx, tmp, condexec_bits); + store_cpu_field(dc, tmp, condexec_bits); } tcg_clear_temp_count(); diff --git a/qemu/target/arm/translate.h b/qemu/target/arm/translate.h index 076fd40c..d857d315 100644 --- a/qemu/target/arm/translate.h +++ b/qemu/target/arm/translate.h @@ -171,14 +171,15 @@ static inline void gen_a64_set_pc_im(DisasContext *s, uint64_t val) } #endif -void arm_test_cc(TCGContext *tcg_ctx, DisasCompare *cmp, int cc); -void arm_free_cc(TCGContext *tcg_ctx, DisasCompare *cmp); -void arm_jump_cc(TCGContext *tcg_ctx, DisasCompare *cmp, TCGLabel *label); -void arm_gen_test_cc(TCGContext *tcg_ctx, int cc, TCGLabel *label); +void arm_test_cc(DisasContext *s, DisasCompare *cmp, int cc); +void arm_free_cc(DisasContext *s, DisasCompare *cmp); +void arm_jump_cc(DisasContext *s, DisasCompare *cmp, TCGLabel *label); +void arm_gen_test_cc(DisasContext *s, int cc, TCGLabel *label); /* Return state of Alternate Half-precision flag, caller frees result */ -static inline TCGv_i32 get_ahp_flag(TCGContext *tcg_ctx) +static inline TCGv_i32 get_ahp_flag(DisasContext *s) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 ret = tcg_temp_new_i32(tcg_ctx); tcg_gen_ld_i32(tcg_ctx, ret, tcg_ctx->cpu_env,