From 49b9f4f8da637cb1aebe3184ec8a5e46a1272e9f Mon Sep 17 00:00:00 2001 From: Chris Eagle Date: Thu, 4 Feb 2016 19:09:41 -0800 Subject: [PATCH] uc_x86_mmr type available in qemu/target-i386/unicorn.c --- include/unicorn/x86.h | 10 ++-- qemu/target-i386/cpu.h | 2 +- qemu/target-i386/unicorn.c | 97 ++++++++++++++++++----------------- tests/unit/test_gdt_idt_x86.c | 8 +-- 4 files changed, 59 insertions(+), 58 deletions(-) diff --git a/include/unicorn/x86.h b/include/unicorn/x86.h index ab5a0481..37667cfc 100644 --- a/include/unicorn/x86.h +++ b/include/unicorn/x86.h @@ -10,12 +10,12 @@ extern "C" { //Memory-Management Register fields (idtr, gdtr, ldtr, tr) //borrow from SegmentCache in qemu/target-i386/cpu.h -typedef struct x86_mmr { - uint32_t selector; - uint64_t base; /* handle 32 or 64 bit CPUs */ +typedef struct uc_x86_mmr { + uint16_t selector; /* not used by gdtr and idtr */ + uint64_t base; /* handle 32 or 64 bit CPUs */ uint32_t limit; - uint32_t flags; -} x86_mmr; + uint32_t flags; /* not used by gdtr and idtr */ +} uc_x86_mmr; // Callback function for tracing SYSCALL/SYSENTER (for uc_hook_intr()) // @user_data: user data passed to tracing APIs. diff --git a/qemu/target-i386/cpu.h b/qemu/target-i386/cpu.h index 68f802f9..4628a8df 100644 --- a/qemu/target-i386/cpu.h +++ b/qemu/target-i386/cpu.h @@ -699,7 +699,7 @@ typedef enum { typedef struct SegmentCache { uint32_t selector; - uint64_t base; /* handle 32 or 64 bit CPUs */ + target_ulong base; uint32_t limit; uint32_t flags; } SegmentCache; diff --git a/qemu/target-i386/unicorn.c b/qemu/target-i386/unicorn.c index 89ccdb6d..19b3dfcf 100644 --- a/qemu/target-i386/unicorn.c +++ b/qemu/target-i386/unicorn.c @@ -9,6 +9,7 @@ #include "tcg.h" #include "unicorn_common.h" +#include /* needed for uc_x86_mmr */ #define READ_QWORD(x) ((uint64)x) #define READ_DWORD(x) (x & 0xffffffff) @@ -278,24 +279,24 @@ int x86_reg_read(struct uc_struct *uc, unsigned int regid, void *value) *(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_GS].base; break; case UC_X86_REG_IDTR: - ((SegmentCache *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.idt.limit; - ((SegmentCache *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.idt.base; + ((uc_x86_mmr *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.idt.limit; + ((uc_x86_mmr *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.idt.base; break; case UC_X86_REG_GDTR: - ((SegmentCache *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.gdt.limit; - ((SegmentCache *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.gdt.base; + ((uc_x86_mmr *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.gdt.limit; + ((uc_x86_mmr *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.gdt.base; break; case UC_X86_REG_LDTR: - ((SegmentCache *)value)->limit = X86_CPU(uc, mycpu)->env.ldt.limit; - ((SegmentCache *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.ldt.base; - ((SegmentCache *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.ldt.selector; - ((SegmentCache *)value)->flags = X86_CPU(uc, mycpu)->env.ldt.flags; + ((uc_x86_mmr *)value)->limit = X86_CPU(uc, mycpu)->env.ldt.limit; + ((uc_x86_mmr *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.ldt.base; + ((uc_x86_mmr *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.ldt.selector; + ((uc_x86_mmr *)value)->flags = X86_CPU(uc, mycpu)->env.ldt.flags; break; case UC_X86_REG_TR: - ((SegmentCache *)value)->limit = X86_CPU(uc, mycpu)->env.tr.limit; - ((SegmentCache *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.tr.base; - ((SegmentCache *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.tr.selector; - ((SegmentCache *)value)->flags = X86_CPU(uc, mycpu)->env.tr.flags; + ((uc_x86_mmr *)value)->limit = X86_CPU(uc, mycpu)->env.tr.limit; + ((uc_x86_mmr *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.tr.base; + ((uc_x86_mmr *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.tr.selector; + ((uc_x86_mmr *)value)->flags = X86_CPU(uc, mycpu)->env.tr.flags; break; } break; @@ -546,24 +547,24 @@ int x86_reg_read(struct uc_struct *uc, unsigned int regid, void *value) *(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15]); break; case UC_X86_REG_IDTR: - ((SegmentCache *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.idt.limit; - ((SegmentCache *)value)->base = X86_CPU(uc, mycpu)->env.idt.base; + ((uc_x86_mmr *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.idt.limit; + ((uc_x86_mmr *)value)->base = X86_CPU(uc, mycpu)->env.idt.base; break; case UC_X86_REG_GDTR: - ((SegmentCache *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.gdt.limit; - ((SegmentCache *)value)->base = X86_CPU(uc, mycpu)->env.gdt.base; + ((uc_x86_mmr *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.gdt.limit; + ((uc_x86_mmr *)value)->base = X86_CPU(uc, mycpu)->env.gdt.base; break; case UC_X86_REG_LDTR: - ((SegmentCache *)value)->limit = X86_CPU(uc, mycpu)->env.ldt.limit; - ((SegmentCache *)value)->base = X86_CPU(uc, mycpu)->env.ldt.base; - ((SegmentCache *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.ldt.selector; - ((SegmentCache *)value)->flags = X86_CPU(uc, mycpu)->env.ldt.flags; + ((uc_x86_mmr *)value)->limit = X86_CPU(uc, mycpu)->env.ldt.limit; + ((uc_x86_mmr *)value)->base = X86_CPU(uc, mycpu)->env.ldt.base; + ((uc_x86_mmr *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.ldt.selector; + ((uc_x86_mmr *)value)->flags = X86_CPU(uc, mycpu)->env.ldt.flags; break; case UC_X86_REG_TR: - ((SegmentCache *)value)->limit = X86_CPU(uc, mycpu)->env.tr.limit; - ((SegmentCache *)value)->base = X86_CPU(uc, mycpu)->env.tr.base; - ((SegmentCache *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.tr.selector; - ((SegmentCache *)value)->flags = X86_CPU(uc, mycpu)->env.tr.flags; + ((uc_x86_mmr *)value)->limit = X86_CPU(uc, mycpu)->env.tr.limit; + ((uc_x86_mmr *)value)->base = X86_CPU(uc, mycpu)->env.tr.base; + ((uc_x86_mmr *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.tr.selector; + ((uc_x86_mmr *)value)->flags = X86_CPU(uc, mycpu)->env.tr.flags; break; } break; @@ -725,24 +726,24 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(uint32_t *)value; break; case UC_X86_REG_IDTR: - X86_CPU(uc, mycpu)->env.idt.limit = (uint16_t)((SegmentCache *)value)->limit; - X86_CPU(uc, mycpu)->env.idt.base = (uint32_t)((SegmentCache *)value)->base; + X86_CPU(uc, mycpu)->env.idt.limit = (uint16_t)((uc_x86_mmr *)value)->limit; + X86_CPU(uc, mycpu)->env.idt.base = (uint32_t)((uc_x86_mmr *)value)->base; break; case UC_X86_REG_GDTR: - X86_CPU(uc, mycpu)->env.gdt.limit = (uint16_t)((SegmentCache *)value)->limit; - X86_CPU(uc, mycpu)->env.gdt.base = (uint32_t)((SegmentCache *)value)->base; + X86_CPU(uc, mycpu)->env.gdt.limit = (uint16_t)((uc_x86_mmr *)value)->limit; + X86_CPU(uc, mycpu)->env.gdt.base = (uint32_t)((uc_x86_mmr *)value)->base; break; case UC_X86_REG_LDTR: - X86_CPU(uc, mycpu)->env.ldt.limit = ((SegmentCache *)value)->limit; - X86_CPU(uc, mycpu)->env.ldt.base = (uint32_t)((SegmentCache *)value)->base; - X86_CPU(uc, mycpu)->env.ldt.selector = (uint16_t)((SegmentCache *)value)->selector; - X86_CPU(uc, mycpu)->env.ldt.flags = ((SegmentCache *)value)->flags; + X86_CPU(uc, mycpu)->env.ldt.limit = (uint16_t)((uc_x86_mmr *)value)->limit; + X86_CPU(uc, mycpu)->env.ldt.base = (uint32_t)((uc_x86_mmr *)value)->base; + X86_CPU(uc, mycpu)->env.ldt.selector = (uint16_t)((uc_x86_mmr *)value)->selector; + X86_CPU(uc, mycpu)->env.ldt.flags = ((uc_x86_mmr *)value)->flags; break; case UC_X86_REG_TR: - X86_CPU(uc, mycpu)->env.tr.limit = ((SegmentCache *)value)->limit; - X86_CPU(uc, mycpu)->env.tr.base = (uint32_t)((SegmentCache *)value)->base; - X86_CPU(uc, mycpu)->env.tr.selector = (uint16_t)((SegmentCache *)value)->selector; - X86_CPU(uc, mycpu)->env.tr.flags = ((SegmentCache *)value)->flags; + X86_CPU(uc, mycpu)->env.tr.limit = (uint16_t)((uc_x86_mmr *)value)->limit; + X86_CPU(uc, mycpu)->env.tr.base = (uint32_t)((uc_x86_mmr *)value)->base; + X86_CPU(uc, mycpu)->env.tr.selector = (uint16_t)((uc_x86_mmr *)value)->selector; + X86_CPU(uc, mycpu)->env.tr.flags = ((uc_x86_mmr *)value)->flags; break; } break; @@ -1003,24 +1004,24 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15], *(uint8_t *)value); break; case UC_X86_REG_IDTR: - X86_CPU(uc, mycpu)->env.idt.limit = (uint16_t)((SegmentCache *)value)->limit; - X86_CPU(uc, mycpu)->env.idt.base = ((SegmentCache *)value)->base; + X86_CPU(uc, mycpu)->env.idt.limit = (uint16_t)((uc_x86_mmr *)value)->limit; + X86_CPU(uc, mycpu)->env.idt.base = ((uc_x86_mmr *)value)->base; break; case UC_X86_REG_GDTR: - X86_CPU(uc, mycpu)->env.gdt.limit = (uint16_t)((SegmentCache *)value)->limit; - X86_CPU(uc, mycpu)->env.gdt.base = ((SegmentCache *)value)->base; + X86_CPU(uc, mycpu)->env.gdt.limit = (uint16_t)((uc_x86_mmr *)value)->limit; + X86_CPU(uc, mycpu)->env.gdt.base = ((uc_x86_mmr *)value)->base; break; case UC_X86_REG_LDTR: - X86_CPU(uc, mycpu)->env.ldt.limit = ((SegmentCache *)value)->limit; - X86_CPU(uc, mycpu)->env.ldt.base = ((SegmentCache *)value)->base; - X86_CPU(uc, mycpu)->env.ldt.selector = (uint16_t)((SegmentCache *)value)->selector; - X86_CPU(uc, mycpu)->env.ldt.flags = ((SegmentCache *)value)->flags; + X86_CPU(uc, mycpu)->env.ldt.limit = ((uc_x86_mmr *)value)->limit; + X86_CPU(uc, mycpu)->env.ldt.base = ((uc_x86_mmr *)value)->base; + X86_CPU(uc, mycpu)->env.ldt.selector = (uint16_t)((uc_x86_mmr *)value)->selector; + X86_CPU(uc, mycpu)->env.ldt.flags = ((uc_x86_mmr *)value)->flags; break; case UC_X86_REG_TR: - X86_CPU(uc, mycpu)->env.tr.limit = ((SegmentCache *)value)->limit; - X86_CPU(uc, mycpu)->env.tr.base = ((SegmentCache *)value)->base; - X86_CPU(uc, mycpu)->env.tr.selector = (uint16_t)((SegmentCache *)value)->selector; - X86_CPU(uc, mycpu)->env.tr.flags = ((SegmentCache *)value)->flags; + X86_CPU(uc, mycpu)->env.tr.limit = ((uc_x86_mmr *)value)->limit; + X86_CPU(uc, mycpu)->env.tr.base = ((uc_x86_mmr *)value)->base; + X86_CPU(uc, mycpu)->env.tr.selector = (uint16_t)((uc_x86_mmr *)value)->selector; + X86_CPU(uc, mycpu)->env.tr.flags = ((uc_x86_mmr *)value)->flags; break; } break; diff --git a/tests/unit/test_gdt_idt_x86.c b/tests/unit/test_gdt_idt_x86.c index 0ee0c9bc..5344d7a5 100644 --- a/tests/unit/test_gdt_idt_x86.c +++ b/tests/unit/test_gdt_idt_x86.c @@ -47,10 +47,10 @@ static void test_idt_gdt_i386(/*void **state*/) uc_engine *uc; uc_err err; uint8_t buf[6]; - x86_mmr idt; - x86_mmr gdt; - x86_mmr ldt; - x86_mmr tr; + uc_x86_mmr idt; + uc_x86_mmr gdt; + uc_x86_mmr ldt; + uc_x86_mmr tr; const uint8_t code[] = "\x0f\x01\x0c\x24\x0f\x01\x44\x24\x06"; // sidt [esp]; sgdt [esp+6] const uint64_t address = 0x1000000;