From 4a3d8417ca50a0ffc18dd8b7876193eefb67fe9a Mon Sep 17 00:00:00 2001
From: Palmer Dabbelt <palmer@sifive.com>
Date: Thu, 8 Aug 2019 17:10:32 -0400
Subject: [PATCH] RISC-V: Add support for the Zicsr extension

The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.

Backports commit 591bddea8d874e1500921de0353818e5586618f5 from qemu
---
 qemu/target/riscv/cpu.h | 1 +
 qemu/target/riscv/csr.c | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h
index c4686407..dc72b3e4 100644
--- a/qemu/target/riscv/cpu.h
+++ b/qemu/target/riscv/cpu.h
@@ -224,6 +224,7 @@ typedef struct RISCVCPU {
 
     struct {
         bool ext_ifencei;
+        bool ext_icsr;
     } cfg;
 } RISCVCPU;
 
diff --git a/qemu/target/riscv/csr.c b/qemu/target/riscv/csr.c
index cb1b1cec..a0dd575c 100644
--- a/qemu/target/riscv/csr.c
+++ b/qemu/target/riscv/csr.c
@@ -797,6 +797,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 {
     int ret;
     target_ulong old_value;
+    RISCVCPU *cpu = env_archcpu(env);
 
     /* check privileges and return -1 if check fails */
 #if !defined(CONFIG_USER_ONLY)
@@ -807,6 +808,11 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
     }
 #endif
 
+    /* ensure the CSR extension is enabled. */
+    if (!cpu->cfg.ext_icsr) {
+        return -1;
+    }
+
     /* check predicate */
     if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
         return -1;