From 4a6a41d2c577da7ef3bc4bb1284ee094c0ac5053 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 8 Mar 2018 12:54:44 -0500 Subject: [PATCH] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 The fprintf is only there for debugging as the skeleton is added to, it will be removed once the skeleton is complete. Backports commit 372087348d561e7f4051d7b32609bda417092ddf from qemu --- qemu/aarch64.h | 4 ++++ qemu/aarch64eb.h | 4 ++++ qemu/header_gen.py | 4 ++++ qemu/target/arm/helper-a64.c | 4 ++++ qemu/target/arm/helper-a64.h | 5 ++++- qemu/target/arm/translate-a64.c | 28 ++++++++++++++++++++++++++++ 6 files changed, 48 insertions(+), 1 deletion(-) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 822d69fb..96b8c525 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -3720,10 +3720,14 @@ #define arm_set_cpu_off arm_set_cpu_off_aarch64 #define arm_set_cpu_on arm_set_cpu_on_aarch64 #define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64 +#define helper_advsimd_addh helper_advsimd_addh_aarch64 +#define helper_advsimd_divh helper_advsimd_divh_aarch64 #define helper_advsimd_maxh helper_advsimd_maxh_aarch64 #define helper_advsimd_maxnumh helper_advsimd_maxnumh_aarch64 #define helper_advsimd_minh helper_advsimd_minh_aarch64 #define helper_advsimd_minnumh helper_advsimd_minnumh_aarch64 +#define helper_advsimd_mulh helper_advsimd_mulh_aarch64 +#define helper_advsimd_subh helper_advsimd_subh_aarch64 #define helper_crc32_64 helper_crc32_64_aarch64 #define helper_crc32c_64 helper_crc32c_64_aarch64 #define helper_fcvtx_f64_to_f32 helper_fcvtx_f64_to_f32_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 39194f31..5fb8ca97 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -3720,10 +3720,14 @@ #define arm_set_cpu_off arm_set_cpu_off_aarch64eb #define arm_set_cpu_on arm_set_cpu_on_aarch64eb #define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64eb +#define helper_advsimd_addh helper_advsimd_addh_aarch64eb +#define helper_advsimd_divh helper_advsimd_divh_aarch64eb #define helper_advsimd_maxh helper_advsimd_maxh_aarch64eb #define helper_advsimd_maxnumh helper_advsimd_maxnumh_aarch64eb #define helper_advsimd_minh helper_advsimd_minh_aarch64eb #define helper_advsimd_minnumh helper_advsimd_minnumh_aarch64eb +#define helper_advsimd_mulh helper_advsimd_mulh_aarch64eb +#define helper_advsimd_subh helper_advsimd_subh_aarch64eb #define helper_crc32_64 helper_crc32_64_aarch64eb #define helper_crc32c_64 helper_crc32c_64_aarch64eb #define helper_fcvtx_f64_to_f32 helper_fcvtx_f64_to_f32_aarch64eb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index dbc7dd91..8e70cd74 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3740,10 +3740,14 @@ aarch64_symbols = ( 'arm_set_cpu_off', 'arm_set_cpu_on', 'gen_a64_set_pc_im', + 'helper_advsimd_addh', + 'helper_advsimd_divh', 'helper_advsimd_maxh', 'helper_advsimd_maxnumh', 'helper_advsimd_minh', 'helper_advsimd_minnumh', + 'helper_advsimd_mulh', + 'helper_advsimd_subh', 'helper_crc32_64', 'helper_crc32c_64', 'helper_fcvtx_f64_to_f32', diff --git a/qemu/target/arm/helper-a64.c b/qemu/target/arm/helper-a64.c index 6c2ceec5..21bb994a 100644 --- a/qemu/target/arm/helper-a64.c +++ b/qemu/target/arm/helper-a64.c @@ -632,6 +632,10 @@ float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \ return float16_ ## name(a, b, fpst); \ } +ADVSIMD_HALFOP(add) +ADVSIMD_HALFOP(sub) +ADVSIMD_HALFOP(mul) +ADVSIMD_HALFOP(div) ADVSIMD_HALFOP(min) ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) diff --git a/qemu/target/arm/helper-a64.h b/qemu/target/arm/helper-a64.h index 0a332694..289ea481 100644 --- a/qemu/target/arm/helper-a64.h +++ b/qemu/target/arm/helper-a64.h @@ -48,4 +48,7 @@ DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) - +DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index f4abc6bb..7eeac3bc 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -10435,6 +10435,34 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); switch (fpopcode) { + case 0x0: /* FMAXNM */ + gen_helper_advsimd_maxnumh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x2: /* FADD */ + gen_helper_advsimd_addh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x6: /* FMAX */ + gen_helper_advsimd_maxh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x8: /* FMINNM */ + gen_helper_advsimd_minnumh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xa: /* FSUB */ + gen_helper_advsimd_subh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xe: /* FMIN */ + gen_helper_advsimd_minh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x13: /* FMUL */ + gen_helper_advsimd_mulh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x17: /* FDIV */ + gen_helper_advsimd_divh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1a: /* FABD */ + gen_helper_advsimd_subh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + tcg_gen_andi_i32(tcg_ctx, tcg_res, tcg_res, 0x7fff); + break; default: fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", __func__, insn, fpopcode, s->pc);