diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 48d11260..9c38e29f 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -7201,6 +7201,38 @@ riscv_symbols = ( 'helper_vfncvt_f_x_v_w', 'helper_vfncvt_f_f_v_h', 'helper_vfncvt_f_f_v_w', + 'helper_vredsum_vs_b', + 'helper_vredsum_vs_h', + 'helper_vredsum_vs_w', + 'helper_vredsum_vs_d', + 'helper_vredmaxu_vs_b', + 'helper_vredmaxu_vs_h', + 'helper_vredmaxu_vs_w', + 'helper_vredmaxu_vs_d', + 'helper_vredmax_vs_b', + 'helper_vredmax_vs_h', + 'helper_vredmax_vs_w', + 'helper_vredmax_vs_d', + 'helper_vredminu_vs_b', + 'helper_vredminu_vs_h', + 'helper_vredminu_vs_w', + 'helper_vredminu_vs_d', + 'helper_vredmin_vs_b', + 'helper_vredmin_vs_h', + 'helper_vredmin_vs_w', + 'helper_vredmin_vs_d', + 'helper_vredand_vs_b', + 'helper_vredand_vs_h', + 'helper_vredand_vs_w', + 'helper_vredand_vs_d', + 'helper_vredor_vs_b', + 'helper_vredor_vs_h', + 'helper_vredor_vs_w', + 'helper_vredor_vs_d', + 'helper_vredxor_vs_b', + 'helper_vredxor_vs_h', + 'helper_vredxor_vs_w', + 'helper_vredxor_vs_d', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 9ad68ee8..3d978832 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -4637,6 +4637,38 @@ #define helper_vfncvt_f_x_v_w helper_vfncvt_f_x_v_w_riscv32 #define helper_vfncvt_f_f_v_h helper_vfncvt_f_f_v_h_riscv32 #define helper_vfncvt_f_f_v_w helper_vfncvt_f_f_v_w_riscv32 +#define helper_vredsum_vs_b helper_vredsum_vs_b_riscv32 +#define helper_vredsum_vs_h helper_vredsum_vs_h_riscv32 +#define helper_vredsum_vs_w helper_vredsum_vs_w_riscv32 +#define helper_vredsum_vs_d helper_vredsum_vs_d_riscv32 +#define helper_vredmaxu_vs_b helper_vredmaxu_vs_b_riscv32 +#define helper_vredmaxu_vs_h helper_vredmaxu_vs_h_riscv32 +#define helper_vredmaxu_vs_w helper_vredmaxu_vs_w_riscv32 +#define helper_vredmaxu_vs_d helper_vredmaxu_vs_d_riscv32 +#define helper_vredmax_vs_b helper_vredmax_vs_b_riscv32 +#define helper_vredmax_vs_h helper_vredmax_vs_h_riscv32 +#define helper_vredmax_vs_w helper_vredmax_vs_w_riscv32 +#define helper_vredmax_vs_d helper_vredmax_vs_d_riscv32 +#define helper_vredminu_vs_b helper_vredminu_vs_b_riscv32 +#define helper_vredminu_vs_h helper_vredminu_vs_h_riscv32 +#define helper_vredminu_vs_w helper_vredminu_vs_w_riscv32 +#define helper_vredminu_vs_d helper_vredminu_vs_d_riscv32 +#define helper_vredmin_vs_b helper_vredmin_vs_b_riscv32 +#define helper_vredmin_vs_h helper_vredmin_vs_h_riscv32 +#define helper_vredmin_vs_w helper_vredmin_vs_w_riscv32 +#define helper_vredmin_vs_d helper_vredmin_vs_d_riscv32 +#define helper_vredand_vs_b helper_vredand_vs_b_riscv32 +#define helper_vredand_vs_h helper_vredand_vs_h_riscv32 +#define helper_vredand_vs_w helper_vredand_vs_w_riscv32 +#define helper_vredand_vs_d helper_vredand_vs_d_riscv32 +#define helper_vredor_vs_b helper_vredor_vs_b_riscv32 +#define helper_vredor_vs_h helper_vredor_vs_h_riscv32 +#define helper_vredor_vs_w helper_vredor_vs_w_riscv32 +#define helper_vredor_vs_d helper_vredor_vs_d_riscv32 +#define helper_vredxor_vs_b helper_vredxor_vs_b_riscv32 +#define helper_vredxor_vs_h helper_vredxor_vs_h_riscv32 +#define helper_vredxor_vs_w helper_vredxor_vs_w_riscv32 +#define helper_vredxor_vs_d helper_vredxor_vs_d_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index a4ceb488..4ed0651d 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -4637,6 +4637,38 @@ #define helper_vfncvt_f_x_v_w helper_vfncvt_f_x_v_w_riscv64 #define helper_vfncvt_f_f_v_h helper_vfncvt_f_f_v_h_riscv64 #define helper_vfncvt_f_f_v_w helper_vfncvt_f_f_v_w_riscv64 +#define helper_vredsum_vs_b helper_vredsum_vs_b_riscv64 +#define helper_vredsum_vs_h helper_vredsum_vs_h_riscv64 +#define helper_vredsum_vs_w helper_vredsum_vs_w_riscv64 +#define helper_vredsum_vs_d helper_vredsum_vs_d_riscv64 +#define helper_vredmaxu_vs_b helper_vredmaxu_vs_b_riscv64 +#define helper_vredmaxu_vs_h helper_vredmaxu_vs_h_riscv64 +#define helper_vredmaxu_vs_w helper_vredmaxu_vs_w_riscv64 +#define helper_vredmaxu_vs_d helper_vredmaxu_vs_d_riscv64 +#define helper_vredmax_vs_b helper_vredmax_vs_b_riscv64 +#define helper_vredmax_vs_h helper_vredmax_vs_h_riscv64 +#define helper_vredmax_vs_w helper_vredmax_vs_w_riscv64 +#define helper_vredmax_vs_d helper_vredmax_vs_d_riscv64 +#define helper_vredminu_vs_b helper_vredminu_vs_b_riscv64 +#define helper_vredminu_vs_h helper_vredminu_vs_h_riscv64 +#define helper_vredminu_vs_w helper_vredminu_vs_w_riscv64 +#define helper_vredminu_vs_d helper_vredminu_vs_d_riscv64 +#define helper_vredmin_vs_b helper_vredmin_vs_b_riscv64 +#define helper_vredmin_vs_h helper_vredmin_vs_h_riscv64 +#define helper_vredmin_vs_w helper_vredmin_vs_w_riscv64 +#define helper_vredmin_vs_d helper_vredmin_vs_d_riscv64 +#define helper_vredand_vs_b helper_vredand_vs_b_riscv64 +#define helper_vredand_vs_h helper_vredand_vs_h_riscv64 +#define helper_vredand_vs_w helper_vredand_vs_w_riscv64 +#define helper_vredand_vs_d helper_vredand_vs_d_riscv64 +#define helper_vredor_vs_b helper_vredor_vs_b_riscv64 +#define helper_vredor_vs_h helper_vredor_vs_h_riscv64 +#define helper_vredor_vs_w helper_vredor_vs_w_riscv64 +#define helper_vredor_vs_d helper_vredor_vs_d_riscv64 +#define helper_vredxor_vs_b helper_vredxor_vs_b_riscv64 +#define helper_vredxor_vs_h helper_vredxor_vs_h_riscv64 +#define helper_vredxor_vs_w helper_vredxor_vs_w_riscv64 +#define helper_vredxor_vs_d helper_vredxor_vs_d_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index 99082e45..4d327b98 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -1042,3 +1042,36 @@ DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredmaxu_vs_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredmaxu_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredmaxu_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredmaxu_vs_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredmax_vs_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredminu_vs_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredminu_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredminu_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredminu_vs_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredmin_vs_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredand_vs_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredand_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredand_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredand_vs_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredor_vs_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredor_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredor_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredor_vs_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredxor_vs_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredxor_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredxor_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vredxor_vs_d, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index 55fbe166..878eeecb 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -531,6 +531,14 @@ vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm +vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm +vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm +vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm +vredxor_vs 000011 . ..... ..... 010 ..... 1010111 @r_vm +vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm +vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm +vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm +vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index 146eddca..c2d611d0 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -2361,3 +2361,21 @@ GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v) GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v) GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v) GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v) + +/* + *** Vector Reduction Operations + */ +/* Vector Single-Width Integer Reduction Instructions */ +static bool reduction_check(DisasContext *s, arg_rmrr *a) +{ + return vext_check_isa_ill(s) && vext_check_reg(s, a->rs2, false); +} + +GEN_OPIVV_TRANS(vredsum_vs, reduction_check) +GEN_OPIVV_TRANS(vredmaxu_vs, reduction_check) +GEN_OPIVV_TRANS(vredmax_vs, reduction_check) +GEN_OPIVV_TRANS(vredminu_vs, reduction_check) +GEN_OPIVV_TRANS(vredmin_vs, reduction_check) +GEN_OPIVV_TRANS(vredand_vs, reduction_check) +GEN_OPIVV_TRANS(vredor_vs, reduction_check) +GEN_OPIVV_TRANS(vredxor_vs, reduction_check) diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index 06aa5092..bcbd7522 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -4308,3 +4308,77 @@ RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16) RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32) GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2, clearh) GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl) + +/* + *** Vector Reduction Operations + */ +/* Vector Single-Width Integer Reduction Instructions */ +#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\ +void HELPER(NAME)(void *vd, void *v0, void *vs1, \ + void *vs2, CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t mlen = vext_mlen(desc); \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \ + TD s1 = *((TD *)vs1 + HD(0)); \ + \ + for (i = 0; i < vl; i++) { \ + TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + s1 = OP(s1, (TD)s2); \ + } \ + *((TD *)vd + HD(0)) = s1; \ + CLEAR_FN(vd, 1, sizeof(TD), tot); \ +} + +/* vd[0] = sum(vs1[0], vs2[*]) */ +GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD, clearb) +GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD, clearh) +GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD, clearl) +GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD, clearq) + +/* vd[0] = maxu(vs1[0], vs2[*]) */ +GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX, clearb) +GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX, clearh) +GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX, clearl) +GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX, clearq) + +/* vd[0] = max(vs1[0], vs2[*]) */ +GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX, clearb) +GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX, clearh) +GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX, clearl) +GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX, clearq) + +/* vd[0] = minu(vs1[0], vs2[*]) */ +GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN, clearb) +GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN, clearh) +GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN, clearl) +GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN, clearq) + +/* vd[0] = min(vs1[0], vs2[*]) */ +GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN, clearb) +GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN, clearh) +GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN, clearl) +GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN, clearq) + +/* vd[0] = and(vs1[0], vs2[*]) */ +GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND, clearb) +GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND, clearh) +GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND, clearl) +GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND, clearq) + +/* vd[0] = or(vs1[0], vs2[*]) */ +GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR, clearb) +GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR, clearh) +GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR, clearl) +GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR, clearq) + +/* vd[0] = xor(vs1[0], vs2[*]) */ +GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR, clearb) +GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR, clearh) +GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR, clearl) +GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR, clearq)