diff --git a/qemu/scripts/decodetree.py b/qemu/scripts/decodetree.py
index caa3fa75..0246ad14 100644
--- a/qemu/scripts/decodetree.py
+++ b/qemu/scripts/decodetree.py
@@ -466,8 +466,7 @@ class Pattern(General):
         output('typedef ', self.base.base.struct_name(),
                ' arg_', self.name, ';\n')
         output(translate_scope, 'bool ', translate_prefix, '_', self.name,
-               '(DisasContext *ctx, arg_', self.name,
-               ' *a, ', insntype, ' insn);\n')
+               '(DisasContext *ctx, arg_', self.name, ' *a);\n')
 
     def output_code(self, i, extracted, outerbits, outermask):
         global translate_prefix
@@ -479,7 +478,7 @@ class Pattern(General):
         for n, f in self.fields.items():
             output(ind, 'u.f_', arg, '.', n, ' = ', f.str_extract(), ';\n')
         output(ind, 'return ', translate_prefix, '_', self.name,
-               '(ctx, &u.f_', arg, ', insn);\n')
+               '(ctx, &u.f_', arg, ');\n')
 # end Pattern
 
 
diff --git a/qemu/target/arm/translate-sve.c b/qemu/target/arm/translate-sve.c
index c004ac3e..857b2889 100644
--- a/qemu/target/arm/translate-sve.c
+++ b/qemu/target/arm/translate-sve.c
@@ -279,12 +279,12 @@ const uint64_t pred_esz_masks[4] = {
  *** SVE Logical - Unpredicated Group
  */
 
-static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
 {
     return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
 }
 
-static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
 {
     if (a->rn == a->rm) { /* MOV */
         return do_mov_z(s, a->rd, a->rn);
@@ -293,12 +293,12 @@ static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
     }
 }
 
-static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
 {
     return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm);
 }
 
-static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
 {
     return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
 }
@@ -307,32 +307,32 @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
  *** SVE Integer Arithmetic - Unpredicated Group
  */
 
-static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a)
 {
     return do_vector3_z(s, tcg_gen_gvec_add, a->esz, a->rd, a->rn, a->rm);
 }
 
-static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a)
 {
     return do_vector3_z(s, tcg_gen_gvec_sub, a->esz, a->rd, a->rn, a->rm);
 }
 
-static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a)
 {
     return do_vector3_z(s, tcg_gen_gvec_ssadd, a->esz, a->rd, a->rn, a->rm);
 }
 
-static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
 {
     return do_vector3_z(s, tcg_gen_gvec_sssub, a->esz, a->rd, a->rn, a->rm);
 }
 
-static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a)
 {
     return do_vector3_z(s, tcg_gen_gvec_usadd, a->esz, a->rd, a->rn, a->rm);
 }
 
-static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
 {
     return do_vector3_z(s, tcg_gen_gvec_ussub, a->esz, a->rd, a->rn, a->rm);
 }
@@ -377,8 +377,7 @@ static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
 }
 
 #define DO_ZPZZ(NAME, name) \
-static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a,         \
-                                uint32_t insn)                            \
+static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a)         \
 {                                                                         \
     static gen_helper_gvec_4 * const fns[4] = {                           \
         gen_helper_sve_##name##_zpzz_b, gen_helper_sve_##name##_zpzz_h,   \
@@ -410,7 +409,7 @@ DO_ZPZZ(ASR, asr)
 DO_ZPZZ(LSR, lsr)
 DO_ZPZZ(LSL, lsl)
 
-static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
+static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
 {
     static gen_helper_gvec_4 * const fns[4] = {
         NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d
@@ -418,7 +417,7 @@ static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
     return do_zpzz_ool(s, a, fns[a->esz]);
 }
 
-static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
+static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
 {
     static gen_helper_gvec_4 * const fns[4] = {
         NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d
@@ -426,7 +425,7 @@ static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
     return do_zpzz_ool(s, a, fns[a->esz]);
 }
 
-static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
+static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
 {
     if (sve_access_check(s)) {
         do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz);
@@ -457,7 +456,7 @@ static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 *fn)
 }
 
 #define DO_ZPZ(NAME, name) \
-static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \
+static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a)           \
 {                                                                   \
     static gen_helper_gvec_3 * const fns[4] = {                     \
         gen_helper_sve_##name##_b, gen_helper_sve_##name##_h,       \
@@ -474,7 +473,7 @@ DO_ZPZ(NOT_zpz, not_zpz)
 DO_ZPZ(ABS, abs)
 DO_ZPZ(NEG, neg)
 
-static bool trans_FABS(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FABS(DisasContext *s, arg_rpr_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         NULL,
@@ -485,7 +484,7 @@ static bool trans_FABS(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
     return do_zpz_ool(s, a, fns[a->esz]);
 }
 
-static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         NULL,
@@ -496,7 +495,7 @@ static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
     return do_zpz_ool(s, a, fns[a->esz]);
 }
 
-static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         NULL,
@@ -507,7 +506,7 @@ static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
     return do_zpz_ool(s, a, fns[a->esz]);
 }
 
-static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         NULL,
@@ -518,7 +517,7 @@ static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
     return do_zpz_ool(s, a, fns[a->esz]);
 }
 
-static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         NULL, NULL,
@@ -528,7 +527,7 @@ static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
     return do_zpz_ool(s, a, fns[a->esz]);
 }
 
-static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         NULL, NULL,
@@ -538,12 +537,12 @@ static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
     return do_zpz_ool(s, a, fns[a->esz]);
 }
 
-static bool trans_SXTW(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_SXTW(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_sxtw_d : NULL);
 }
 
-static bool trans_UXTW(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_UXTW(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_uxtw_d : NULL);
 }
@@ -589,7 +588,7 @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
 }
 
 #define DO_VPZ(NAME, name) \
-static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \
+static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a)                \
 {                                                                        \
     static gen_helper_gvec_reduc * const fns[4] = {                      \
         gen_helper_sve_##name##_b, gen_helper_sve_##name##_h,            \
@@ -608,7 +607,7 @@ DO_VPZ(UMAXV, umaxv)
 DO_VPZ(SMINV, sminv)
 DO_VPZ(UMINV, uminv)
 
-static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a)
 {
     static gen_helper_gvec_reduc * const fns[4] = {
         gen_helper_sve_saddv_b, gen_helper_sve_saddv_h,
@@ -672,7 +671,7 @@ static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
     return true;
 }
 
-static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn)
+static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h,
@@ -688,7 +687,7 @@ static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn)
     return do_zpzi_ool(s, a, fns[a->esz]);
 }
 
-static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn)
+static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h,
@@ -706,7 +705,7 @@ static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn)
     }
 }
 
-static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn)
+static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h,
@@ -724,7 +723,7 @@ static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn)
     }
 }
 
-static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a, uint32_t insn)
+static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         gen_helper_sve_asrd_b, gen_helper_sve_asrd_h,
@@ -747,8 +746,7 @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a, uint32_t insn)
  */
 
 #define DO_ZPZW(NAME, name) \
-static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a,         \
-                                uint32_t insn)                            \
+static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a)         \
 {                                                                         \
     static gen_helper_gvec_4 * const fns[3] = {                           \
         gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h,   \
@@ -798,17 +796,17 @@ static bool do_shift_imm(DisasContext *s, arg_rri_esz *a, bool asr,
     return true;
 }
 
-static bool trans_ASR_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
+static bool trans_ASR_zzi(DisasContext *s, arg_rri_esz *a)
 {
     return do_shift_imm(s, a, true, tcg_gen_gvec_sari);
 }
 
-static bool trans_LSR_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
+static bool trans_LSR_zzi(DisasContext *s, arg_rri_esz *a)
 {
     return do_shift_imm(s, a, false, tcg_gen_gvec_shri);
 }
 
-static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
+static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a)
 {
     return do_shift_imm(s, a, false, tcg_gen_gvec_shli);
 }
@@ -830,8 +828,7 @@ static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
 }
 
 #define DO_ZZW(NAME, name) \
-static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a,           \
-                               uint32_t insn)                             \
+static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a)           \
 {                                                                         \
     static gen_helper_gvec_3 * const fns[4] = {                           \
         gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h,     \
@@ -846,7 +843,7 @@ DO_ZZW(LSL, lsl)
 
 #undef DO_ZZW
 
-static bool trans_DOT_zzz(DisasContext *s, arg_DOT_zzz *a, uint32_t insn)
+static bool trans_DOT_zzz(DisasContext *s, arg_DOT_zzz *a)
 {
     static gen_helper_gvec_3 * const fns[2][2] = {
         { gen_helper_gvec_sdot_b, gen_helper_gvec_sdot_h },
@@ -864,7 +861,7 @@ static bool trans_DOT_zzz(DisasContext *s, arg_DOT_zzz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_DOT_zzx(DisasContext *s, arg_DOT_zzx *a, uint32_t insn)
+static bool trans_DOT_zzx(DisasContext *s, arg_DOT_zzx *a)
 {
     static gen_helper_gvec_3 * const fns[2][2] = {
         { gen_helper_gvec_sdot_idx_b, gen_helper_gvec_sdot_idx_h },
@@ -903,7 +900,7 @@ static bool do_zpzzz_ool(DisasContext *s, arg_rprrr_esz *a,
 }
 
 #define DO_ZPZZZ(NAME, name) \
-static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a, uint32_t insn) \
+static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a)          \
 {                                                                    \
     static gen_helper_gvec_5 * const fns[4] = {                      \
         gen_helper_sve_##name##_b, gen_helper_sve_##name##_h,        \
@@ -953,7 +950,7 @@ static void do_index(DisasContext *s, int esz, int rd,
     tcg_temp_free_i32(tcg_ctx, desc);
 }
 
-static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a, uint32_t insn)
+static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -966,7 +963,7 @@ static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a, uint32_t insn)
     return true;
 }
 
-static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a, uint32_t insn)
+static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -978,7 +975,7 @@ static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a, uint32_t insn)
     return true;
 }
 
-static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a, uint32_t insn)
+static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -990,7 +987,7 @@ static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a, uint32_t insn)
     return true;
 }
 
-static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a, uint32_t insn)
+static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a)
 {
     if (sve_access_check(s)) {
         TCGv_i64 start = cpu_reg(s, a->rn);
@@ -1004,7 +1001,7 @@ static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a, uint32_t insn)
  *** SVE Stack Allocation Group
  */
 
-static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a, uint32_t insn)
+static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a)
 {
     TCGContext *tcg_ctx = s->uc->tcg_ctx;
     TCGv_i64 rd = cpu_reg_sp(s, a->rd);
@@ -1013,7 +1010,7 @@ static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a, uint32_t insn)
     return true;
 }
 
-static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a, uint32_t insn)
+static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a)
 {
     TCGContext *tcg_ctx = s->uc->tcg_ctx;
     TCGv_i64 rd = cpu_reg_sp(s, a->rd);
@@ -1022,7 +1019,7 @@ static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a, uint32_t insn)
     return true;
 }
 
-static bool trans_RDVL(DisasContext *s, arg_RDVL *a, uint32_t insn)
+static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
 {
     TCGContext *tcg_ctx = s->uc->tcg_ctx;
     TCGv_i64 reg = cpu_reg(s, a->rd);
@@ -1047,22 +1044,22 @@ static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
     return true;
 }
 
-static bool trans_ADR_p32(DisasContext *s, arg_rrri *a, uint32_t insn)
+static bool trans_ADR_p32(DisasContext *s, arg_rrri *a)
 {
     return do_adr(s, a, gen_helper_sve_adr_p32);
 }
 
-static bool trans_ADR_p64(DisasContext *s, arg_rrri *a, uint32_t insn)
+static bool trans_ADR_p64(DisasContext *s, arg_rrri *a)
 {
     return do_adr(s, a, gen_helper_sve_adr_p64);
 }
 
-static bool trans_ADR_s32(DisasContext *s, arg_rrri *a, uint32_t insn)
+static bool trans_ADR_s32(DisasContext *s, arg_rrri *a)
 {
     return do_adr(s, a, gen_helper_sve_adr_s32);
 }
 
-static bool trans_ADR_u32(DisasContext *s, arg_rrri *a, uint32_t insn)
+static bool trans_ADR_u32(DisasContext *s, arg_rrri *a)
 {
     return do_adr(s, a, gen_helper_sve_adr_u32);
 }
@@ -1071,7 +1068,7 @@ static bool trans_ADR_u32(DisasContext *s, arg_rrri *a, uint32_t insn)
  *** SVE Integer Misc - Unpredicated Group
  */
 
-static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a, uint32_t insn)
+static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a)
 {
     static gen_helper_gvec_2 * const fns[4] = {
         NULL,
@@ -1092,7 +1089,7 @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         NULL,
@@ -1183,7 +1180,7 @@ static void gen_and_pg_vec(TCGContext *s, unsigned vece, TCGv_vec pd, TCGv_vec p
     tcg_gen_and_vec(s, vece, pd, pd, pg);
 }
 
-static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn)
+static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a)
 {
     static const GVecGen4 op = {
         gen_and_pg_i64,
@@ -1223,7 +1220,7 @@ static void gen_bic_pg_vec(TCGContext *s, unsigned vece, TCGv_vec pd, TCGv_vec p
     tcg_gen_and_vec(s, vece, pd, pd, pg);
 }
 
-static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn)
+static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a)
 {
     static const GVecGen4 op = {
         gen_bic_pg_i64,
@@ -1257,7 +1254,7 @@ static void gen_eor_pg_vec(TCGContext *s, unsigned vece, TCGv_vec pd, TCGv_vec p
     tcg_gen_and_vec(s, vece, pd, pd, pg);
 }
 
-static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn)
+static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a)
 {
     static const GVecGen4 op = {
         gen_eor_pg_i64,
@@ -1291,7 +1288,7 @@ static void gen_sel_pg_vec(TCGContext *s, unsigned vece, TCGv_vec pd, TCGv_vec p
     tcg_gen_or_vec(s, vece, pd, pn, pm);
 }
 
-static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn)
+static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a)
 {
     static const GVecGen4 op = {
         gen_sel_pg_i64,
@@ -1323,7 +1320,7 @@ static void gen_orr_pg_vec(TCGContext *s, unsigned vece, TCGv_vec pd, TCGv_vec p
     tcg_gen_and_vec(s, vece, pd, pd, pg);
 }
 
-static bool trans_ORR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn)
+static bool trans_ORR_pppp(DisasContext *s, arg_rprr_s *a)
 {
     static const GVecGen4 op = {
         gen_orr_pg_i64,
@@ -1357,7 +1354,7 @@ static void gen_orn_pg_vec(TCGContext *s, unsigned vece, TCGv_vec pd, TCGv_vec p
     tcg_gen_and_vec(s, vece, pd, pd, pg);
 }
 
-static bool trans_ORN_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn)
+static bool trans_ORN_pppp(DisasContext *s, arg_rprr_s *a)
 {
     static const GVecGen4 op = {
         gen_orn_pg_i64,
@@ -1389,7 +1386,7 @@ static void gen_nor_pg_vec(TCGContext *s, unsigned vece, TCGv_vec pd, TCGv_vec p
     tcg_gen_andc_vec(s, vece, pd, pg, pd);
 }
 
-static bool trans_NOR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn)
+static bool trans_NOR_pppp(DisasContext *s, arg_rprr_s *a)
 {
     static const GVecGen4 op = {
         gen_nor_pg_i64,
@@ -1421,7 +1418,7 @@ static void gen_nand_pg_vec(TCGContext *s, unsigned vece, TCGv_vec pd, TCGv_vec
     tcg_gen_andc_vec(s, vece, pd, pg, pd);
 }
 
-static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn)
+static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a)
 {
     static const GVecGen4 op = {
         gen_nand_pg_i64,
@@ -1444,7 +1441,7 @@ static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn)
  *** SVE Predicate Misc Group
  */
 
-static bool trans_PTEST(DisasContext *s, arg_PTEST *a, uint32_t insn)
+static bool trans_PTEST(DisasContext *s, arg_PTEST *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -1588,24 +1585,24 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
     return true;
 }
 
-static bool trans_PTRUE(DisasContext *s, arg_PTRUE *a, uint32_t insn)
+static bool trans_PTRUE(DisasContext *s, arg_PTRUE *a)
 {
     return do_predset(s, a->esz, a->rd, a->pat, a->s);
 }
 
-static bool trans_SETFFR(DisasContext *s, arg_SETFFR *a, uint32_t insn)
+static bool trans_SETFFR(DisasContext *s, arg_SETFFR *a)
 {
     /* Note pat == 31 is #all, to set all elements.  */
     return do_predset(s, 0, FFR_PRED_NUM, 31, false);
 }
 
-static bool trans_PFALSE(DisasContext *s, arg_PFALSE *a, uint32_t insn)
+static bool trans_PFALSE(DisasContext *s, arg_PFALSE *a)
 {
     /* Note pat == 32 is #unimp, to set no elements.  */
     return do_predset(s, 0, a->rd, 32, false);
 }
 
-static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a, uint32_t insn)
+static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a)
 {
     /* The path through do_pppp_flags is complicated enough to want to avoid
      * duplication.  Frob the arguments into the form of a predicated AND.
@@ -1614,15 +1611,15 @@ static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a, uint32_t insn)
         .rd = a->rd, .pg = a->pg, .s = a->s,
         .rn = FFR_PRED_NUM, .rm = FFR_PRED_NUM,
     };
-    return trans_AND_pppp(s, &alt_a, insn);
+    return trans_AND_pppp(s, &alt_a);
 }
 
-static bool trans_RDFFR(DisasContext *s, arg_RDFFR *a, uint32_t insn)
+static bool trans_RDFFR(DisasContext *s, arg_RDFFR *a)
 {
     return do_mov_p(s, a->rd, FFR_PRED_NUM);
 }
 
-static bool trans_WRFFR(DisasContext *s, arg_WRFFR *a, uint32_t insn)
+static bool trans_WRFFR(DisasContext *s, arg_WRFFR *a)
 {
     return do_mov_p(s, FFR_PRED_NUM, a->rn);
 }
@@ -1657,12 +1654,12 @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
     return true;
 }
 
-static bool trans_PFIRST(DisasContext *s, arg_rr_esz *a, uint32_t insn)
+static bool trans_PFIRST(DisasContext *s, arg_rr_esz *a)
 {
     return do_pfirst_pnext(s, a, gen_helper_sve_pfirst);
 }
 
-static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a, uint32_t insn)
+static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a)
 {
     return do_pfirst_pnext(s, a, gen_helper_sve_pnext);
 }
@@ -1836,7 +1833,7 @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,
     tcg_temp_free_i32(tcg_ctx, desc);
 }
 
-static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a, uint32_t insn)
+static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -1847,7 +1844,7 @@ static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a, uint32_t insn)
     return true;
 }
 
-static bool trans_INCDEC_r(DisasContext *s, arg_incdec_cnt *a, uint32_t insn)
+static bool trans_INCDEC_r(DisasContext *s, arg_incdec_cnt *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -1861,8 +1858,7 @@ static bool trans_INCDEC_r(DisasContext *s, arg_incdec_cnt *a, uint32_t insn)
     return true;
 }
 
-static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a,
-                               uint32_t insn)
+static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a)
 {
     if (!sve_access_check(s)) {
         return true;
@@ -1889,8 +1885,7 @@ static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a,
     return true;
 }
 
-static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a,
-                               uint32_t insn)
+static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a)
 {
     if (!sve_access_check(s)) {
         return true;
@@ -1910,7 +1905,7 @@ static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a,
     return true;
 }
 
-static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a, uint32_t insn)
+static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a)
 {
     if (a->esz == 0) {
         return false;
@@ -1935,8 +1930,7 @@ static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a, uint32_t insn)
     return true;
 }
 
-static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a,
-                            uint32_t insn)
+static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a)
 {
     if (a->esz == 0) {
         return false;
@@ -1980,22 +1974,22 @@ static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn)
     return true;
 }
 
-static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn)
+static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a)
 {
     return do_zz_dbm(s, a, tcg_gen_gvec_andi);
 }
 
-static bool trans_ORR_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn)
+static bool trans_ORR_zzi(DisasContext *s, arg_rr_dbm *a)
 {
     return do_zz_dbm(s, a, tcg_gen_gvec_ori);
 }
 
-static bool trans_EOR_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn)
+static bool trans_EOR_zzi(DisasContext *s, arg_rr_dbm *a)
 {
     return do_zz_dbm(s, a, tcg_gen_gvec_xori);
 }
 
-static bool trans_DUPM(DisasContext *s, arg_DUPM *a, uint32_t insn)
+static bool trans_DUPM(DisasContext *s, arg_DUPM *a)
 {
     uint64_t imm;
     if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1),
@@ -2043,7 +2037,7 @@ static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg,
     tcg_temp_free_i32(tcg_ctx, desc);
 }
 
-static bool trans_FCPY(DisasContext *s, arg_FCPY *a, uint32_t insn)
+static bool trans_FCPY(DisasContext *s, arg_FCPY *a)
 {
     if (a->esz == 0) {
         return false;
@@ -2059,9 +2053,9 @@ static bool trans_FCPY(DisasContext *s, arg_FCPY *a, uint32_t insn)
     return true;
 }
 
-static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a, uint32_t insn)
+static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a)
 {
-    if (a->esz == 0 && extract32(insn, 13, 1)) {
+    if (a->esz == 0 && extract32(s->insn, 13, 1)) {
         return false;
     }
     if (sve_access_check(s)) {
@@ -2073,14 +2067,14 @@ static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a, uint32_t insn)
+static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a)
 {
     static gen_helper_gvec_2i * const fns[4] = {
         gen_helper_sve_cpy_z_b, gen_helper_sve_cpy_z_h,
         gen_helper_sve_cpy_z_s, gen_helper_sve_cpy_z_d,
     };
 
-    if (a->esz == 0 && extract32(insn, 13, 1)) {
+    if (a->esz == 0 && extract32(s->insn, 13, 1)) {
         return false;
     }
     if (sve_access_check(s)) {
@@ -2099,7 +2093,7 @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a, uint32_t insn)
  *** SVE Permute Extract Group
  */
 
-static bool trans_EXT(DisasContext *s, arg_EXT *a, uint32_t insn)
+static bool trans_EXT(DisasContext *s, arg_EXT *a)
 {
     if (!sve_access_check(s)) {
         return true;
@@ -2134,7 +2128,7 @@ static bool trans_EXT(DisasContext *s, arg_EXT *a, uint32_t insn)
  *** SVE Permute - Unpredicated Group
  */
 
-static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a, uint32_t insn)
+static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -2145,7 +2139,7 @@ static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a, uint32_t insn)
     return true;
 }
 
-static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a, uint32_t insn)
+static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a)
 {
     if ((a->imm & 0x1f) == 0) {
         return false;
@@ -2192,7 +2186,7 @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val)
     tcg_temp_free_i32(tcg_ctx, desc);
 }
 
-static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -2204,7 +2198,7 @@ static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a)
 {
     if (sve_access_check(s)) {
         do_insr_i64(s, a, cpu_reg(s, a->rm));
@@ -2212,7 +2206,7 @@ static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_REV_v(DisasContext *s, arg_rr_esz *a, uint32_t insn)
+static bool trans_REV_v(DisasContext *s, arg_rr_esz *a)
 {
     static gen_helper_gvec_2 * const fns[4] = {
         gen_helper_sve_rev_b, gen_helper_sve_rev_h,
@@ -2229,7 +2223,7 @@ static bool trans_REV_v(DisasContext *s, arg_rr_esz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_TBL(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         gen_helper_sve_tbl_b, gen_helper_sve_tbl_h,
@@ -2247,7 +2241,7 @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_UNPK(DisasContext *s, arg_UNPK *a, uint32_t insn)
+static bool trans_UNPK(DisasContext *s, arg_UNPK *a)
 {
     static gen_helper_gvec_2 * const fns[4][2] = {
         { NULL, NULL },
@@ -2347,47 +2341,47 @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd,
     return true;
 }
 
-static bool trans_ZIP1_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_ZIP1_p(DisasContext *s, arg_rrr_esz *a)
 {
     return do_perm_pred3(s, a, 0, gen_helper_sve_zip_p);
 }
 
-static bool trans_ZIP2_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_ZIP2_p(DisasContext *s, arg_rrr_esz *a)
 {
     return do_perm_pred3(s, a, 1, gen_helper_sve_zip_p);
 }
 
-static bool trans_UZP1_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_UZP1_p(DisasContext *s, arg_rrr_esz *a)
 {
     return do_perm_pred3(s, a, 0, gen_helper_sve_uzp_p);
 }
 
-static bool trans_UZP2_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_UZP2_p(DisasContext *s, arg_rrr_esz *a)
 {
     return do_perm_pred3(s, a, 1, gen_helper_sve_uzp_p);
 }
 
-static bool trans_TRN1_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_TRN1_p(DisasContext *s, arg_rrr_esz *a)
 {
     return do_perm_pred3(s, a, 0, gen_helper_sve_trn_p);
 }
 
-static bool trans_TRN2_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_TRN2_p(DisasContext *s, arg_rrr_esz *a)
 {
     return do_perm_pred3(s, a, 1, gen_helper_sve_trn_p);
 }
 
-static bool trans_REV_p(DisasContext *s, arg_rr_esz *a, uint32_t insn)
+static bool trans_REV_p(DisasContext *s, arg_rr_esz *a)
 {
     return do_perm_pred2(s, a, 0, gen_helper_sve_rev_p);
 }
 
-static bool trans_PUNPKLO(DisasContext *s, arg_PUNPKLO *a, uint32_t insn)
+static bool trans_PUNPKLO(DisasContext *s, arg_PUNPKLO *a)
 {
     return do_perm_pred2(s, a, 0, gen_helper_sve_punpk_p);
 }
 
-static bool trans_PUNPKHI(DisasContext *s, arg_PUNPKHI *a, uint32_t insn)
+static bool trans_PUNPKHI(DisasContext *s, arg_PUNPKHI *a)
 {
     return do_perm_pred2(s, a, 1, gen_helper_sve_punpk_p);
 }
@@ -2429,12 +2423,12 @@ static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data,
     return true;
 }
 
-static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a)
 {
     return do_zip(s, a, false);
 }
 
-static bool trans_ZIP2_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_ZIP2_z(DisasContext *s, arg_rrr_esz *a)
 {
     return do_zip(s, a, true);
 }
@@ -2444,12 +2438,12 @@ static gen_helper_gvec_3 * const uzp_fns[4] = {
     gen_helper_sve_uzp_s, gen_helper_sve_uzp_d,
 };
 
-static bool trans_UZP1_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_UZP1_z(DisasContext *s, arg_rrr_esz *a)
 {
     return do_zzz_data_ool(s, a, 0, uzp_fns[a->esz]);
 }
 
-static bool trans_UZP2_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_UZP2_z(DisasContext *s, arg_rrr_esz *a)
 {
     return do_zzz_data_ool(s, a, 1 << a->esz, uzp_fns[a->esz]);
 }
@@ -2459,12 +2453,12 @@ static gen_helper_gvec_3 * const trn_fns[4] = {
     gen_helper_sve_trn_s, gen_helper_sve_trn_d,
 };
 
-static bool trans_TRN1_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_TRN1_z(DisasContext *s, arg_rrr_esz *a)
 {
     return do_zzz_data_ool(s, a, 0, trn_fns[a->esz]);
 }
 
-static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a)
 {
     return do_zzz_data_ool(s, a, 1 << a->esz, trn_fns[a->esz]);
 }
@@ -2473,7 +2467,7 @@ static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
  *** SVE Permute Vector - Predicated Group
  */
 
-static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
@@ -2647,12 +2641,12 @@ static bool do_clast_vector(DisasContext *s, arg_rprr_esz *a, bool before)
     return true;
 }
 
-static bool trans_CLASTA_z(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
+static bool trans_CLASTA_z(DisasContext *s, arg_rprr_esz *a)
 {
     return do_clast_vector(s, a, false);
 }
 
-static bool trans_CLASTB_z(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
+static bool trans_CLASTB_z(DisasContext *s, arg_rprr_esz *a)
 {
     return do_clast_vector(s, a, true);
 }
@@ -2707,12 +2701,12 @@ static bool do_clast_fp(DisasContext *s, arg_rpr_esz *a, bool before)
     return true;
 }
 
-static bool trans_CLASTA_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_CLASTA_v(DisasContext *s, arg_rpr_esz *a)
 {
     return do_clast_fp(s, a, false);
 }
 
-static bool trans_CLASTB_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_CLASTB_v(DisasContext *s, arg_rpr_esz *a)
 {
     return do_clast_fp(s, a, true);
 }
@@ -2749,12 +2743,12 @@ static bool do_clast_general(DisasContext *s, arg_rpr_esz *a, bool before)
     return true;
 }
 
-static bool trans_CLASTA_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_CLASTA_r(DisasContext *s, arg_rpr_esz *a)
 {
     return do_clast_general(s, a, false);
 }
 
-static bool trans_CLASTB_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_CLASTB_r(DisasContext *s, arg_rpr_esz *a)
 {
     return do_clast_general(s, a, true);
 }
@@ -2791,12 +2785,12 @@ static bool do_last_fp(DisasContext *s, arg_rpr_esz *a, bool before)
     return true;
 }
 
-static bool trans_LASTA_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_LASTA_v(DisasContext *s, arg_rpr_esz *a)
 {
     return do_last_fp(s, a, false);
 }
 
-static bool trans_LASTB_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_LASTB_v(DisasContext *s, arg_rpr_esz *a)
 {
     return do_last_fp(s, a, true);
 }
@@ -2813,17 +2807,17 @@ static bool do_last_general(DisasContext *s, arg_rpr_esz *a, bool before)
     return true;
 }
 
-static bool trans_LASTA_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_LASTA_r(DisasContext *s, arg_rpr_esz *a)
 {
     return do_last_general(s, a, false);
 }
 
-static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a)
 {
     return do_last_general(s, a, true);
 }
 
-static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a)
 {
     if (sve_access_check(s)) {
         do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, cpu_reg_sp(s, a->rn));
@@ -2831,7 +2825,7 @@ static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -2843,7 +2837,7 @@ static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_REVB(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_REVB(DisasContext *s, arg_rpr_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         NULL,
@@ -2854,7 +2848,7 @@ static bool trans_REVB(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
     return do_zpz_ool(s, a, fns[a->esz]);
 }
 
-static bool trans_REVH(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_REVH(DisasContext *s, arg_rpr_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         NULL,
@@ -2865,12 +2859,12 @@ static bool trans_REVH(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
     return do_zpz_ool(s, a, fns[a->esz]);
 }
 
-static bool trans_REVW(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_REVW(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_revw_d : NULL);
 }
 
-static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
 {
     static gen_helper_gvec_3 * const fns[4] = {
         gen_helper_sve_rbit_b,
@@ -2881,7 +2875,7 @@ static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
     return do_zpz_ool(s, a, fns[a->esz]);
 }
 
-static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
+static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -2941,8 +2935,7 @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
 }
 
 #define DO_PPZZ(NAME, name) \
-static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a,         \
-                                uint32_t insn)                            \
+static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a)         \
 {                                                                         \
     static gen_helper_gvec_flags_4 * const fns[4] = {                     \
         gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h,   \
@@ -2961,8 +2954,7 @@ DO_PPZZ(CMPHS, cmphs)
 #undef DO_PPZZ
 
 #define DO_PPZW(NAME, name) \
-static bool trans_##NAME##_ppzw(DisasContext *s, arg_rprr_esz *a,         \
-                                uint32_t insn)                            \
+static bool trans_##NAME##_ppzw(DisasContext *s, arg_rprr_esz *a)         \
 {                                                                         \
     static gen_helper_gvec_flags_4 * const fns[4] = {                     \
         gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h,   \
@@ -3027,8 +3019,7 @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a,
 }
 
 #define DO_PPZI(NAME, name) \
-static bool trans_##NAME##_ppzi(DisasContext *s, arg_rpri_esz *a,         \
-                                uint32_t insn)                            \
+static bool trans_##NAME##_ppzi(DisasContext *s, arg_rpri_esz *a)         \
 {                                                                         \
     static gen_helper_gvec_flags_3 * const fns[4] = {                     \
         gen_helper_sve_##name##_ppzi_b, gen_helper_sve_##name##_ppzi_h,   \
@@ -3123,37 +3114,37 @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a,
     return true;
 }
 
-static bool trans_BRKPA(DisasContext *s, arg_rprr_s *a, uint32_t insn)
+static bool trans_BRKPA(DisasContext *s, arg_rprr_s *a)
 {
     return do_brk3(s, a, gen_helper_sve_brkpa, gen_helper_sve_brkpas);
 }
 
-static bool trans_BRKPB(DisasContext *s, arg_rprr_s *a, uint32_t insn)
+static bool trans_BRKPB(DisasContext *s, arg_rprr_s *a)
 {
     return do_brk3(s, a, gen_helper_sve_brkpb, gen_helper_sve_brkpbs);
 }
 
-static bool trans_BRKA_m(DisasContext *s, arg_rpr_s *a, uint32_t insn)
+static bool trans_BRKA_m(DisasContext *s, arg_rpr_s *a)
 {
     return do_brk2(s, a, gen_helper_sve_brka_m, gen_helper_sve_brkas_m);
 }
 
-static bool trans_BRKB_m(DisasContext *s, arg_rpr_s *a, uint32_t insn)
+static bool trans_BRKB_m(DisasContext *s, arg_rpr_s *a)
 {
     return do_brk2(s, a, gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m);
 }
 
-static bool trans_BRKA_z(DisasContext *s, arg_rpr_s *a, uint32_t insn)
+static bool trans_BRKA_z(DisasContext *s, arg_rpr_s *a)
 {
     return do_brk2(s, a, gen_helper_sve_brka_z, gen_helper_sve_brkas_z);
 }
 
-static bool trans_BRKB_z(DisasContext *s, arg_rpr_s *a, uint32_t insn)
+static bool trans_BRKB_z(DisasContext *s, arg_rpr_s *a)
 {
     return do_brk2(s, a, gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z);
 }
 
-static bool trans_BRKN(DisasContext *s, arg_rpr_s *a, uint32_t insn)
+static bool trans_BRKN(DisasContext *s, arg_rpr_s *a)
 {
     return do_brk2(s, a, gen_helper_sve_brkn, gen_helper_sve_brkns);
 }
@@ -3205,7 +3196,7 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg)
     }
 }
 
-static bool trans_CNTP(DisasContext *s, arg_CNTP *a, uint32_t insn)
+static bool trans_CNTP(DisasContext *s, arg_CNTP *a)
 {
     if (sve_access_check(s)) {
         do_cntp(s, cpu_reg(s, a->rd), a->esz, a->rn, a->pg);
@@ -3213,8 +3204,7 @@ static bool trans_CNTP(DisasContext *s, arg_CNTP *a, uint32_t insn)
     return true;
 }
 
-static bool trans_INCDECP_r(DisasContext *s, arg_incdec_pred *a,
-                            uint32_t insn)
+static bool trans_INCDECP_r(DisasContext *s, arg_incdec_pred *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -3232,8 +3222,7 @@ static bool trans_INCDECP_r(DisasContext *s, arg_incdec_pred *a,
     return true;
 }
 
-static bool trans_INCDECP_z(DisasContext *s, arg_incdec2_pred *a,
-                            uint32_t insn)
+static bool trans_INCDECP_z(DisasContext *s, arg_incdec2_pred *a)
 {
     if (a->esz == 0) {
         return false;
@@ -3251,8 +3240,7 @@ static bool trans_INCDECP_z(DisasContext *s, arg_incdec2_pred *a,
     return true;
 }
 
-static bool trans_SINCDECP_r_32(DisasContext *s, arg_incdec_pred *a,
-                                uint32_t insn)
+static bool trans_SINCDECP_r_32(DisasContext *s, arg_incdec_pred *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -3265,8 +3253,7 @@ static bool trans_SINCDECP_r_32(DisasContext *s, arg_incdec_pred *a,
     return true;
 }
 
-static bool trans_SINCDECP_r_64(DisasContext *s, arg_incdec_pred *a,
-                                uint32_t insn)
+static bool trans_SINCDECP_r_64(DisasContext *s, arg_incdec_pred *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -3279,8 +3266,7 @@ static bool trans_SINCDECP_r_64(DisasContext *s, arg_incdec_pred *a,
     return true;
 }
 
-static bool trans_SINCDECP_z(DisasContext *s, arg_incdec2_pred *a,
-                             uint32_t insn)
+static bool trans_SINCDECP_z(DisasContext *s, arg_incdec2_pred *a)
 {
     if (a->esz == 0) {
         return false;
@@ -3298,7 +3284,7 @@ static bool trans_SINCDECP_z(DisasContext *s, arg_incdec2_pred *a,
  *** SVE Integer Compare Scalars Group
  */
 
-static bool trans_CTERM(DisasContext *s, arg_CTERM *a, uint32_t insn)
+static bool trans_CTERM(DisasContext *s, arg_CTERM *a)
 {
     if (!sve_access_check(s)) {
         return true;
@@ -3324,7 +3310,7 @@ static bool trans_CTERM(DisasContext *s, arg_CTERM *a, uint32_t insn)
     return true;
 }
 
-static bool trans_WHILE(DisasContext *s, arg_WHILE *a, uint32_t insn)
+static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
 {
     TCGContext *tcg_ctx = s->uc->tcg_ctx;
     TCGv_i64 op0, op1, t0, t1, tmax;
@@ -3414,7 +3400,7 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a, uint32_t insn)
  *** SVE Integer Wide Immediate - Unpredicated Group
  */
 
-static bool trans_FDUP(DisasContext *s, arg_FDUP *a, uint32_t insn)
+static bool trans_FDUP(DisasContext *s, arg_FDUP *a)
 {
     if (a->esz == 0) {
         return false;
@@ -3434,9 +3420,9 @@ static bool trans_FDUP(DisasContext *s, arg_FDUP *a, uint32_t insn)
     return true;
 }
 
-static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a, uint32_t insn)
+static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
 {
-    if (a->esz == 0 && extract32(insn, 13, 1)) {
+    if (a->esz == 0 && extract32(s->insn, 13, 1)) {
         return false;
     }
     if (sve_access_check(s)) {
@@ -3449,9 +3435,9 @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a, uint32_t insn)
     return true;
 }
 
-static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
+static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a)
 {
-    if (a->esz == 0 && extract32(insn, 13, 1)) {
+    if (a->esz == 0 && extract32(s->insn, 13, 1)) {
         return false;
     }
     if (sve_access_check(s)) {
@@ -3463,13 +3449,13 @@ static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
+static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a)
 {
     a->imm = -a->imm;
-    return trans_ADD_zzi(s, a, insn);
+    return trans_ADD_zzi(s, a);
 }
 
-static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
+static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)
 {
     static const GVecGen2s op[4] = {
         {
@@ -3518,7 +3504,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
         }
     };
 
-    if (a->esz == 0 && extract32(insn, 13, 1)) {
+    if (a->esz == 0 && extract32(s->insn, 13, 1)) {
         return false;
     }
     if (sve_access_check(s)) {
@@ -3533,7 +3519,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_MUL_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
+static bool trans_MUL_zzi(DisasContext *s, arg_rri_esz *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -3544,10 +3530,9 @@ static bool trans_MUL_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
     return true;
 }
 
-static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, uint32_t insn,
-                       bool u, bool d)
+static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
 {
-    if (a->esz == 0 && extract32(insn, 13, 1)) {
+    if (a->esz == 0 && extract32(s->insn, 13, 1)) {
         return false;
     }
     if (sve_access_check(s)) {
@@ -3559,24 +3544,24 @@ static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, uint32_t insn,
     return true;
 }
 
-static bool trans_SQADD_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
+static bool trans_SQADD_zzi(DisasContext *s, arg_rri_esz *a)
 {
-    return do_zzi_sat(s, a, insn, false, false);
+    return do_zzi_sat(s, a, false, false);
 }
 
-static bool trans_UQADD_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
+static bool trans_UQADD_zzi(DisasContext *s, arg_rri_esz *a)
 {
-    return do_zzi_sat(s, a, insn, true, false);
+    return do_zzi_sat(s, a, true, false);
 }
 
-static bool trans_SQSUB_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
+static bool trans_SQSUB_zzi(DisasContext *s, arg_rri_esz *a)
 {
-    return do_zzi_sat(s, a, insn, false, true);
+    return do_zzi_sat(s, a, false, true);
 }
 
-static bool trans_UQSUB_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn)
+static bool trans_UQSUB_zzi(DisasContext *s, arg_rri_esz *a)
 {
-    return do_zzi_sat(s, a, insn, true, true);
+    return do_zzi_sat(s, a, true, true);
 }
 
 static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn)
@@ -3595,8 +3580,7 @@ static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn)
 }
 
 #define DO_ZZI(NAME, name) \
-static bool trans_##NAME##_zzi(DisasContext *s, arg_rri_esz *a,         \
-                               uint32_t insn)                           \
+static bool trans_##NAME##_zzi(DisasContext *s, arg_rri_esz *a)         \
 {                                                                       \
     static gen_helper_gvec_2i * const fns[4] = {                        \
         gen_helper_sve_##name##i_b, gen_helper_sve_##name##i_h,         \
@@ -3616,7 +3600,7 @@ DO_ZZI(UMIN, umin)
  *** SVE Floating Point Multiply-Add Indexed Group
  */
 
-static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a, uint32_t insn)
+static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a)
 {
     static gen_helper_gvec_4_ptr * const fns[3] = {
         gen_helper_gvec_fmla_idx_h,
@@ -3643,7 +3627,7 @@ static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a, uint32_t insn)
  *** SVE Floating Point Multiply Indexed Group
  */
 
-static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a, uint32_t insn)
+static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a)
 {
     static gen_helper_gvec_3_ptr * const fns[3] = {
         gen_helper_gvec_fmul_idx_h,
@@ -3700,7 +3684,7 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
 }
 
 #define DO_VPZ(NAME, name) \
-static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \
+static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a)                \
 {                                                                        \
     static gen_helper_fp_reduce * const fns[3] = {                       \
         gen_helper_sve_##name##_h,                                       \
@@ -3738,7 +3722,7 @@ static void do_zz_fp(DisasContext *s, arg_rr_esz *a, gen_helper_gvec_2_ptr *fn)
     tcg_temp_free_ptr(tcg_ctx, status);
 }
 
-static bool trans_FRECPE(DisasContext *s, arg_rr_esz *a, uint32_t insn)
+static bool trans_FRECPE(DisasContext *s, arg_rr_esz *a)
 {
     static gen_helper_gvec_2_ptr * const fns[3] = {
         gen_helper_gvec_frecpe_h,
@@ -3754,7 +3738,7 @@ static bool trans_FRECPE(DisasContext *s, arg_rr_esz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_FRSQRTE(DisasContext *s, arg_rr_esz *a, uint32_t insn)
+static bool trans_FRSQRTE(DisasContext *s, arg_rr_esz *a)
 {
     static gen_helper_gvec_2_ptr * const fns[3] = {
         gen_helper_gvec_frsqrte_h,
@@ -3789,7 +3773,7 @@ static void do_ppz_fp(DisasContext *s, arg_rpr_esz *a,
 }
 
 #define DO_PPZ(NAME, name) \
-static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \
+static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a)         \
 {                                                                 \
     static gen_helper_gvec_3_ptr * const fns[3] = {               \
         gen_helper_sve_##name##_h,                                \
@@ -3818,7 +3802,7 @@ DO_PPZ(FCMNE_ppz0, fcmne0)
  *** SVE floating-point trig multiply-add coefficient
  */
 
-static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a, uint32_t insn)
+static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a)
 {
     static gen_helper_gvec_3_ptr * const fns[3] = {
         gen_helper_sve_ftmad_h,
@@ -3846,7 +3830,7 @@ static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a, uint32_t insn)
  *** SVE Floating Point Accumulating Reduction Group
  */
 
-static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
+static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
 {
     typedef void fadda_fn(TCGContext *, TCGv_i64, TCGv_i64, TCGv_ptr,
                           TCGv_ptr, TCGv_ptr, TCGv_i32);
@@ -3913,7 +3897,7 @@ static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a,
 
 
 #define DO_FP3(NAME, name) \
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a, uint32_t insn) \
+static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a)           \
 {                                                                   \
     static gen_helper_gvec_3_ptr * const fns[4] = {                 \
         NULL, gen_helper_gvec_##name##_h,                           \
@@ -3956,7 +3940,7 @@ static bool do_zpzz_fp(DisasContext *s, arg_rprr_esz *a,
 }
 
 #define DO_FP3(NAME, name) \
-static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a, uint32_t insn) \
+static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a)          \
 {                                                                   \
     static gen_helper_gvec_4_ptr * const fns[4] = {                 \
         NULL, gen_helper_sve_##name##_h,                            \
@@ -4018,8 +4002,7 @@ static void do_fp_imm(DisasContext *s, arg_rpri_esz *a, uint64_t imm,
 }
 
 #define DO_FP_IMM(NAME, name, const0, const1) \
-static bool trans_##NAME##_zpzi(DisasContext *s, arg_rpri_esz *a,         \
-                                uint32_t insn)                            \
+static bool trans_##NAME##_zpzi(DisasContext *s, arg_rpri_esz *a)         \
 {                                                                         \
     static gen_helper_sve_fp2scalar * const fns[3] = {                    \
         gen_helper_sve_##name##_h,                                        \
@@ -4076,8 +4059,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *a,
 }
 
 #define DO_FPCMP(NAME, name) \
-static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a,     \
-                                uint32_t insn)                        \
+static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a)     \
 {                                                                     \
     static gen_helper_gvec_4_ptr * const fns[4] = {                   \
         NULL, gen_helper_sve_##name##_h,                              \
@@ -4096,7 +4078,7 @@ DO_FPCMP(FACGT, facgt)
 
 #undef DO_FPCMP
 
-static bool trans_FCADD(DisasContext *s, arg_FCADD *a, uint32_t insn)
+static bool trans_FCADD(DisasContext *s, arg_FCADD *a)
 {
     static gen_helper_gvec_4_ptr * const fns[3] = {
         gen_helper_sve_fcadd_h,
@@ -4155,7 +4137,7 @@ static bool do_fmla(DisasContext *s, arg_rprrr_esz *a, gen_helper_sve_fmla *fn)
 }
 
 #define DO_FMLA(NAME, name) \
-static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a, uint32_t insn) \
+static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a)          \
 {                                                                    \
     static gen_helper_sve_fmla * const fns[4] = {                    \
         NULL, gen_helper_sve_##name##_h,                             \
@@ -4171,8 +4153,7 @@ DO_FMLA(FNMLS_zpzzz, fnmls_zpzzz)
 
 #undef DO_FMLA
 
-static bool trans_FCMLA_zpzzz(DisasContext *s,
-                              arg_FCMLA_zpzzz *a, uint32_t insn)
+static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
 {
     static gen_helper_sve_fmla * const fns[3] = {
         gen_helper_sve_fcmla_zpzzz_h,
@@ -4209,7 +4190,7 @@ static bool trans_FCMLA_zpzzz(DisasContext *s,
     return true;
 }
 
-static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a, uint32_t insn)
+static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a)
 {
     static gen_helper_gvec_3_ptr * const fns[2] = {
         gen_helper_gvec_fcmlah_idx,
@@ -4253,102 +4234,102 @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg,
     return true;
 }
 
-static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh);
 }
 
-static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hs);
 }
 
-static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh);
 }
 
-static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hd);
 }
 
-static bool trans_FCVT_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVT_ds(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_ds);
 }
 
-static bool trans_FCVT_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVT_sd(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sd);
 }
 
-static bool trans_FCVTZS_hh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVTZS_hh(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hh);
 }
 
-static bool trans_FCVTZU_hh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVTZU_hh(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hh);
 }
 
-static bool trans_FCVTZS_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVTZS_hs(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hs);
 }
 
-static bool trans_FCVTZU_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVTZU_hs(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hs);
 }
 
-static bool trans_FCVTZS_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVTZS_hd(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hd);
 }
 
-static bool trans_FCVTZU_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVTZU_hd(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hd);
 }
 
-static bool trans_FCVTZS_ss(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVTZS_ss(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_ss);
 }
 
-static bool trans_FCVTZU_ss(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVTZU_ss(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_ss);
 }
 
-static bool trans_FCVTZS_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVTZS_sd(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_sd);
 }
 
-static bool trans_FCVTZU_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVTZU_sd(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_sd);
 }
 
-static bool trans_FCVTZS_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVTZS_ds(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_ds);
 }
 
-static bool trans_FCVTZU_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVTZU_ds(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_ds);
 }
 
-static bool trans_FCVTZS_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVTZS_dd(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_dd);
 }
 
-static bool trans_FCVTZU_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FCVTZU_dd(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_dd);
 }
@@ -4359,7 +4340,7 @@ static gen_helper_gvec_3_ptr * const frint_fns[3] = {
     gen_helper_sve_frint_d
 };
 
-static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a)
 {
     if (a->esz == 0) {
         return false;
@@ -4368,7 +4349,7 @@ static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
                       frint_fns[a->esz - 1]);
 }
 
-static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a)
 {
     static gen_helper_gvec_3_ptr * const fns[3] = {
         gen_helper_sve_frintx_h,
@@ -4406,32 +4387,32 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, int mode)
     return true;
 }
 
-static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a)
 {
     return do_frint_mode(s, a, float_round_nearest_even);
 }
 
-static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a)
 {
     return do_frint_mode(s, a, float_round_up);
 }
 
-static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a)
 {
     return do_frint_mode(s, a, float_round_down);
 }
 
-static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a)
 {
     return do_frint_mode(s, a, float_round_to_zero);
 }
 
-static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
 {
     return do_frint_mode(s, a, float_round_ties_away);
 }
 
-static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a)
 {
     static gen_helper_gvec_3_ptr * const fns[3] = {
         gen_helper_sve_frecpx_h,
@@ -4444,7 +4425,7 @@ static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);
 }
 
-static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a)
 {
     static gen_helper_gvec_3_ptr * const fns[3] = {
         gen_helper_sve_fsqrt_h,
@@ -4457,72 +4438,72 @@ static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);
 }
 
-static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_hh);
 }
 
-static bool trans_SCVTF_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_SCVTF_sh(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_sh);
 }
 
-static bool trans_SCVTF_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_SCVTF_dh(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_dh);
 }
 
-static bool trans_SCVTF_ss(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_SCVTF_ss(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ss);
 }
 
-static bool trans_SCVTF_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_SCVTF_ds(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ds);
 }
 
-static bool trans_SCVTF_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_SCVTF_sd(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_sd);
 }
 
-static bool trans_SCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_SCVTF_dd(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_dd);
 }
 
-static bool trans_UCVTF_hh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_UCVTF_hh(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_hh);
 }
 
-static bool trans_UCVTF_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_UCVTF_sh(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_sh);
 }
 
-static bool trans_UCVTF_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_UCVTF_dh(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_dh);
 }
 
-static bool trans_UCVTF_ss(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_UCVTF_ss(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ss);
 }
 
-static bool trans_UCVTF_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_UCVTF_ds(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ds);
 }
 
-static bool trans_UCVTF_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_UCVTF_sd(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_sd);
 }
 
-static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a)
 {
     return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_dd);
 }
@@ -4703,7 +4684,7 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
     tcg_temp_free_i64(tcg_ctx, t0);
 }
 
-static bool trans_LDR_zri(DisasContext *s, arg_rri *a, uint32_t insn)
+static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
 {
     if (sve_access_check(s)) {
         int size = vec_full_reg_size(s);
@@ -4713,7 +4694,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a, uint32_t insn)
     return true;
 }
 
-static bool trans_LDR_pri(DisasContext *s, arg_rri *a, uint32_t insn)
+static bool trans_LDR_pri(DisasContext *s, arg_rri *a)
 {
     if (sve_access_check(s)) {
         int size = pred_full_reg_size(s);
@@ -4723,7 +4704,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a, uint32_t insn)
     return true;
 }
 
-static bool trans_STR_zri(DisasContext *s, arg_rri *a, uint32_t insn)
+static bool trans_STR_zri(DisasContext *s, arg_rri *a)
 {
     if (sve_access_check(s)) {
         int size = vec_full_reg_size(s);
@@ -4733,7 +4714,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a, uint32_t insn)
     return true;
 }
 
-static bool trans_STR_pri(DisasContext *s, arg_rri *a, uint32_t insn)
+static bool trans_STR_pri(DisasContext *s, arg_rri *a)
 {
     if (sve_access_check(s)) {
         int size = pred_full_reg_size(s);
@@ -4859,7 +4840,7 @@ static void do_ld_zpa(DisasContext *s, int zt, int pg,
     do_mem_zpa(s, zt, pg, addr, dtype, fn);
 }
 
-static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn)
+static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a)
 {
     if (a->rm == 31) {
         return false;
@@ -4874,7 +4855,7 @@ static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn)
     return true;
 }
 
-static bool trans_LD_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
+static bool trans_LD_zpri(DisasContext *s, arg_rpri_load *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -4890,7 +4871,7 @@ static bool trans_LD_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
     return true;
 }
 
-static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn)
+static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a)
 {
     static gen_helper_gvec_mem * const fns[2][16] = {
         /* Little-endian */
@@ -4947,7 +4928,7 @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn)
     return true;
 }
 
-static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
+static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a)
 {
     static gen_helper_gvec_mem * const fns[2][16] = {
         /* Little-endian */
@@ -5061,7 +5042,7 @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz)
     }
 }
 
-static bool trans_LD1RQ_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn)
+static bool trans_LD1RQ_zprr(DisasContext *s, arg_rprr_load *a)
 {
     if (a->rm == 31) {
         return false;
@@ -5077,7 +5058,7 @@ static bool trans_LD1RQ_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn)
     return true;
 }
 
-static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
+static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a)
 {
     if (sve_access_check(s)) {
         TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -5089,7 +5070,7 @@ static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
 }
 
 /* Load and broadcast element.  */
-static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
+static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a)
 {
     if (!sve_access_check(s)) {
         return true;
@@ -5210,7 +5191,7 @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
     do_mem_zpa(s, zt, pg, addr, msz_dtype(msz), fn);
 }
 
-static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a, uint32_t insn)
+static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a)
 {
     if (a->rm == 31 || a->msz > a->esz) {
         return false;
@@ -5225,7 +5206,7 @@ static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a, uint32_t insn)
     return true;
 }
 
-static bool trans_ST_zpri(DisasContext *s, arg_rpri_store *a, uint32_t insn)
+static bool trans_ST_zpri(DisasContext *s, arg_rpri_store *a)
 {
     if (a->msz > a->esz) {
         return false;
@@ -5441,7 +5422,7 @@ static gen_helper_gvec_mem_scatter * const gather_load_fn64[2][2][3][2][4] = {
             gen_helper_sve_ldffdd_be_zd, } } } },
 };
 
-static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a, uint32_t insn)
+static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a)
 {
     gen_helper_gvec_mem_scatter *fn = NULL;
     int be = s->be_data == MO_BE;
@@ -5465,7 +5446,7 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a, uint32_t insn)
+static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)
 {
     gen_helper_gvec_mem_scatter *fn = NULL;
     int be = s->be_data == MO_BE;
@@ -5548,7 +5529,7 @@ static gen_helper_gvec_mem_scatter * const scatter_store_fn64[2][3][4] = {
         gen_helper_sve_stdd_be_zd, } },
 };
 
-static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a, uint32_t insn)
+static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a)
 {
     gen_helper_gvec_mem_scatter *fn;
     int be = s->be_data == MO_BE;
@@ -5574,7 +5555,7 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a, uint32_t insn)
+static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
 {
     gen_helper_gvec_mem_scatter *fn = NULL;
     int be = s->be_data == MO_BE;
@@ -5612,14 +5593,14 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a, uint32_t insn)
  * Prefetches
  */
 
-static bool trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn)
+static bool trans_PRF(DisasContext *s, arg_PRF *a)
 {
     /* Prefetch is a nop within QEMU.  */
     (void)sve_access_check(s);
     return true;
 }
 
-static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a, uint32_t insn)
+static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a)
 {
     if (a->rm == 31) {
         return false;
@@ -5643,12 +5624,12 @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a, uint32_t insn)
  * In the meantime, just emit the moves.
  */
 
-static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a, uint32_t insn)
+static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a)
 {
     return do_mov_z(s, a->rd, a->rn);
 }
 
-static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a)
 {
     if (sve_access_check(s)) {
         do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz);
@@ -5656,7 +5637,7 @@ static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
     return true;
 }
 
-static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a)
 {
     if (sve_access_check(s)) {
         do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz);