From 4e498cc54dc4ac75512f19cc55603907ff541913 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 27 Feb 2018 09:51:08 -0500 Subject: [PATCH] target-m68k: Reorg flags handling Separate all ccr bits. Continue to batch updates via cc_op. Backports commit 620c6cf66584bfbee90db84a7e87a6eabf230ca9 from qemu --- qemu/target-m68k/translate.c | 424 +++++++++++++++-------------------- qemu/tcg/tcg.h | 6 +- 2 files changed, 189 insertions(+), 241 deletions(-) diff --git a/qemu/target-m68k/translate.c b/qemu/target-m68k/translate.c index cdf403ad..2f3befef 100644 --- a/qemu/target-m68k/translate.c +++ b/qemu/target-m68k/translate.c @@ -147,58 +147,46 @@ typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn); #endif static const uint8_t cc_op_live[CC_OP_NB] = { - USES_CC_DST | USES_CC_SRC, - USES_CC_DST, - USES_CC_DST, - USES_CC_DST, - USES_CC_DST, - USES_CC_DST | USES_CC_SRC, - USES_CC_DST | USES_CC_SRC, - USES_CC_DST | USES_CC_SRC, - USES_CC_DST | USES_CC_SRC, - USES_CC_DST | USES_CC_SRC, - USES_CC_DST | USES_CC_SRC, - USES_CC_DST | USES_CC_SRC, - USES_CC_DST | USES_CC_SRC, - USES_CC_DST | USES_CC_SRC, - USES_CC_DST | USES_CC_SRC, - USES_CC_DST | USES_CC_SRC, - USES_CC_DST | USES_CC_SRC, - USES_CC_DST | USES_CC_SRC, - USES_CC_DST | USES_CC_SRC, - USES_CC_DST | USES_CC_SRC, + CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X, + CCF_X | CCF_N | CCF_V, + CCF_X | CCF_N | CCF_V, + CCF_X | CCF_N | CCF_V, + CCF_X | CCF_N, }; static void set_cc_op(DisasContext *s, CCOp op) { TCGContext *tcg_ctx = s->uc->tcg_ctx; + CCOp old_op = s->cc_op; int dead; - if (s->cc_op == op) { + if (old_op == op) { return; } - - /* Discard CC computation that will no longer be used. */ - - dead = cc_op_live[s->cc_op] & ~cc_op_live[op]; - if (dead & USES_CC_DST) { - tcg_gen_discard_i32(tcg_ctx, tcg_ctx->QREG_CC_DEST); - } - if (dead & USES_CC_SRC) { - tcg_gen_discard_i32(tcg_ctx, tcg_ctx->QREG_CC_SRC); - } - if (s->cc_op == CC_OP_DYNAMIC) { - tcg_gen_discard_i32(tcg_ctx, tcg_ctx->QREG_CC_OP); - } s->cc_op = op; + s->cc_op_synced = 0; + + /* Discard CC computation that will no longer be used. + Note that X and N are never dead. */ + dead = cc_op_live[old_op] & ~cc_op_live[op]; + if (dead & CCF_C) { + tcg_gen_discard_i32(tcg_ctx, tcg_ctx->QREG_CC_C); + } + if (dead & CCF_Z) { + tcg_gen_discard_i32(tcg_ctx, tcg_ctx->QREG_CC_Z); + } + if (dead & CCF_V) { + tcg_gen_discard_i32(tcg_ctx, tcg_ctx->QREG_CC_V); + } } /* Update the CPU env CC_OP state. */ -static inline void update_cc_op(DisasContext *s) +static void update_cc_op(DisasContext *s) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - if (s->cc_op != CC_OP_DYNAMIC) { + if (!s->cc_op_synced) { + s->cc_op_synced = 1; tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_OP, s->cc_op); } } @@ -443,46 +431,85 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) /* Evaluate all the CC flags. */ -static inline void gen_flush_flags(DisasContext *s) +static void gen_flush_flags(DisasContext *s) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - if (s->cc_op == CC_OP_FLAGS) + TCGv tmp; + + switch (s->cc_op) { + case CC_OP_FLAGS: return; - if (s->cc_op == CC_OP_DYNAMIC) { - gen_helper_flush_flags(tcg_ctx, tcg_ctx->QREG_CC_DEST, - tcg_ctx->cpu_env, tcg_ctx->QREG_CC_OP); - } else { - gen_helper_flush_flags(tcg_ctx, tcg_ctx->QREG_CC_DEST, - tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, s->cc_op)); + case CC_OP_DYNAMIC: + gen_helper_flush_flags(tcg_ctx, tcg_ctx->cpu_env, tcg_ctx->QREG_CC_OP); + break; + default: + tmp = tcg_const_i32(tcg_ctx, s->cc_op); + gen_helper_flush_flags(tcg_ctx, tcg_ctx->cpu_env, tmp); + tcg_temp_free(tcg_ctx, tmp); + break; } - set_cc_op(s, CC_OP_FLAGS); + + /* Note that flush_flags also assigned to env->cc_op. */ + s->cc_op = CC_OP_FLAGS; + s->cc_op_synced = 1; } -#define SET_CC_OP(opsize, op) do { \ - switch (opsize) { \ - case OS_BYTE: \ - set_cc_op(s, CC_OP_##op##B); break; \ - case OS_WORD: \ - set_cc_op(s, CC_OP_##op##W); break; \ - case OS_LONG: \ - set_cc_op(s, CC_OP_##op); break; \ - default: \ - abort(); \ - } \ -} while (0) +/* Sign or zero extend a value. */ + +static inline void gen_ext(DisasContext *s, TCGv res, TCGv val, int opsize, int sign) +{ + TCGContext *tcg_ctx = s->uc->tcg_ctx; + + switch (opsize) { + case OS_BYTE: + if (sign) { + tcg_gen_ext8s_i32(tcg_ctx, res, val); + } else { + tcg_gen_ext8u_i32(tcg_ctx, res, val); + } + break; + case OS_WORD: + if (sign) { + tcg_gen_ext16s_i32(tcg_ctx, res, val); + } else { + tcg_gen_ext16u_i32(tcg_ctx, res, val); + } + break; + case OS_LONG: + tcg_gen_mov_i32(tcg_ctx, res, val); + break; + default: + g_assert_not_reached(); + } +} + +static TCGv gen_extend(DisasContext *s, TCGv val, int opsize, int sign) +{ + TCGv tmp; + TCGContext *tcg_ctx = s->uc->tcg_ctx; + + if (opsize == OS_LONG) { + tmp = val; + } else { + tmp = tcg_temp_new(tcg_ctx); + gen_ext(s, tmp, val, opsize, sign); + } + + return tmp; +} static void gen_logic_cc(DisasContext *s, TCGv val, int opsize) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - tcg_gen_mov_i32(tcg_ctx, tcg_ctx->QREG_CC_DEST, val); - SET_CC_OP(opsize, LOGIC); + gen_ext(s, tcg_ctx->QREG_CC_N, val, opsize, 1); + set_cc_op(s, CC_OP_LOGIC); } static void gen_update_cc_add(DisasContext *s, TCGv dest, TCGv src) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - tcg_gen_mov_i32(tcg_ctx, tcg_ctx->QREG_CC_DEST, dest); - tcg_gen_mov_i32(tcg_ctx, tcg_ctx->QREG_CC_SRC, src); + tcg_gen_mov_i32(tcg_ctx, tcg_ctx->QREG_CC_N, dest); + tcg_gen_mov_i32(tcg_ctx, tcg_ctx->QREG_CC_V, src); } static inline int opsize_bytes(int opsize) @@ -543,37 +570,6 @@ static void gen_partset_reg(DisasContext *s, int opsize, TCGv reg, TCGv val) } } -/* Sign or zero extend a value. */ -static inline TCGv gen_extend(DisasContext *s, TCGv val, int opsize, int sign) -{ - TCGContext *tcg_ctx = s->uc->tcg_ctx; - TCGv tmp; - - switch (opsize) { - case OS_BYTE: - tmp = tcg_temp_new(tcg_ctx); - if (sign) - tcg_gen_ext8s_i32(tcg_ctx, tmp, val); - else - tcg_gen_ext8u_i32(tcg_ctx, tmp, val); - break; - case OS_WORD: - tmp = tcg_temp_new(tcg_ctx); - if (sign) - tcg_gen_ext16s_i32(tcg_ctx, tmp, val); - else - tcg_gen_ext16u_i32(tcg_ctx, tmp, val); - break; - case OS_LONG: - case OS_SINGLE: - tmp = val; - break; - default: - g_assert_not_reached(); - } - return tmp; -} - /* Generate code for an "effective address". Does not adjust the base register for autoincrement addressing modes. */ static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn, @@ -756,7 +752,8 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - TCGv tmp; + TCGv tmp, tmp2; + TCGCond tcond; /* TODO: Optimize compare/branch pairs rather than always flushing flag state to CC_OP_FLAGS. */ @@ -765,97 +762,57 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) switch (cond) { case 0: /* T */ tcg_gen_br(tcg_ctx, l1); - break; + return; case 1: /* F */ - break; - case 2: /* HI (!C && !Z) */ - tmp = tcg_temp_new(tcg_ctx); - tcg_gen_andi_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_DEST, CCF_C | CCF_Z); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_EQ, tmp, 0, l1); - break; + return; + case 2: /* HI (!C && !Z) -> !(C || Z)*/ case 3: /* LS (C || Z) */ tmp = tcg_temp_new(tcg_ctx); - tcg_gen_andi_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_DEST, CCF_C | CCF_Z); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tmp, 0, l1); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tmp, tcg_ctx->QREG_CC_Z, 0); + tcg_gen_or_i32(tcg_ctx, tmp, tmp, tcg_ctx->QREG_CC_C); + tcond = (cond & 1 ? TCG_COND_NE : TCG_COND_EQ); break; case 4: /* CC (!C) */ - tmp = tcg_temp_new(tcg_ctx); - tcg_gen_andi_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_DEST, CCF_C); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_EQ, tmp, 0, l1); - break; case 5: /* CS (C) */ - tmp = tcg_temp_new(tcg_ctx); - tcg_gen_andi_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_DEST, CCF_C); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tmp, 0, l1); + tmp = tcg_ctx->QREG_CC_C; + tcond = (cond & 1 ? TCG_COND_NE : TCG_COND_EQ); break; case 6: /* NE (!Z) */ - tmp = tcg_temp_new(tcg_ctx); - tcg_gen_andi_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_DEST, CCF_Z); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_EQ, tmp, 0, l1); - break; case 7: /* EQ (Z) */ - tmp = tcg_temp_new(tcg_ctx); - tcg_gen_andi_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_DEST, CCF_Z); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tmp, 0, l1); + tmp = tcg_ctx->QREG_CC_Z; + tcond = (cond & 1 ? TCG_COND_EQ : TCG_COND_NE); break; case 8: /* VC (!V) */ - tmp = tcg_temp_new(tcg_ctx); - tcg_gen_andi_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_DEST, CCF_V); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_EQ, tmp, 0, l1); - break; case 9: /* VS (V) */ - tmp = tcg_temp_new(tcg_ctx); - tcg_gen_andi_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_DEST, CCF_V); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tmp, 0, l1); + tmp = tcg_ctx->QREG_CC_V; + tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE); break; case 10: /* PL (!N) */ - tmp = tcg_temp_new(tcg_ctx); - tcg_gen_andi_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_DEST, CCF_N); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_EQ, tmp, 0, l1); - break; case 11: /* MI (N) */ - tmp = tcg_temp_new(tcg_ctx); - tcg_gen_andi_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_DEST, CCF_N); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tmp, 0, l1); + tmp = tcg_ctx->QREG_CC_N; + tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE); break; case 12: /* GE (!(N ^ V)) */ - tmp = tcg_temp_new(tcg_ctx); - assert(CCF_V == (CCF_N >> 2)); - tcg_gen_shri_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_DEST, 2); - tcg_gen_xor_i32(tcg_ctx, tmp, tmp, tcg_ctx->QREG_CC_DEST); - tcg_gen_andi_i32(tcg_ctx, tmp, tmp, CCF_V); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_EQ, tmp, 0, l1); - break; case 13: /* LT (N ^ V) */ tmp = tcg_temp_new(tcg_ctx); - assert(CCF_V == (CCF_N >> 2)); - tcg_gen_shri_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_DEST, 2); - tcg_gen_xor_i32(tcg_ctx, tmp, tmp, tcg_ctx->QREG_CC_DEST); - tcg_gen_andi_i32(tcg_ctx, tmp, tmp, CCF_V); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tmp, 0, l1); + tcg_gen_xor_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_N, tcg_ctx->QREG_CC_V); + tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE); break; case 14: /* GT (!(Z || (N ^ V))) */ - tmp = tcg_temp_new(tcg_ctx); - assert(CCF_V == (CCF_N >> 2)); - tcg_gen_andi_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_DEST, CCF_N); - tcg_gen_shri_i32(tcg_ctx, tmp, tmp, 2); - tcg_gen_xor_i32(tcg_ctx, tmp, tmp, tcg_ctx->QREG_CC_DEST); - tcg_gen_andi_i32(tcg_ctx, tmp, tmp, CCF_V | CCF_Z); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_EQ, tmp, 0, l1); - break; case 15: /* LE (Z || (N ^ V)) */ tmp = tcg_temp_new(tcg_ctx); - assert(CCF_V == (CCF_N >> 2)); - tcg_gen_andi_i32(tcg_ctx, tmp, tcg_ctx->QREG_CC_DEST, CCF_N); - tcg_gen_shri_i32(tcg_ctx, tmp, tmp, 2); - tcg_gen_xor_i32(tcg_ctx, tmp, tmp, tcg_ctx->QREG_CC_DEST); - tcg_gen_andi_i32(tcg_ctx, tmp, tmp, CCF_V | CCF_Z); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tmp, 0, l1); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tmp, tcg_ctx->QREG_CC_Z, 0); + tcg_gen_neg_i32(tcg_ctx, tmp, tmp); + tmp2 = tcg_temp_new(tcg_ctx); + tcg_gen_xor_i32(tcg_ctx, tmp2, tcg_ctx->QREG_CC_N, tcg_ctx->QREG_CC_V); + tcg_gen_or_i32(tcg_ctx, tmp, tmp, tmp2); + tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE); break; default: /* Should ever happen. */ abort(); } + tcg_gen_brcondi_i32(tcg_ctx, tcond, tmp, 0, l1); } DISAS_INSN(scc) @@ -1028,6 +985,7 @@ DISAS_INSN(divw) tcg_gen_ext16u_i32(tcg_ctx, tmp, tcg_ctx->QREG_DIV1); tcg_gen_shli_i32(tcg_ctx, src, tcg_ctx->QREG_DIV2, 16); tcg_gen_or_i32(tcg_ctx, reg, tmp, src); + set_cc_op(s, CC_OP_FLAGS); } @@ -1127,42 +1085,43 @@ DISAS_INSN(bitop_reg) else opsize = OS_LONG; op = (insn >> 6) & 3; + + gen_flush_flags(s); + SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); src2 = DREG(insn, 9); dest = tcg_temp_new(tcg_ctx); - gen_flush_flags(s); tmp = tcg_temp_new(tcg_ctx); if (opsize == OS_BYTE) tcg_gen_andi_i32(tcg_ctx, tmp, src2, 7); else tcg_gen_andi_i32(tcg_ctx, tmp, src2, 31); - src2 = tmp; - tmp = tcg_temp_new(tcg_ctx); - tcg_gen_shr_i32(tcg_ctx, tmp, src1, src2); - tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 1); - tcg_gen_shli_i32(tcg_ctx, tmp, tmp, 2); - /* Clear CCF_Z if bit set. */ - tcg_gen_ori_i32(tcg_ctx, tcg_ctx->QREG_CC_DEST, tcg_ctx->QREG_CC_DEST, CCF_Z); - tcg_gen_xor_i32(tcg_ctx, tcg_ctx->QREG_CC_DEST, tcg_ctx->QREG_CC_DEST, tmp); - tcg_gen_shl_i32(tcg_ctx, tmp, tcg_const_i32(tcg_ctx, 1), src2); + src2 = tcg_const_i32(tcg_ctx, 1); + tcg_gen_shl_i32(tcg_ctx, src2, src2, tmp); + tcg_temp_free(tcg_ctx, tmp); + + tcg_gen_and_i32(tcg_ctx, tcg_ctx->QREG_CC_Z, src1, src2); + switch (op) { case 1: /* bchg */ - tcg_gen_xor_i32(tcg_ctx, dest, src1, tmp); + tcg_gen_xor_i32(tcg_ctx, dest, src1, src2); break; case 2: /* bclr */ - tcg_gen_not_i32(tcg_ctx, tmp, tmp); - tcg_gen_and_i32(tcg_ctx, dest, src1, tmp); + tcg_gen_andc_i32(tcg_ctx, dest, src1, src2); break; case 3: /* bset */ - tcg_gen_or_i32(tcg_ctx, dest, src1, tmp); + tcg_gen_or_i32(tcg_ctx, dest, src1, src2); break; default: /* btst */ break; } - if (op) + tcg_temp_free(tcg_ctx, src2); + if (op) { DEST_EA(env, insn, opsize, dest, &addr); + } + tcg_temp_free(tcg_ctx, dest); } DISAS_INSN(sats) @@ -1171,7 +1130,7 @@ DISAS_INSN(sats) TCGv reg; reg = DREG(insn, 0); gen_flush_flags(s); - gen_helper_sats(tcg_ctx, reg, reg, tcg_ctx->QREG_CC_DEST); + gen_helper_sats(tcg_ctx, reg, reg, tcg_ctx->QREG_CC_V); gen_logic_cc(s, reg, OS_LONG); } @@ -1246,28 +1205,20 @@ DISAS_INSN(bitop_im) return; } + gen_flush_flags(s); + SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); - gen_flush_flags(s); if (opsize == OS_BYTE) bitnum &= 7; else bitnum &= 31; mask = 1 << bitnum; - tmp = tcg_temp_new(tcg_ctx); - assert (CCF_Z == (1 << 2)); - if (bitnum > 2) - tcg_gen_shri_i32(tcg_ctx, tmp, src1, bitnum - 2); - else if (bitnum < 2) - tcg_gen_shli_i32(tcg_ctx, tmp, src1, 2 - bitnum); - else - tcg_gen_mov_i32(tcg_ctx, tmp, src1); - tcg_gen_andi_i32(tcg_ctx, tmp, tmp, CCF_Z); - /* Clear CCF_Z if bit set. */ - tcg_gen_ori_i32(tcg_ctx, tcg_ctx->QREG_CC_DEST, tcg_ctx->QREG_CC_DEST, CCF_Z); - tcg_gen_xor_i32(tcg_ctx, tcg_ctx->QREG_CC_DEST, tcg_ctx->QREG_CC_DEST, tmp); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->QREG_CC_Z, src1, mask); + if (op) { + tmp = tcg_temp_new(tcg_ctx); switch (op) { case 1: /* bchg */ tcg_gen_xori_i32(tcg_ctx, tmp, src1, mask); @@ -1282,8 +1233,10 @@ DISAS_INSN(bitop_im) break; } DEST_EA(env, insn, opsize, tmp, &addr); + tcg_temp_free(tcg_ctx, tmp); } } + DISAS_INSN(arith_im) { TCGContext *tcg_ctx = s->uc->tcg_ctx; @@ -1308,7 +1261,7 @@ DISAS_INSN(arith_im) break; case 2: /* subi */ tcg_gen_mov_i32(tcg_ctx, dest, src1); - tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, tcg_const_i32(tcg_ctx, im)); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, im); tcg_gen_subi_i32(tcg_ctx, dest, dest, im); gen_update_cc_add(s, dest, tcg_const_i32(tcg_ctx, im)); set_cc_op(s, CC_OP_SUB); @@ -1317,7 +1270,7 @@ DISAS_INSN(arith_im) tcg_gen_mov_i32(tcg_ctx, dest, src1); tcg_gen_addi_i32(tcg_ctx, dest, dest, im); gen_update_cc_add(s, dest, tcg_const_i32(tcg_ctx, im)); - tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, tcg_const_i32(tcg_ctx, im)); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, im); set_cc_op(s, CC_OP_ADD); break; case 5: /* eori */ @@ -1325,10 +1278,8 @@ DISAS_INSN(arith_im) gen_logic_cc(s, dest, OS_LONG); break; case 6: /* cmpi */ - tcg_gen_mov_i32(tcg_ctx, dest, src1); - tcg_gen_subi_i32(tcg_ctx, dest, dest, im); - gen_update_cc_add(s, dest, tcg_const_i32(tcg_ctx, im)); - set_cc_op(s, CC_OP_SUB); + gen_update_cc_add(s, src1, tcg_const_i32(tcg_ctx, im)); + set_cc_op(s, CC_OP_CMP); break; default: abort(); @@ -1426,9 +1377,9 @@ static TCGv gen_get_ccr(DisasContext *s) TCGv dest; gen_flush_flags(s); + update_cc_op(s); dest = tcg_temp_new(tcg_ctx); - tcg_gen_shli_i32(tcg_ctx, dest, tcg_ctx->QREG_CC_X, 4); - tcg_gen_or_i32(tcg_ctx, dest, dest, tcg_ctx->QREG_CC_DEST); + gen_helper_get_ccr(tcg_ctx, dest, tcg_ctx->cpu_env); return dest; } @@ -1452,47 +1403,48 @@ DISAS_INSN(neg) tcg_gen_mov_i32(tcg_ctx, src1, reg); tcg_gen_neg_i32(tcg_ctx, reg, src1); gen_update_cc_add(s, reg, src1); - tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, tcg_const_i32(tcg_ctx, 0), src1); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->QREG_CC_X, src1, 0); set_cc_op(s, CC_OP_SUB); } static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_DEST, val & 0xf); - tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_X, (val & 0x10) >> 4); - if (!ccr_only) { - gen_helper_set_sr(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, val & 0xff00)); + if (ccr_only) { + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_C, val & CCF_C ? 1 : 0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_V, val & CCF_V ? -1 : 0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_Z, val & CCF_Z ? 0 : 1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_N, val & CCF_N ? -1 : 0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_X, val & CCF_X ? 1 : 0); + } else { + gen_helper_set_sr(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, val)); } set_cc_op(s, CC_OP_FLAGS); } -static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only) +static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, + int ccr_only) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - TCGv tmp; - tmp = tcg_temp_new(tcg_ctx); - tcg_gen_andi_i32(tcg_ctx, tcg_ctx->QREG_CC_DEST, val, 0xf); - tcg_gen_shri_i32(tcg_ctx, tmp, val, 4); - tcg_gen_andi_i32(tcg_ctx, tcg_ctx->QREG_CC_X, tmp, 1); - if (!ccr_only) { - gen_helper_set_sr(tcg_ctx, tcg_ctx->cpu_env, val); + if ((insn & 0x38) == 0) { + if (ccr_only) { + gen_helper_set_ccr(tcg_ctx, tcg_ctx->cpu_env, DREG(insn, 0)); + } else { + gen_helper_set_sr(tcg_ctx, tcg_ctx->cpu_env, DREG(insn, 0)); + } + set_cc_op(s, CC_OP_FLAGS); + } else if ((insn & 0x3f) == 0x3c) { + uint16_t val; + val = read_im16(env, s); + gen_set_sr_im(s, val, ccr_only); + } else { + disas_undef(env, s, insn); } } -static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, - int ccr_only) -{ - TCGv src; - TCGContext *tcg_ctx = s->uc->tcg_ctx; - s->cc_op = CC_OP_FLAGS; - SRC_EA(env, src, OS_WORD, 0, NULL); - gen_set_sr(s, src, ccr_only); -} - DISAS_INSN(move_to_ccr) { - gen_move_to_sr(env, s, insn, 1); + gen_set_sr(env, s, insn, 1); } DISAS_INSN(not) @@ -1708,10 +1660,10 @@ DISAS_INSN(addsubq) src2 = tcg_const_i32(tcg_ctx, val); if (insn & 0x0100) { tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, src2); - tcg_gen_subi_i32(tcg_ctx, dest, dest, val); + tcg_gen_sub_i32(tcg_ctx, dest, dest, src2); set_cc_op(s, CC_OP_SUB); } else { - tcg_gen_addi_i32(tcg_ctx, dest, dest, val); + tcg_gen_add_i32(tcg_ctx, dest, dest, src2); tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, src2); set_cc_op(s, CC_OP_ADD); } @@ -1756,18 +1708,16 @@ DISAS_INSN(branch) /* bsr */ gen_push(s, tcg_const_i32(tcg_ctx, s->pc)); } + update_cc_op(s); if (op > 1) { /* Bcc */ l1 = gen_new_label(tcg_ctx); gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); - update_cc_op(s); gen_jmp_tb(s, 1, base + offset); gen_set_label(tcg_ctx, l1); - update_cc_op(s); gen_jmp_tb(s, 0, s->pc); } else { /* Unconditional branch. */ - update_cc_op(s); gen_jmp_tb(s, 0, base + offset); } } @@ -1863,16 +1813,13 @@ DISAS_INSN(cmp) TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv src; TCGv reg; - TCGv dest; int opsize; opsize = insn_opsize(insn); SRC_EA(env, src, opsize, -1, NULL); reg = DREG(insn, 9); - dest = tcg_temp_new(tcg_ctx); - tcg_gen_sub_i32(tcg_ctx, dest, reg, src); - gen_update_cc_add(s, dest, src); - SET_CC_OP(opsize, SUB); + gen_update_cc_add(s, reg, src); + set_cc_op(s, CC_OP_CMP); } DISAS_INSN(cmpa) @@ -1881,7 +1828,6 @@ DISAS_INSN(cmpa) int opsize; TCGv src; TCGv reg; - TCGv dest; if (insn & 0x100) { opsize = OS_LONG; @@ -1890,10 +1836,8 @@ DISAS_INSN(cmpa) } SRC_EA(env, src, opsize, 1, NULL); reg = AREG(insn, 9); - dest = tcg_temp_new(tcg_ctx); - tcg_gen_sub_i32(tcg_ctx, dest, reg, src); - gen_update_cc_add(s, dest, src); - SET_CC_OP(OS_LONG, SUB); + gen_update_cc_add(s, reg, src); + set_cc_op(s, CC_OP_CMP); } DISAS_INSN(eor) @@ -1965,6 +1909,8 @@ DISAS_INSN(shift_im) int tmp; TCGv shift; + set_cc_op(s, CC_OP_FLAGS); + reg = DREG(insn, 0); tmp = (insn >> 9) & 7; if (tmp == 0) @@ -1980,7 +1926,6 @@ DISAS_INSN(shift_im) gen_helper_sar_cc(tcg_ctx, reg, tcg_ctx->cpu_env, reg, shift); } } - set_cc_op(s, CC_OP_SHIFT); } DISAS_INSN(shift_reg) @@ -1991,8 +1936,6 @@ DISAS_INSN(shift_reg) reg = DREG(insn, 0); shift = DREG(insn, 9); - /* Shift by zero leaves C flag unmodified. */ - gen_flush_flags(s); if (insn & 0x100) { gen_helper_shl_cc(tcg_ctx, reg, tcg_ctx->cpu_env, reg, shift); } else { @@ -2002,7 +1945,7 @@ DISAS_INSN(shift_reg) gen_helper_sar_cc(tcg_ctx, reg, tcg_ctx->cpu_env, reg, shift); } } - set_cc_op(s, CC_OP_SHIFT); + set_cc_op(s, CC_OP_FLAGS); } DISAS_INSN(ff1) @@ -2066,7 +2009,7 @@ DISAS_INSN(move_to_sr) gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); return; } - gen_move_to_sr(env, s, insn, 0); + gen_set_sr(env, s, insn, 0); gen_lookup_tb(s); } @@ -2834,8 +2777,10 @@ DISAS_INSN(from_mext) DISAS_INSN(macsr_to_ccr) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_X, 0); - tcg_gen_andi_i32(tcg_ctx, tcg_ctx->QREG_CC_DEST, tcg_ctx->QREG_MACSR, 0xf); + TCGv tmp = tcg_temp_new(tcg_ctx); + tcg_gen_andi_i32(tcg_ctx, tmp, tcg_ctx->QREG_MACSR, 0xf); + gen_helper_set_sr(tcg_ctx, tcg_ctx->cpu_env, tmp); + tcg_temp_free(tcg_ctx, tmp); set_cc_op(s, CC_OP_FLAGS); } @@ -3141,6 +3086,7 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) dc->is_jmp = DISAS_NEXT; dc->pc = pc_start; dc->cc_op = CC_OP_DYNAMIC; + dc->cc_op_synced = 1; dc->singlestep_enabled = cs->singlestep_enabled; dc->fpcr = env->fpcr; dc->user = (env->sr & SR_S) == 0; diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h index b69412a3..b3867bec 100644 --- a/qemu/tcg/tcg.h +++ b/qemu/tcg/tcg.h @@ -891,9 +891,11 @@ struct TCGContext { TCGv QREG_PC; TCGv QREG_SR; TCGv QREG_CC_OP; - TCGv QREG_CC_DEST; - TCGv QREG_CC_SRC; TCGv QREG_CC_X; + TCGv QREG_CC_C; + TCGv QREG_CC_N; + TCGv QREG_CC_V; + TCGv QREG_CC_Z; TCGv QREG_DIV1; TCGv QREG_DIV2; TCGv QREG_MACSR;