diff --git a/qemu/Makefile.target b/qemu/Makefile.target index 82c6e466..b9c1a3d1 100644 --- a/qemu/Makefile.target +++ b/qemu/Makefile.target @@ -41,7 +41,7 @@ all: $(PROGS) ######################################################### # cpu emulator library obj-y = exec.o translate-all.o cpu-exec.o -obj-y += tcg/tcg.o tcg/optimize.o +obj-y += tcg/tcg.o tcg/tcg-op.o tcg/optimize.o obj-y += fpu/softfloat.o obj-y += target-$(TARGET_BASE_ARCH)/ diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 470a62d4..5f7ec8c4 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -2690,11 +2690,13 @@ #define tcg_func_start tcg_func_start_aarch64 #define tcg_gen_abs_i32 tcg_gen_abs_i32_aarch64 #define tcg_gen_add2_i32 tcg_gen_add2_i32_aarch64 +#define tcg_gen_add2_i64 tcg_gen_add2_i64_aarch64 #define tcg_gen_add_i32 tcg_gen_add_i32_aarch64 #define tcg_gen_add_i64 tcg_gen_add_i64_aarch64 #define tcg_gen_addi_i32 tcg_gen_addi_i32_aarch64 #define tcg_gen_addi_i64 tcg_gen_addi_i64_aarch64 #define tcg_gen_andc_i32 tcg_gen_andc_i32_aarch64 +#define tcg_gen_andc_i64 tcg_gen_andc_i64_aarch64 #define tcg_gen_and_i32 tcg_gen_and_i32_aarch64 #define tcg_gen_and_i64 tcg_gen_and_i64_aarch64 #define tcg_gen_andi_i32 tcg_gen_andi_i32_aarch64 @@ -2703,8 +2705,12 @@ #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_aarch64 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_aarch64 #define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_aarch64 +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_aarch64 #define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_aarch64 +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_aarch64 #define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_aarch64 +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_aarch64 +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_aarch64 #define tcg_gen_callN tcg_gen_callN_aarch64 #define tcg_gen_code tcg_gen_code_aarch64 #define tcg_gen_code_common tcg_gen_code_common_aarch64 @@ -2712,16 +2718,36 @@ #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_aarch64 #define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_aarch64 #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_aarch64 +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_aarch64 +#define tcg_gen_discard_i64 tcg_gen_discard_i64_aarch64 +#define tcg_gen_div_i32 tcg_gen_div_i32_aarch64 +#define tcg_gen_div_i64 tcg_gen_div_i64_aarch64 +#define tcg_gen_divu_i32 tcg_gen_divu_i32_aarch64 +#define tcg_gen_divu_i64 tcg_gen_divu_i64_aarch64 +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_aarch64 +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_aarch64 #define tcg_gen_exit_tb tcg_gen_exit_tb_aarch64 #define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_aarch64 +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_aarch64 #define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_aarch64 +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_aarch64 #define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_aarch64 #define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_aarch64 #define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_aarch64 +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_aarch64 #define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_aarch64 +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_aarch64 #define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_aarch64 +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_aarch64 +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_aarch64 #define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64 #define tcg_gen_goto_tb tcg_gen_goto_tb_aarch64 +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_aarch64 +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_aarch64 +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_aarch64 +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_aarch64 +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_aarch64 +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_aarch64 #define tcg_gen_ld_i32 tcg_gen_ld_i32_aarch64 #define tcg_gen_ld_i64 tcg_gen_ld_i64_aarch64 #define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_aarch64 @@ -2733,12 +2759,28 @@ #define tcg_gen_movi_i32 tcg_gen_movi_i32_aarch64 #define tcg_gen_movi_i64 tcg_gen_movi_i64_aarch64 #define tcg_gen_mul_i32 tcg_gen_mul_i32_aarch64 +#define tcg_gen_mul_i64 tcg_gen_mul_i64_aarch64 +#define tcg_gen_muli_i32 tcg_gen_muli_i32_aarch64 +#define tcg_gen_muli_i64 tcg_gen_muli_i64_aarch64 #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_aarch64 +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_aarch64 #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_aarch64 +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_aarch64 +#define tcg_gen_nand_i32 tcg_gen_nand_i32_aarch64 +#define tcg_gen_nand_i64 tcg_gen_nand_i64_aarch64 #define tcg_gen_neg_i32 tcg_gen_neg_i32_aarch64 #define tcg_gen_neg_i64 tcg_gen_neg_i64_aarch64 +#define tcg_gen_nor_i32 tcg_gen_nor_i32_aarch64 +#define tcg_gen_nor_i64 tcg_gen_nor_i64_aarch64 #define tcg_gen_not_i32 tcg_gen_not_i32_aarch64 +#define tcg_gen_not_i64 tcg_gen_not_i64_aarch64 #define tcg_gen_op0 tcg_gen_op0_aarch64 +#define tcg_gen_op1 tcg_gen_op1_aarch64 +#define tcg_gen_op2 tcg_gen_op2_aarch64 +#define tcg_gen_op3 tcg_gen_op3_aarch64 +#define tcg_gen_op4 tcg_gen_op4_aarch64 +#define tcg_gen_op5 tcg_gen_op5_aarch64 +#define tcg_gen_op6 tcg_gen_op6_aarch64 #define tcg_gen_op1i tcg_gen_op1i_aarch64 #define tcg_gen_op2_i32 tcg_gen_op2_i32_aarch64 #define tcg_gen_op2_i64 tcg_gen_op2_i64_aarch64 @@ -2755,20 +2797,35 @@ #define tcg_gen_op6i_i32 tcg_gen_op6i_i32_aarch64 #define tcg_gen_op6i_i64 tcg_gen_op6i_i64_aarch64 #define tcg_gen_orc_i32 tcg_gen_orc_i32_aarch64 +#define tcg_gen_orc_i64 tcg_gen_orc_i64_aarch64 #define tcg_gen_or_i32 tcg_gen_or_i32_aarch64 #define tcg_gen_or_i64 tcg_gen_or_i64_aarch64 #define tcg_gen_ori_i32 tcg_gen_ori_i32_aarch64 +#define tcg_gen_ori_i64 tcg_gen_ori_i64_aarch64 #define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_aarch64 #define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_aarch64 #define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_aarch64 #define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_aarch64 +#define tcg_gen_rem_i32 tcg_gen_rem_i32_aarch64 +#define tcg_gen_rem_i64 tcg_gen_rem_i64_aarch64 +#define tcg_gen_remu_i32 tcg_gen_remu_i32_aarch64 +#define tcg_gen_remu_i64 tcg_gen_remu_i64_aarch64 #define tcg_gen_rotl_i32 tcg_gen_rotl_i32_aarch64 +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_aarch64 #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_aarch64 +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_aarch64 #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_aarch64 +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_aarch64 #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_aarch64 +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_aarch64 #define tcg_gen_sar_i32 tcg_gen_sar_i32_aarch64 +#define tcg_gen_sar_i64 tcg_gen_sar_i64_aarch64 #define tcg_gen_sari_i32 tcg_gen_sari_i32_aarch64 +#define tcg_gen_sari_i64 tcg_gen_sari_i64_aarch64 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_aarch64 +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_aarch64 +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_aarch64 +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_aarch64 #define tcg_gen_shl_i32 tcg_gen_shl_i32_aarch64 #define tcg_gen_shl_i64 tcg_gen_shl_i64_aarch64 #define tcg_gen_shli_i32 tcg_gen_shli_i32_aarch64 @@ -2780,14 +2837,20 @@ #define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64 #define tcg_gen_st_i32 tcg_gen_st_i32_aarch64 #define tcg_gen_st_i64 tcg_gen_st_i64_aarch64 +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_aarch64 +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_aarch64 #define tcg_gen_sub_i32 tcg_gen_sub_i32_aarch64 #define tcg_gen_sub_i64 tcg_gen_sub_i64_aarch64 +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_aarch64 +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64 #define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64 +#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64 #define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_aarch64 #define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_aarch64 #define tcg_gen_xor_i32 tcg_gen_xor_i32_aarch64 #define tcg_gen_xor_i64 tcg_gen_xor_i64_aarch64 #define tcg_gen_xori_i32 tcg_gen_xori_i32_aarch64 +#define tcg_gen_xori_i64 tcg_gen_xori_i64_aarch64 #define tcg_get_arg_str_i32 tcg_get_arg_str_i32_aarch64 #define tcg_get_arg_str_i64 tcg_get_arg_str_i64_aarch64 #define tcg_get_arg_str_idx tcg_get_arg_str_idx_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index fbdb37a7..482d9323 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -2690,11 +2690,13 @@ #define tcg_func_start tcg_func_start_aarch64eb #define tcg_gen_abs_i32 tcg_gen_abs_i32_aarch64eb #define tcg_gen_add2_i32 tcg_gen_add2_i32_aarch64eb +#define tcg_gen_add2_i64 tcg_gen_add2_i64_aarch64eb #define tcg_gen_add_i32 tcg_gen_add_i32_aarch64eb #define tcg_gen_add_i64 tcg_gen_add_i64_aarch64eb #define tcg_gen_addi_i32 tcg_gen_addi_i32_aarch64eb #define tcg_gen_addi_i64 tcg_gen_addi_i64_aarch64eb #define tcg_gen_andc_i32 tcg_gen_andc_i32_aarch64eb +#define tcg_gen_andc_i64 tcg_gen_andc_i64_aarch64eb #define tcg_gen_and_i32 tcg_gen_and_i32_aarch64eb #define tcg_gen_and_i64 tcg_gen_and_i64_aarch64eb #define tcg_gen_andi_i32 tcg_gen_andi_i32_aarch64eb @@ -2703,8 +2705,12 @@ #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_aarch64eb #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_aarch64eb #define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_aarch64eb +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_aarch64eb #define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_aarch64eb +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_aarch64eb #define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_aarch64eb +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_aarch64eb +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_aarch64eb #define tcg_gen_callN tcg_gen_callN_aarch64eb #define tcg_gen_code tcg_gen_code_aarch64eb #define tcg_gen_code_common tcg_gen_code_common_aarch64eb @@ -2712,16 +2718,36 @@ #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_aarch64eb #define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_aarch64eb #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_aarch64eb +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_aarch64eb +#define tcg_gen_discard_i64 tcg_gen_discard_i64_aarch64eb +#define tcg_gen_div_i32 tcg_gen_div_i32_aarch64eb +#define tcg_gen_div_i64 tcg_gen_div_i64_aarch64eb +#define tcg_gen_divu_i32 tcg_gen_divu_i32_aarch64eb +#define tcg_gen_divu_i64 tcg_gen_divu_i64_aarch64eb +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_aarch64eb +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_aarch64eb #define tcg_gen_exit_tb tcg_gen_exit_tb_aarch64eb #define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_aarch64eb +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_aarch64eb #define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_aarch64eb +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_aarch64eb #define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_aarch64eb #define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_aarch64eb #define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_aarch64eb +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_aarch64eb #define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_aarch64eb +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_aarch64eb #define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_aarch64eb +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_aarch64eb +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_aarch64eb #define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64eb #define tcg_gen_goto_tb tcg_gen_goto_tb_aarch64eb +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_aarch64eb +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_aarch64eb +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_aarch64eb +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_aarch64eb +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_aarch64eb +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_aarch64eb #define tcg_gen_ld_i32 tcg_gen_ld_i32_aarch64eb #define tcg_gen_ld_i64 tcg_gen_ld_i64_aarch64eb #define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_aarch64eb @@ -2733,12 +2759,28 @@ #define tcg_gen_movi_i32 tcg_gen_movi_i32_aarch64eb #define tcg_gen_movi_i64 tcg_gen_movi_i64_aarch64eb #define tcg_gen_mul_i32 tcg_gen_mul_i32_aarch64eb +#define tcg_gen_mul_i64 tcg_gen_mul_i64_aarch64eb +#define tcg_gen_muli_i32 tcg_gen_muli_i32_aarch64eb +#define tcg_gen_muli_i64 tcg_gen_muli_i64_aarch64eb #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_aarch64eb +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_aarch64eb #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_aarch64eb +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_aarch64eb +#define tcg_gen_nand_i32 tcg_gen_nand_i32_aarch64eb +#define tcg_gen_nand_i64 tcg_gen_nand_i64_aarch64eb #define tcg_gen_neg_i32 tcg_gen_neg_i32_aarch64eb #define tcg_gen_neg_i64 tcg_gen_neg_i64_aarch64eb +#define tcg_gen_nor_i32 tcg_gen_nor_i32_aarch64eb +#define tcg_gen_nor_i64 tcg_gen_nor_i64_aarch64eb #define tcg_gen_not_i32 tcg_gen_not_i32_aarch64eb +#define tcg_gen_not_i64 tcg_gen_not_i64_aarch64eb #define tcg_gen_op0 tcg_gen_op0_aarch64eb +#define tcg_gen_op1 tcg_gen_op1_aarch64eb +#define tcg_gen_op2 tcg_gen_op2_aarch64eb +#define tcg_gen_op3 tcg_gen_op3_aarch64eb +#define tcg_gen_op4 tcg_gen_op4_aarch64eb +#define tcg_gen_op5 tcg_gen_op5_aarch64eb +#define tcg_gen_op6 tcg_gen_op6_aarch64eb #define tcg_gen_op1i tcg_gen_op1i_aarch64eb #define tcg_gen_op2_i32 tcg_gen_op2_i32_aarch64eb #define tcg_gen_op2_i64 tcg_gen_op2_i64_aarch64eb @@ -2755,20 +2797,35 @@ #define tcg_gen_op6i_i32 tcg_gen_op6i_i32_aarch64eb #define tcg_gen_op6i_i64 tcg_gen_op6i_i64_aarch64eb #define tcg_gen_orc_i32 tcg_gen_orc_i32_aarch64eb +#define tcg_gen_orc_i64 tcg_gen_orc_i64_aarch64eb #define tcg_gen_or_i32 tcg_gen_or_i32_aarch64eb #define tcg_gen_or_i64 tcg_gen_or_i64_aarch64eb #define tcg_gen_ori_i32 tcg_gen_ori_i32_aarch64eb +#define tcg_gen_ori_i64 tcg_gen_ori_i64_aarch64eb #define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_aarch64eb #define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_aarch64eb #define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_aarch64eb #define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_aarch64eb +#define tcg_gen_rem_i32 tcg_gen_rem_i32_aarch64eb +#define tcg_gen_rem_i64 tcg_gen_rem_i64_aarch64eb +#define tcg_gen_remu_i32 tcg_gen_remu_i32_aarch64eb +#define tcg_gen_remu_i64 tcg_gen_remu_i64_aarch64eb #define tcg_gen_rotl_i32 tcg_gen_rotl_i32_aarch64eb +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_aarch64eb #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_aarch64eb +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_aarch64eb #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_aarch64eb +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_aarch64eb #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_aarch64eb +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_aarch64eb #define tcg_gen_sar_i32 tcg_gen_sar_i32_aarch64eb +#define tcg_gen_sar_i64 tcg_gen_sar_i64_aarch64eb #define tcg_gen_sari_i32 tcg_gen_sari_i32_aarch64eb +#define tcg_gen_sari_i64 tcg_gen_sari_i64_aarch64eb #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_aarch64eb +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_aarch64eb +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_aarch64eb +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_aarch64eb #define tcg_gen_shl_i32 tcg_gen_shl_i32_aarch64eb #define tcg_gen_shl_i64 tcg_gen_shl_i64_aarch64eb #define tcg_gen_shli_i32 tcg_gen_shli_i32_aarch64eb @@ -2780,14 +2837,20 @@ #define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64eb #define tcg_gen_st_i32 tcg_gen_st_i32_aarch64eb #define tcg_gen_st_i64 tcg_gen_st_i64_aarch64eb +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_aarch64eb +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_aarch64eb #define tcg_gen_sub_i32 tcg_gen_sub_i32_aarch64eb #define tcg_gen_sub_i64 tcg_gen_sub_i64_aarch64eb +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_aarch64eb +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64eb #define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64eb +#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64eb #define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_aarch64eb #define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_aarch64eb #define tcg_gen_xor_i32 tcg_gen_xor_i32_aarch64eb #define tcg_gen_xor_i64 tcg_gen_xor_i64_aarch64eb #define tcg_gen_xori_i32 tcg_gen_xori_i32_aarch64eb +#define tcg_gen_xori_i64 tcg_gen_xori_i64_aarch64eb #define tcg_get_arg_str_i32 tcg_get_arg_str_i32_aarch64eb #define tcg_get_arg_str_i64 tcg_get_arg_str_i64_aarch64eb #define tcg_get_arg_str_idx tcg_get_arg_str_idx_aarch64eb diff --git a/qemu/arm.h b/qemu/arm.h index 87d02032..005d8842 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -2690,11 +2690,13 @@ #define tcg_func_start tcg_func_start_arm #define tcg_gen_abs_i32 tcg_gen_abs_i32_arm #define tcg_gen_add2_i32 tcg_gen_add2_i32_arm +#define tcg_gen_add2_i64 tcg_gen_add2_i64_arm #define tcg_gen_add_i32 tcg_gen_add_i32_arm #define tcg_gen_add_i64 tcg_gen_add_i64_arm #define tcg_gen_addi_i32 tcg_gen_addi_i32_arm #define tcg_gen_addi_i64 tcg_gen_addi_i64_arm #define tcg_gen_andc_i32 tcg_gen_andc_i32_arm +#define tcg_gen_andc_i64 tcg_gen_andc_i64_arm #define tcg_gen_and_i32 tcg_gen_and_i32_arm #define tcg_gen_and_i64 tcg_gen_and_i64_arm #define tcg_gen_andi_i32 tcg_gen_andi_i32_arm @@ -2703,8 +2705,12 @@ #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_arm #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_arm #define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_arm +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_arm #define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_arm +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_arm #define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_arm +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_arm +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_arm #define tcg_gen_callN tcg_gen_callN_arm #define tcg_gen_code tcg_gen_code_arm #define tcg_gen_code_common tcg_gen_code_common_arm @@ -2712,16 +2718,36 @@ #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_arm #define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_arm #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_arm +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_arm +#define tcg_gen_discard_i64 tcg_gen_discard_i64_arm +#define tcg_gen_div_i32 tcg_gen_div_i32_arm +#define tcg_gen_div_i64 tcg_gen_div_i64_arm +#define tcg_gen_divu_i32 tcg_gen_divu_i32_arm +#define tcg_gen_divu_i64 tcg_gen_divu_i64_arm +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_arm +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_arm #define tcg_gen_exit_tb tcg_gen_exit_tb_arm #define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_arm +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_arm #define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_arm +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_arm #define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_arm #define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_arm #define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_arm +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_arm #define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_arm +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_arm #define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_arm +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_arm +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_arm #define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_arm #define tcg_gen_goto_tb tcg_gen_goto_tb_arm +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_arm +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_arm +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_arm +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_arm +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_arm +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_arm #define tcg_gen_ld_i32 tcg_gen_ld_i32_arm #define tcg_gen_ld_i64 tcg_gen_ld_i64_arm #define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_arm @@ -2733,12 +2759,28 @@ #define tcg_gen_movi_i32 tcg_gen_movi_i32_arm #define tcg_gen_movi_i64 tcg_gen_movi_i64_arm #define tcg_gen_mul_i32 tcg_gen_mul_i32_arm +#define tcg_gen_mul_i64 tcg_gen_mul_i64_arm +#define tcg_gen_muli_i32 tcg_gen_muli_i32_arm +#define tcg_gen_muli_i64 tcg_gen_muli_i64_arm #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_arm +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_arm #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_arm +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_arm +#define tcg_gen_nand_i32 tcg_gen_nand_i32_arm +#define tcg_gen_nand_i64 tcg_gen_nand_i64_arm #define tcg_gen_neg_i32 tcg_gen_neg_i32_arm #define tcg_gen_neg_i64 tcg_gen_neg_i64_arm +#define tcg_gen_nor_i32 tcg_gen_nor_i32_arm +#define tcg_gen_nor_i64 tcg_gen_nor_i64_arm #define tcg_gen_not_i32 tcg_gen_not_i32_arm +#define tcg_gen_not_i64 tcg_gen_not_i64_arm #define tcg_gen_op0 tcg_gen_op0_arm +#define tcg_gen_op1 tcg_gen_op1_arm +#define tcg_gen_op2 tcg_gen_op2_arm +#define tcg_gen_op3 tcg_gen_op3_arm +#define tcg_gen_op4 tcg_gen_op4_arm +#define tcg_gen_op5 tcg_gen_op5_arm +#define tcg_gen_op6 tcg_gen_op6_arm #define tcg_gen_op1i tcg_gen_op1i_arm #define tcg_gen_op2_i32 tcg_gen_op2_i32_arm #define tcg_gen_op2_i64 tcg_gen_op2_i64_arm @@ -2755,20 +2797,35 @@ #define tcg_gen_op6i_i32 tcg_gen_op6i_i32_arm #define tcg_gen_op6i_i64 tcg_gen_op6i_i64_arm #define tcg_gen_orc_i32 tcg_gen_orc_i32_arm +#define tcg_gen_orc_i64 tcg_gen_orc_i64_arm #define tcg_gen_or_i32 tcg_gen_or_i32_arm #define tcg_gen_or_i64 tcg_gen_or_i64_arm #define tcg_gen_ori_i32 tcg_gen_ori_i32_arm +#define tcg_gen_ori_i64 tcg_gen_ori_i64_arm #define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_arm #define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_arm #define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_arm #define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_arm +#define tcg_gen_rem_i32 tcg_gen_rem_i32_arm +#define tcg_gen_rem_i64 tcg_gen_rem_i64_arm +#define tcg_gen_remu_i32 tcg_gen_remu_i32_arm +#define tcg_gen_remu_i64 tcg_gen_remu_i64_arm #define tcg_gen_rotl_i32 tcg_gen_rotl_i32_arm +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_arm #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_arm +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_arm #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_arm +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_arm #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_arm +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_arm #define tcg_gen_sar_i32 tcg_gen_sar_i32_arm +#define tcg_gen_sar_i64 tcg_gen_sar_i64_arm #define tcg_gen_sari_i32 tcg_gen_sari_i32_arm +#define tcg_gen_sari_i64 tcg_gen_sari_i64_arm #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_arm +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_arm +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_arm +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_arm #define tcg_gen_shl_i32 tcg_gen_shl_i32_arm #define tcg_gen_shl_i64 tcg_gen_shl_i64_arm #define tcg_gen_shli_i32 tcg_gen_shli_i32_arm @@ -2780,14 +2837,20 @@ #define tcg_gen_shri_i64 tcg_gen_shri_i64_arm #define tcg_gen_st_i32 tcg_gen_st_i32_arm #define tcg_gen_st_i64 tcg_gen_st_i64_arm +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_arm +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_arm #define tcg_gen_sub_i32 tcg_gen_sub_i32_arm #define tcg_gen_sub_i64 tcg_gen_sub_i64_arm +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_arm +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_arm #define tcg_gen_subi_i32 tcg_gen_subi_i32_arm +#define tcg_gen_subi_i64 tcg_gen_subi_i64_arm #define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_arm #define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_arm #define tcg_gen_xor_i32 tcg_gen_xor_i32_arm #define tcg_gen_xor_i64 tcg_gen_xor_i64_arm #define tcg_gen_xori_i32 tcg_gen_xori_i32_arm +#define tcg_gen_xori_i64 tcg_gen_xori_i64_arm #define tcg_get_arg_str_i32 tcg_get_arg_str_i32_arm #define tcg_get_arg_str_i64 tcg_get_arg_str_i64_arm #define tcg_get_arg_str_idx tcg_get_arg_str_idx_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index 30b771b5..7516015c 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -2690,11 +2690,13 @@ #define tcg_func_start tcg_func_start_armeb #define tcg_gen_abs_i32 tcg_gen_abs_i32_armeb #define tcg_gen_add2_i32 tcg_gen_add2_i32_armeb +#define tcg_gen_add2_i64 tcg_gen_add2_i64_armeb #define tcg_gen_add_i32 tcg_gen_add_i32_armeb #define tcg_gen_add_i64 tcg_gen_add_i64_armeb #define tcg_gen_addi_i32 tcg_gen_addi_i32_armeb #define tcg_gen_addi_i64 tcg_gen_addi_i64_armeb #define tcg_gen_andc_i32 tcg_gen_andc_i32_armeb +#define tcg_gen_andc_i64 tcg_gen_andc_i64_armeb #define tcg_gen_and_i32 tcg_gen_and_i32_armeb #define tcg_gen_and_i64 tcg_gen_and_i64_armeb #define tcg_gen_andi_i32 tcg_gen_andi_i32_armeb @@ -2703,8 +2705,12 @@ #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_armeb #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_armeb #define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_armeb +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_armeb #define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_armeb +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_armeb #define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_armeb +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_armeb +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_armeb #define tcg_gen_callN tcg_gen_callN_armeb #define tcg_gen_code tcg_gen_code_armeb #define tcg_gen_code_common tcg_gen_code_common_armeb @@ -2712,16 +2718,36 @@ #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_armeb #define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_armeb #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_armeb +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_armeb +#define tcg_gen_discard_i64 tcg_gen_discard_i64_armeb +#define tcg_gen_div_i32 tcg_gen_div_i32_armeb +#define tcg_gen_div_i64 tcg_gen_div_i64_armeb +#define tcg_gen_divu_i32 tcg_gen_divu_i32_armeb +#define tcg_gen_divu_i64 tcg_gen_divu_i64_armeb +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_armeb +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_armeb #define tcg_gen_exit_tb tcg_gen_exit_tb_armeb #define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_armeb +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_armeb #define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_armeb +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_armeb #define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_armeb #define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_armeb #define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_armeb +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_armeb #define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_armeb +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_armeb #define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_armeb +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_armeb +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_armeb #define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_armeb #define tcg_gen_goto_tb tcg_gen_goto_tb_armeb +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_armeb +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_armeb +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_armeb +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_armeb +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_armeb +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_armeb #define tcg_gen_ld_i32 tcg_gen_ld_i32_armeb #define tcg_gen_ld_i64 tcg_gen_ld_i64_armeb #define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_armeb @@ -2733,12 +2759,28 @@ #define tcg_gen_movi_i32 tcg_gen_movi_i32_armeb #define tcg_gen_movi_i64 tcg_gen_movi_i64_armeb #define tcg_gen_mul_i32 tcg_gen_mul_i32_armeb +#define tcg_gen_mul_i64 tcg_gen_mul_i64_armeb +#define tcg_gen_muli_i32 tcg_gen_muli_i32_armeb +#define tcg_gen_muli_i64 tcg_gen_muli_i64_armeb #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_armeb +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_armeb #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_armeb +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_armeb +#define tcg_gen_nand_i32 tcg_gen_nand_i32_armeb +#define tcg_gen_nand_i64 tcg_gen_nand_i64_armeb #define tcg_gen_neg_i32 tcg_gen_neg_i32_armeb #define tcg_gen_neg_i64 tcg_gen_neg_i64_armeb +#define tcg_gen_nor_i32 tcg_gen_nor_i32_armeb +#define tcg_gen_nor_i64 tcg_gen_nor_i64_armeb #define tcg_gen_not_i32 tcg_gen_not_i32_armeb +#define tcg_gen_not_i64 tcg_gen_not_i64_armeb #define tcg_gen_op0 tcg_gen_op0_armeb +#define tcg_gen_op1 tcg_gen_op1_armeb +#define tcg_gen_op2 tcg_gen_op2_armeb +#define tcg_gen_op3 tcg_gen_op3_armeb +#define tcg_gen_op4 tcg_gen_op4_armeb +#define tcg_gen_op5 tcg_gen_op5_armeb +#define tcg_gen_op6 tcg_gen_op6_armeb #define tcg_gen_op1i tcg_gen_op1i_armeb #define tcg_gen_op2_i32 tcg_gen_op2_i32_armeb #define tcg_gen_op2_i64 tcg_gen_op2_i64_armeb @@ -2755,20 +2797,35 @@ #define tcg_gen_op6i_i32 tcg_gen_op6i_i32_armeb #define tcg_gen_op6i_i64 tcg_gen_op6i_i64_armeb #define tcg_gen_orc_i32 tcg_gen_orc_i32_armeb +#define tcg_gen_orc_i64 tcg_gen_orc_i64_armeb #define tcg_gen_or_i32 tcg_gen_or_i32_armeb #define tcg_gen_or_i64 tcg_gen_or_i64_armeb #define tcg_gen_ori_i32 tcg_gen_ori_i32_armeb +#define tcg_gen_ori_i64 tcg_gen_ori_i64_armeb #define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_armeb #define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_armeb #define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_armeb #define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_armeb +#define tcg_gen_rem_i32 tcg_gen_rem_i32_armeb +#define tcg_gen_rem_i64 tcg_gen_rem_i64_armeb +#define tcg_gen_remu_i32 tcg_gen_remu_i32_armeb +#define tcg_gen_remu_i64 tcg_gen_remu_i64_armeb #define tcg_gen_rotl_i32 tcg_gen_rotl_i32_armeb +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_armeb #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_armeb +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_armeb #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_armeb +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_armeb #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_armeb +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_armeb #define tcg_gen_sar_i32 tcg_gen_sar_i32_armeb +#define tcg_gen_sar_i64 tcg_gen_sar_i64_armeb #define tcg_gen_sari_i32 tcg_gen_sari_i32_armeb +#define tcg_gen_sari_i64 tcg_gen_sari_i64_armeb #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_armeb +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_armeb +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_armeb +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_armeb #define tcg_gen_shl_i32 tcg_gen_shl_i32_armeb #define tcg_gen_shl_i64 tcg_gen_shl_i64_armeb #define tcg_gen_shli_i32 tcg_gen_shli_i32_armeb @@ -2780,14 +2837,20 @@ #define tcg_gen_shri_i64 tcg_gen_shri_i64_armeb #define tcg_gen_st_i32 tcg_gen_st_i32_armeb #define tcg_gen_st_i64 tcg_gen_st_i64_armeb +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_armeb +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_armeb #define tcg_gen_sub_i32 tcg_gen_sub_i32_armeb #define tcg_gen_sub_i64 tcg_gen_sub_i64_armeb +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_armeb +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_armeb #define tcg_gen_subi_i32 tcg_gen_subi_i32_armeb +#define tcg_gen_subi_i64 tcg_gen_subi_i64_armeb #define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_armeb #define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_armeb #define tcg_gen_xor_i32 tcg_gen_xor_i32_armeb #define tcg_gen_xor_i64 tcg_gen_xor_i64_armeb #define tcg_gen_xori_i32 tcg_gen_xori_i32_armeb +#define tcg_gen_xori_i64 tcg_gen_xori_i64_armeb #define tcg_get_arg_str_i32 tcg_get_arg_str_i32_armeb #define tcg_get_arg_str_i64 tcg_get_arg_str_i64_armeb #define tcg_get_arg_str_idx tcg_get_arg_str_idx_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 253bd3e4..8a011359 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -2696,11 +2696,13 @@ symbols = ( 'tcg_func_start', 'tcg_gen_abs_i32', 'tcg_gen_add2_i32', + 'tcg_gen_add2_i64', 'tcg_gen_add_i32', 'tcg_gen_add_i64', 'tcg_gen_addi_i32', 'tcg_gen_addi_i64', 'tcg_gen_andc_i32', + 'tcg_gen_andc_i64', 'tcg_gen_and_i32', 'tcg_gen_and_i64', 'tcg_gen_andi_i32', @@ -2709,8 +2711,12 @@ symbols = ( 'tcg_gen_brcond_i32', 'tcg_gen_brcond_i64', 'tcg_gen_brcondi_i32', + 'tcg_gen_brcondi_i64', 'tcg_gen_bswap16_i32', + 'tcg_gen_bswap16_i64', 'tcg_gen_bswap32_i32', + 'tcg_gen_bswap32_i64', + 'tcg_gen_bswap64_i64', 'tcg_gen_callN', 'tcg_gen_code', 'tcg_gen_code_common', @@ -2718,16 +2724,36 @@ symbols = ( 'tcg_gen_concat_i32_i64', 'tcg_gen_debug_insn_start', 'tcg_gen_deposit_i32', + 'tcg_gen_deposit_i64', + 'tcg_gen_discard_i64', + 'tcg_gen_div_i32', + 'tcg_gen_div_i64', + 'tcg_gen_divu_i32', + 'tcg_gen_divu_i64', + 'tcg_gen_eqv_i32', + 'tcg_gen_eqv_i64', 'tcg_gen_exit_tb', 'tcg_gen_ext16s_i32', + 'tcg_gen_ext16s_i64', 'tcg_gen_ext16u_i32', + 'tcg_gen_ext16u_i64', 'tcg_gen_ext32s_i64', 'tcg_gen_ext32u_i64', 'tcg_gen_ext8s_i32', + 'tcg_gen_ext8s_i64', 'tcg_gen_ext8u_i32', + 'tcg_gen_ext8u_i64', 'tcg_gen_ext_i32_i64', + 'tcg_gen_extr32_i64', + 'tcg_gen_extr_i64_i32', 'tcg_gen_extu_i32_i64', 'tcg_gen_goto_tb', + 'tcg_gen_ld16s_i64', + 'tcg_gen_ld16u_i64', + 'tcg_gen_ld32s_i64', + 'tcg_gen_ld32u_i64', + 'tcg_gen_ld8s_i64', + 'tcg_gen_ld8u_i64', 'tcg_gen_ld_i32', 'tcg_gen_ld_i64', 'tcg_gen_ldst_op_i32', @@ -2739,12 +2765,28 @@ symbols = ( 'tcg_gen_movi_i32', 'tcg_gen_movi_i64', 'tcg_gen_mul_i32', + 'tcg_gen_mul_i64', + 'tcg_gen_muli_i32', + 'tcg_gen_muli_i64', 'tcg_gen_muls2_i32', + 'tcg_gen_muls2_i64', 'tcg_gen_mulu2_i32', + 'tcg_gen_mulu2_i64', + 'tcg_gen_nand_i32', + 'tcg_gen_nand_i64', 'tcg_gen_neg_i32', 'tcg_gen_neg_i64', + 'tcg_gen_nor_i32', + 'tcg_gen_nor_i64', 'tcg_gen_not_i32', + 'tcg_gen_not_i64', 'tcg_gen_op0', + 'tcg_gen_op1', + 'tcg_gen_op2', + 'tcg_gen_op3', + 'tcg_gen_op4', + 'tcg_gen_op5', + 'tcg_gen_op6', 'tcg_gen_op1i', 'tcg_gen_op2_i32', 'tcg_gen_op2_i64', @@ -2761,20 +2803,35 @@ symbols = ( 'tcg_gen_op6i_i32', 'tcg_gen_op6i_i64', 'tcg_gen_orc_i32', + 'tcg_gen_orc_i64', 'tcg_gen_or_i32', 'tcg_gen_or_i64', 'tcg_gen_ori_i32', + 'tcg_gen_ori_i64', 'tcg_gen_qemu_ld_i32', 'tcg_gen_qemu_ld_i64', 'tcg_gen_qemu_st_i32', 'tcg_gen_qemu_st_i64', + 'tcg_gen_rem_i32', + 'tcg_gen_rem_i64', + 'tcg_gen_remu_i32', + 'tcg_gen_remu_i64', 'tcg_gen_rotl_i32', + 'tcg_gen_rotl_i64', 'tcg_gen_rotli_i32', + 'tcg_gen_rotli_i64', 'tcg_gen_rotr_i32', + 'tcg_gen_rotr_i64', 'tcg_gen_rotri_i32', + 'tcg_gen_rotri_i64', 'tcg_gen_sar_i32', + 'tcg_gen_sar_i64', 'tcg_gen_sari_i32', + 'tcg_gen_sari_i64', 'tcg_gen_setcond_i32', + 'tcg_gen_setcond_i64', + 'tcg_gen_setcondi_i32', + 'tcg_gen_setcondi_i64', 'tcg_gen_shl_i32', 'tcg_gen_shl_i64', 'tcg_gen_shli_i32', @@ -2786,14 +2843,20 @@ symbols = ( 'tcg_gen_shri_i64', 'tcg_gen_st_i32', 'tcg_gen_st_i64', + 'tcg_gen_sub2_i32', + 'tcg_gen_sub2_i64', 'tcg_gen_sub_i32', 'tcg_gen_sub_i64', + 'tcg_gen_subfi_i32', + 'tcg_gen_subfi_i64', 'tcg_gen_subi_i32', + 'tcg_gen_subi_i64', 'tcg_gen_trunc_i64_i32', 'tcg_gen_trunc_shr_i64_i32', 'tcg_gen_xor_i32', 'tcg_gen_xor_i64', 'tcg_gen_xori_i32', + 'tcg_gen_xori_i64', 'tcg_get_arg_str_i32', 'tcg_get_arg_str_i64', 'tcg_get_arg_str_idx', diff --git a/qemu/m68k.h b/qemu/m68k.h index dffdf7e7..e51689c8 100644 --- a/qemu/m68k.h +++ b/qemu/m68k.h @@ -2690,11 +2690,13 @@ #define tcg_func_start tcg_func_start_m68k #define tcg_gen_abs_i32 tcg_gen_abs_i32_m68k #define tcg_gen_add2_i32 tcg_gen_add2_i32_m68k +#define tcg_gen_add2_i64 tcg_gen_add2_i64_m68k #define tcg_gen_add_i32 tcg_gen_add_i32_m68k #define tcg_gen_add_i64 tcg_gen_add_i64_m68k #define tcg_gen_addi_i32 tcg_gen_addi_i32_m68k #define tcg_gen_addi_i64 tcg_gen_addi_i64_m68k #define tcg_gen_andc_i32 tcg_gen_andc_i32_m68k +#define tcg_gen_andc_i64 tcg_gen_andc_i64_m68k #define tcg_gen_and_i32 tcg_gen_and_i32_m68k #define tcg_gen_and_i64 tcg_gen_and_i64_m68k #define tcg_gen_andi_i32 tcg_gen_andi_i32_m68k @@ -2703,8 +2705,12 @@ #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_m68k #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_m68k #define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_m68k +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_m68k #define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_m68k +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_m68k #define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_m68k +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_m68k +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_m68k #define tcg_gen_callN tcg_gen_callN_m68k #define tcg_gen_code tcg_gen_code_m68k #define tcg_gen_code_common tcg_gen_code_common_m68k @@ -2712,16 +2718,36 @@ #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_m68k #define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_m68k #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_m68k +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_m68k +#define tcg_gen_discard_i64 tcg_gen_discard_i64_m68k +#define tcg_gen_div_i32 tcg_gen_div_i32_m68k +#define tcg_gen_div_i64 tcg_gen_div_i64_m68k +#define tcg_gen_divu_i32 tcg_gen_divu_i32_m68k +#define tcg_gen_divu_i64 tcg_gen_divu_i64_m68k +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_m68k +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_m68k #define tcg_gen_exit_tb tcg_gen_exit_tb_m68k #define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_m68k +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_m68k #define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_m68k +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_m68k #define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_m68k #define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_m68k #define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_m68k +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_m68k #define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_m68k +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_m68k #define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_m68k +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_m68k +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_m68k #define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_m68k #define tcg_gen_goto_tb tcg_gen_goto_tb_m68k +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_m68k +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_m68k +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_m68k +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_m68k +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_m68k +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_m68k #define tcg_gen_ld_i32 tcg_gen_ld_i32_m68k #define tcg_gen_ld_i64 tcg_gen_ld_i64_m68k #define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_m68k @@ -2733,12 +2759,28 @@ #define tcg_gen_movi_i32 tcg_gen_movi_i32_m68k #define tcg_gen_movi_i64 tcg_gen_movi_i64_m68k #define tcg_gen_mul_i32 tcg_gen_mul_i32_m68k +#define tcg_gen_mul_i64 tcg_gen_mul_i64_m68k +#define tcg_gen_muli_i32 tcg_gen_muli_i32_m68k +#define tcg_gen_muli_i64 tcg_gen_muli_i64_m68k #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_m68k +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_m68k #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_m68k +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_m68k +#define tcg_gen_nand_i32 tcg_gen_nand_i32_m68k +#define tcg_gen_nand_i64 tcg_gen_nand_i64_m68k #define tcg_gen_neg_i32 tcg_gen_neg_i32_m68k #define tcg_gen_neg_i64 tcg_gen_neg_i64_m68k +#define tcg_gen_nor_i32 tcg_gen_nor_i32_m68k +#define tcg_gen_nor_i64 tcg_gen_nor_i64_m68k #define tcg_gen_not_i32 tcg_gen_not_i32_m68k +#define tcg_gen_not_i64 tcg_gen_not_i64_m68k #define tcg_gen_op0 tcg_gen_op0_m68k +#define tcg_gen_op1 tcg_gen_op1_m68k +#define tcg_gen_op2 tcg_gen_op2_m68k +#define tcg_gen_op3 tcg_gen_op3_m68k +#define tcg_gen_op4 tcg_gen_op4_m68k +#define tcg_gen_op5 tcg_gen_op5_m68k +#define tcg_gen_op6 tcg_gen_op6_m68k #define tcg_gen_op1i tcg_gen_op1i_m68k #define tcg_gen_op2_i32 tcg_gen_op2_i32_m68k #define tcg_gen_op2_i64 tcg_gen_op2_i64_m68k @@ -2755,20 +2797,35 @@ #define tcg_gen_op6i_i32 tcg_gen_op6i_i32_m68k #define tcg_gen_op6i_i64 tcg_gen_op6i_i64_m68k #define tcg_gen_orc_i32 tcg_gen_orc_i32_m68k +#define tcg_gen_orc_i64 tcg_gen_orc_i64_m68k #define tcg_gen_or_i32 tcg_gen_or_i32_m68k #define tcg_gen_or_i64 tcg_gen_or_i64_m68k #define tcg_gen_ori_i32 tcg_gen_ori_i32_m68k +#define tcg_gen_ori_i64 tcg_gen_ori_i64_m68k #define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_m68k #define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_m68k #define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_m68k #define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_m68k +#define tcg_gen_rem_i32 tcg_gen_rem_i32_m68k +#define tcg_gen_rem_i64 tcg_gen_rem_i64_m68k +#define tcg_gen_remu_i32 tcg_gen_remu_i32_m68k +#define tcg_gen_remu_i64 tcg_gen_remu_i64_m68k #define tcg_gen_rotl_i32 tcg_gen_rotl_i32_m68k +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_m68k #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_m68k +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_m68k #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_m68k +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_m68k #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_m68k +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_m68k #define tcg_gen_sar_i32 tcg_gen_sar_i32_m68k +#define tcg_gen_sar_i64 tcg_gen_sar_i64_m68k #define tcg_gen_sari_i32 tcg_gen_sari_i32_m68k +#define tcg_gen_sari_i64 tcg_gen_sari_i64_m68k #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_m68k +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_m68k +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_m68k +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_m68k #define tcg_gen_shl_i32 tcg_gen_shl_i32_m68k #define tcg_gen_shl_i64 tcg_gen_shl_i64_m68k #define tcg_gen_shli_i32 tcg_gen_shli_i32_m68k @@ -2780,14 +2837,20 @@ #define tcg_gen_shri_i64 tcg_gen_shri_i64_m68k #define tcg_gen_st_i32 tcg_gen_st_i32_m68k #define tcg_gen_st_i64 tcg_gen_st_i64_m68k +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_m68k +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_m68k #define tcg_gen_sub_i32 tcg_gen_sub_i32_m68k #define tcg_gen_sub_i64 tcg_gen_sub_i64_m68k +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_m68k +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_m68k #define tcg_gen_subi_i32 tcg_gen_subi_i32_m68k +#define tcg_gen_subi_i64 tcg_gen_subi_i64_m68k #define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_m68k #define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_m68k #define tcg_gen_xor_i32 tcg_gen_xor_i32_m68k #define tcg_gen_xor_i64 tcg_gen_xor_i64_m68k #define tcg_gen_xori_i32 tcg_gen_xori_i32_m68k +#define tcg_gen_xori_i64 tcg_gen_xori_i64_m68k #define tcg_get_arg_str_i32 tcg_get_arg_str_i32_m68k #define tcg_get_arg_str_i64 tcg_get_arg_str_i64_m68k #define tcg_get_arg_str_idx tcg_get_arg_str_idx_m68k diff --git a/qemu/mips.h b/qemu/mips.h index 36ad9a4d..0b9dd49b 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -2690,11 +2690,13 @@ #define tcg_func_start tcg_func_start_mips #define tcg_gen_abs_i32 tcg_gen_abs_i32_mips #define tcg_gen_add2_i32 tcg_gen_add2_i32_mips +#define tcg_gen_add2_i64 tcg_gen_add2_i64_mips #define tcg_gen_add_i32 tcg_gen_add_i32_mips #define tcg_gen_add_i64 tcg_gen_add_i64_mips #define tcg_gen_addi_i32 tcg_gen_addi_i32_mips #define tcg_gen_addi_i64 tcg_gen_addi_i64_mips #define tcg_gen_andc_i32 tcg_gen_andc_i32_mips +#define tcg_gen_andc_i64 tcg_gen_andc_i64_mips #define tcg_gen_and_i32 tcg_gen_and_i32_mips #define tcg_gen_and_i64 tcg_gen_and_i64_mips #define tcg_gen_andi_i32 tcg_gen_andi_i32_mips @@ -2703,8 +2705,12 @@ #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_mips #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_mips #define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_mips +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_mips #define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_mips +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_mips #define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_mips +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_mips +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_mips #define tcg_gen_callN tcg_gen_callN_mips #define tcg_gen_code tcg_gen_code_mips #define tcg_gen_code_common tcg_gen_code_common_mips @@ -2712,16 +2718,36 @@ #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips #define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_mips #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mips +#define tcg_gen_discard_i64 tcg_gen_discard_i64_mips +#define tcg_gen_div_i32 tcg_gen_div_i32_mips +#define tcg_gen_div_i64 tcg_gen_div_i64_mips +#define tcg_gen_divu_i32 tcg_gen_divu_i32_mips +#define tcg_gen_divu_i64 tcg_gen_divu_i64_mips +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_mips #define tcg_gen_exit_tb tcg_gen_exit_tb_mips #define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_mips +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_mips #define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_mips +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_mips #define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_mips #define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_mips #define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_mips +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_mips #define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_mips +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_mips #define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mips +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mips +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mips #define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips #define tcg_gen_goto_tb tcg_gen_goto_tb_mips +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_mips +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_mips +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_mips +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_mips #define tcg_gen_ld_i32 tcg_gen_ld_i32_mips #define tcg_gen_ld_i64 tcg_gen_ld_i64_mips #define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_mips @@ -2733,12 +2759,28 @@ #define tcg_gen_movi_i32 tcg_gen_movi_i32_mips #define tcg_gen_movi_i64 tcg_gen_movi_i64_mips #define tcg_gen_mul_i32 tcg_gen_mul_i32_mips +#define tcg_gen_mul_i64 tcg_gen_mul_i64_mips +#define tcg_gen_muli_i32 tcg_gen_muli_i32_mips +#define tcg_gen_muli_i64 tcg_gen_muli_i64_mips #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mips +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mips #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mips +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mips +#define tcg_gen_nand_i32 tcg_gen_nand_i32_mips +#define tcg_gen_nand_i64 tcg_gen_nand_i64_mips #define tcg_gen_neg_i32 tcg_gen_neg_i32_mips #define tcg_gen_neg_i64 tcg_gen_neg_i64_mips +#define tcg_gen_nor_i32 tcg_gen_nor_i32_mips +#define tcg_gen_nor_i64 tcg_gen_nor_i64_mips #define tcg_gen_not_i32 tcg_gen_not_i32_mips +#define tcg_gen_not_i64 tcg_gen_not_i64_mips #define tcg_gen_op0 tcg_gen_op0_mips +#define tcg_gen_op1 tcg_gen_op1_mips +#define tcg_gen_op2 tcg_gen_op2_mips +#define tcg_gen_op3 tcg_gen_op3_mips +#define tcg_gen_op4 tcg_gen_op4_mips +#define tcg_gen_op5 tcg_gen_op5_mips +#define tcg_gen_op6 tcg_gen_op6_mips #define tcg_gen_op1i tcg_gen_op1i_mips #define tcg_gen_op2_i32 tcg_gen_op2_i32_mips #define tcg_gen_op2_i64 tcg_gen_op2_i64_mips @@ -2755,20 +2797,35 @@ #define tcg_gen_op6i_i32 tcg_gen_op6i_i32_mips #define tcg_gen_op6i_i64 tcg_gen_op6i_i64_mips #define tcg_gen_orc_i32 tcg_gen_orc_i32_mips +#define tcg_gen_orc_i64 tcg_gen_orc_i64_mips #define tcg_gen_or_i32 tcg_gen_or_i32_mips #define tcg_gen_or_i64 tcg_gen_or_i64_mips #define tcg_gen_ori_i32 tcg_gen_ori_i32_mips +#define tcg_gen_ori_i64 tcg_gen_ori_i64_mips #define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_mips #define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_mips #define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_mips #define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_mips +#define tcg_gen_rem_i32 tcg_gen_rem_i32_mips +#define tcg_gen_rem_i64 tcg_gen_rem_i64_mips +#define tcg_gen_remu_i32 tcg_gen_remu_i32_mips +#define tcg_gen_remu_i64 tcg_gen_remu_i64_mips #define tcg_gen_rotl_i32 tcg_gen_rotl_i32_mips +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_mips #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mips +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mips #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mips +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mips #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mips +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_mips #define tcg_gen_sar_i32 tcg_gen_sar_i32_mips +#define tcg_gen_sar_i64 tcg_gen_sar_i64_mips #define tcg_gen_sari_i32 tcg_gen_sari_i32_mips +#define tcg_gen_sari_i64 tcg_gen_sari_i64_mips #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_mips #define tcg_gen_shl_i32 tcg_gen_shl_i32_mips #define tcg_gen_shl_i64 tcg_gen_shl_i64_mips #define tcg_gen_shli_i32 tcg_gen_shli_i32_mips @@ -2780,14 +2837,20 @@ #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips #define tcg_gen_st_i32 tcg_gen_st_i32_mips #define tcg_gen_st_i64 tcg_gen_st_i64_mips +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_mips +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_mips #define tcg_gen_sub_i32 tcg_gen_sub_i32_mips #define tcg_gen_sub_i64 tcg_gen_sub_i64_mips +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_mips +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips #define tcg_gen_subi_i32 tcg_gen_subi_i32_mips +#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips #define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_mips #define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_mips #define tcg_gen_xor_i32 tcg_gen_xor_i32_mips #define tcg_gen_xor_i64 tcg_gen_xor_i64_mips #define tcg_gen_xori_i32 tcg_gen_xori_i32_mips +#define tcg_gen_xori_i64 tcg_gen_xori_i64_mips #define tcg_get_arg_str_i32 tcg_get_arg_str_i32_mips #define tcg_get_arg_str_i64 tcg_get_arg_str_i64_mips #define tcg_get_arg_str_idx tcg_get_arg_str_idx_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index e464d4b3..fa233c54 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -2690,11 +2690,13 @@ #define tcg_func_start tcg_func_start_mips64 #define tcg_gen_abs_i32 tcg_gen_abs_i32_mips64 #define tcg_gen_add2_i32 tcg_gen_add2_i32_mips64 +#define tcg_gen_add2_i64 tcg_gen_add2_i64_mips64 #define tcg_gen_add_i32 tcg_gen_add_i32_mips64 #define tcg_gen_add_i64 tcg_gen_add_i64_mips64 #define tcg_gen_addi_i32 tcg_gen_addi_i32_mips64 #define tcg_gen_addi_i64 tcg_gen_addi_i64_mips64 #define tcg_gen_andc_i32 tcg_gen_andc_i32_mips64 +#define tcg_gen_andc_i64 tcg_gen_andc_i64_mips64 #define tcg_gen_and_i32 tcg_gen_and_i32_mips64 #define tcg_gen_and_i64 tcg_gen_and_i64_mips64 #define tcg_gen_andi_i32 tcg_gen_andi_i32_mips64 @@ -2703,8 +2705,12 @@ #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_mips64 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_mips64 #define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_mips64 +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_mips64 #define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_mips64 +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_mips64 #define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_mips64 +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_mips64 +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_mips64 #define tcg_gen_callN tcg_gen_callN_mips64 #define tcg_gen_code tcg_gen_code_mips64 #define tcg_gen_code_common tcg_gen_code_common_mips64 @@ -2712,16 +2718,36 @@ #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips64 #define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_mips64 #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips64 +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mips64 +#define tcg_gen_discard_i64 tcg_gen_discard_i64_mips64 +#define tcg_gen_div_i32 tcg_gen_div_i32_mips64 +#define tcg_gen_div_i64 tcg_gen_div_i64_mips64 +#define tcg_gen_divu_i32 tcg_gen_divu_i32_mips64 +#define tcg_gen_divu_i64 tcg_gen_divu_i64_mips64 +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips64 +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_mips64 #define tcg_gen_exit_tb tcg_gen_exit_tb_mips64 #define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_mips64 +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_mips64 #define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_mips64 +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_mips64 #define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_mips64 #define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_mips64 #define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_mips64 +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_mips64 #define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_mips64 +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_mips64 #define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mips64 +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mips64 +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mips64 #define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64 #define tcg_gen_goto_tb tcg_gen_goto_tb_mips64 +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips64 +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips64 +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_mips64 +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_mips64 +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_mips64 +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_mips64 #define tcg_gen_ld_i32 tcg_gen_ld_i32_mips64 #define tcg_gen_ld_i64 tcg_gen_ld_i64_mips64 #define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_mips64 @@ -2733,12 +2759,28 @@ #define tcg_gen_movi_i32 tcg_gen_movi_i32_mips64 #define tcg_gen_movi_i64 tcg_gen_movi_i64_mips64 #define tcg_gen_mul_i32 tcg_gen_mul_i32_mips64 +#define tcg_gen_mul_i64 tcg_gen_mul_i64_mips64 +#define tcg_gen_muli_i32 tcg_gen_muli_i32_mips64 +#define tcg_gen_muli_i64 tcg_gen_muli_i64_mips64 #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mips64 +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mips64 #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mips64 +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mips64 +#define tcg_gen_nand_i32 tcg_gen_nand_i32_mips64 +#define tcg_gen_nand_i64 tcg_gen_nand_i64_mips64 #define tcg_gen_neg_i32 tcg_gen_neg_i32_mips64 #define tcg_gen_neg_i64 tcg_gen_neg_i64_mips64 +#define tcg_gen_nor_i32 tcg_gen_nor_i32_mips64 +#define tcg_gen_nor_i64 tcg_gen_nor_i64_mips64 #define tcg_gen_not_i32 tcg_gen_not_i32_mips64 +#define tcg_gen_not_i64 tcg_gen_not_i64_mips64 #define tcg_gen_op0 tcg_gen_op0_mips64 +#define tcg_gen_op1 tcg_gen_op1_mips64 +#define tcg_gen_op2 tcg_gen_op2_mips64 +#define tcg_gen_op3 tcg_gen_op3_mips64 +#define tcg_gen_op4 tcg_gen_op4_mips64 +#define tcg_gen_op5 tcg_gen_op5_mips64 +#define tcg_gen_op6 tcg_gen_op6_mips64 #define tcg_gen_op1i tcg_gen_op1i_mips64 #define tcg_gen_op2_i32 tcg_gen_op2_i32_mips64 #define tcg_gen_op2_i64 tcg_gen_op2_i64_mips64 @@ -2755,20 +2797,35 @@ #define tcg_gen_op6i_i32 tcg_gen_op6i_i32_mips64 #define tcg_gen_op6i_i64 tcg_gen_op6i_i64_mips64 #define tcg_gen_orc_i32 tcg_gen_orc_i32_mips64 +#define tcg_gen_orc_i64 tcg_gen_orc_i64_mips64 #define tcg_gen_or_i32 tcg_gen_or_i32_mips64 #define tcg_gen_or_i64 tcg_gen_or_i64_mips64 #define tcg_gen_ori_i32 tcg_gen_ori_i32_mips64 +#define tcg_gen_ori_i64 tcg_gen_ori_i64_mips64 #define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_mips64 #define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_mips64 #define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_mips64 #define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_mips64 +#define tcg_gen_rem_i32 tcg_gen_rem_i32_mips64 +#define tcg_gen_rem_i64 tcg_gen_rem_i64_mips64 +#define tcg_gen_remu_i32 tcg_gen_remu_i32_mips64 +#define tcg_gen_remu_i64 tcg_gen_remu_i64_mips64 #define tcg_gen_rotl_i32 tcg_gen_rotl_i32_mips64 +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_mips64 #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mips64 +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mips64 #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mips64 +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mips64 #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mips64 +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_mips64 #define tcg_gen_sar_i32 tcg_gen_sar_i32_mips64 +#define tcg_gen_sar_i64 tcg_gen_sar_i64_mips64 #define tcg_gen_sari_i32 tcg_gen_sari_i32_mips64 +#define tcg_gen_sari_i64 tcg_gen_sari_i64_mips64 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips64 +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips64 +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips64 +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_mips64 #define tcg_gen_shl_i32 tcg_gen_shl_i32_mips64 #define tcg_gen_shl_i64 tcg_gen_shl_i64_mips64 #define tcg_gen_shli_i32 tcg_gen_shli_i32_mips64 @@ -2780,14 +2837,20 @@ #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64 #define tcg_gen_st_i32 tcg_gen_st_i32_mips64 #define tcg_gen_st_i64 tcg_gen_st_i64_mips64 +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_mips64 +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_mips64 #define tcg_gen_sub_i32 tcg_gen_sub_i32_mips64 #define tcg_gen_sub_i64 tcg_gen_sub_i64_mips64 +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_mips64 +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64 #define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64 +#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64 #define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_mips64 #define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_mips64 #define tcg_gen_xor_i32 tcg_gen_xor_i32_mips64 #define tcg_gen_xor_i64 tcg_gen_xor_i64_mips64 #define tcg_gen_xori_i32 tcg_gen_xori_i32_mips64 +#define tcg_gen_xori_i64 tcg_gen_xori_i64_mips64 #define tcg_get_arg_str_i32 tcg_get_arg_str_i32_mips64 #define tcg_get_arg_str_i64 tcg_get_arg_str_i64_mips64 #define tcg_get_arg_str_idx tcg_get_arg_str_idx_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index afe0d47f..ddb2021f 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -2690,11 +2690,13 @@ #define tcg_func_start tcg_func_start_mips64el #define tcg_gen_abs_i32 tcg_gen_abs_i32_mips64el #define tcg_gen_add2_i32 tcg_gen_add2_i32_mips64el +#define tcg_gen_add2_i64 tcg_gen_add2_i64_mips64el #define tcg_gen_add_i32 tcg_gen_add_i32_mips64el #define tcg_gen_add_i64 tcg_gen_add_i64_mips64el #define tcg_gen_addi_i32 tcg_gen_addi_i32_mips64el #define tcg_gen_addi_i64 tcg_gen_addi_i64_mips64el #define tcg_gen_andc_i32 tcg_gen_andc_i32_mips64el +#define tcg_gen_andc_i64 tcg_gen_andc_i64_mips64el #define tcg_gen_and_i32 tcg_gen_and_i32_mips64el #define tcg_gen_and_i64 tcg_gen_and_i64_mips64el #define tcg_gen_andi_i32 tcg_gen_andi_i32_mips64el @@ -2703,8 +2705,12 @@ #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_mips64el #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_mips64el #define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_mips64el +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_mips64el #define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_mips64el +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_mips64el #define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_mips64el +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_mips64el +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_mips64el #define tcg_gen_callN tcg_gen_callN_mips64el #define tcg_gen_code tcg_gen_code_mips64el #define tcg_gen_code_common tcg_gen_code_common_mips64el @@ -2712,16 +2718,36 @@ #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips64el #define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_mips64el #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips64el +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mips64el +#define tcg_gen_discard_i64 tcg_gen_discard_i64_mips64el +#define tcg_gen_div_i32 tcg_gen_div_i32_mips64el +#define tcg_gen_div_i64 tcg_gen_div_i64_mips64el +#define tcg_gen_divu_i32 tcg_gen_divu_i32_mips64el +#define tcg_gen_divu_i64 tcg_gen_divu_i64_mips64el +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips64el +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_mips64el #define tcg_gen_exit_tb tcg_gen_exit_tb_mips64el #define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_mips64el +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_mips64el #define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_mips64el +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_mips64el #define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_mips64el #define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_mips64el #define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_mips64el +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_mips64el #define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_mips64el +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_mips64el #define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mips64el +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mips64el +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mips64el #define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64el #define tcg_gen_goto_tb tcg_gen_goto_tb_mips64el +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips64el +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips64el +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_mips64el +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_mips64el +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_mips64el +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_mips64el #define tcg_gen_ld_i32 tcg_gen_ld_i32_mips64el #define tcg_gen_ld_i64 tcg_gen_ld_i64_mips64el #define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_mips64el @@ -2733,12 +2759,28 @@ #define tcg_gen_movi_i32 tcg_gen_movi_i32_mips64el #define tcg_gen_movi_i64 tcg_gen_movi_i64_mips64el #define tcg_gen_mul_i32 tcg_gen_mul_i32_mips64el +#define tcg_gen_mul_i64 tcg_gen_mul_i64_mips64el +#define tcg_gen_muli_i32 tcg_gen_muli_i32_mips64el +#define tcg_gen_muli_i64 tcg_gen_muli_i64_mips64el #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mips64el +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mips64el #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mips64el +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mips64el +#define tcg_gen_nand_i32 tcg_gen_nand_i32_mips64el +#define tcg_gen_nand_i64 tcg_gen_nand_i64_mips64el #define tcg_gen_neg_i32 tcg_gen_neg_i32_mips64el #define tcg_gen_neg_i64 tcg_gen_neg_i64_mips64el +#define tcg_gen_nor_i32 tcg_gen_nor_i32_mips64el +#define tcg_gen_nor_i64 tcg_gen_nor_i64_mips64el #define tcg_gen_not_i32 tcg_gen_not_i32_mips64el +#define tcg_gen_not_i64 tcg_gen_not_i64_mips64el #define tcg_gen_op0 tcg_gen_op0_mips64el +#define tcg_gen_op1 tcg_gen_op1_mips64el +#define tcg_gen_op2 tcg_gen_op2_mips64el +#define tcg_gen_op3 tcg_gen_op3_mips64el +#define tcg_gen_op4 tcg_gen_op4_mips64el +#define tcg_gen_op5 tcg_gen_op5_mips64el +#define tcg_gen_op6 tcg_gen_op6_mips64el #define tcg_gen_op1i tcg_gen_op1i_mips64el #define tcg_gen_op2_i32 tcg_gen_op2_i32_mips64el #define tcg_gen_op2_i64 tcg_gen_op2_i64_mips64el @@ -2755,20 +2797,35 @@ #define tcg_gen_op6i_i32 tcg_gen_op6i_i32_mips64el #define tcg_gen_op6i_i64 tcg_gen_op6i_i64_mips64el #define tcg_gen_orc_i32 tcg_gen_orc_i32_mips64el +#define tcg_gen_orc_i64 tcg_gen_orc_i64_mips64el #define tcg_gen_or_i32 tcg_gen_or_i32_mips64el #define tcg_gen_or_i64 tcg_gen_or_i64_mips64el #define tcg_gen_ori_i32 tcg_gen_ori_i32_mips64el +#define tcg_gen_ori_i64 tcg_gen_ori_i64_mips64el #define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_mips64el #define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_mips64el #define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_mips64el #define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_mips64el +#define tcg_gen_rem_i32 tcg_gen_rem_i32_mips64el +#define tcg_gen_rem_i64 tcg_gen_rem_i64_mips64el +#define tcg_gen_remu_i32 tcg_gen_remu_i32_mips64el +#define tcg_gen_remu_i64 tcg_gen_remu_i64_mips64el #define tcg_gen_rotl_i32 tcg_gen_rotl_i32_mips64el +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_mips64el #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mips64el +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mips64el #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mips64el +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mips64el #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mips64el +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_mips64el #define tcg_gen_sar_i32 tcg_gen_sar_i32_mips64el +#define tcg_gen_sar_i64 tcg_gen_sar_i64_mips64el #define tcg_gen_sari_i32 tcg_gen_sari_i32_mips64el +#define tcg_gen_sari_i64 tcg_gen_sari_i64_mips64el #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips64el +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips64el +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips64el +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_mips64el #define tcg_gen_shl_i32 tcg_gen_shl_i32_mips64el #define tcg_gen_shl_i64 tcg_gen_shl_i64_mips64el #define tcg_gen_shli_i32 tcg_gen_shli_i32_mips64el @@ -2780,14 +2837,20 @@ #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64el #define tcg_gen_st_i32 tcg_gen_st_i32_mips64el #define tcg_gen_st_i64 tcg_gen_st_i64_mips64el +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_mips64el +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_mips64el #define tcg_gen_sub_i32 tcg_gen_sub_i32_mips64el #define tcg_gen_sub_i64 tcg_gen_sub_i64_mips64el +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_mips64el +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64el #define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64el +#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64el #define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_mips64el #define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_mips64el #define tcg_gen_xor_i32 tcg_gen_xor_i32_mips64el #define tcg_gen_xor_i64 tcg_gen_xor_i64_mips64el #define tcg_gen_xori_i32 tcg_gen_xori_i32_mips64el +#define tcg_gen_xori_i64 tcg_gen_xori_i64_mips64el #define tcg_get_arg_str_i32 tcg_get_arg_str_i32_mips64el #define tcg_get_arg_str_i64 tcg_get_arg_str_i64_mips64el #define tcg_get_arg_str_idx tcg_get_arg_str_idx_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index a04123e7..195d319a 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -2690,11 +2690,13 @@ #define tcg_func_start tcg_func_start_mipsel #define tcg_gen_abs_i32 tcg_gen_abs_i32_mipsel #define tcg_gen_add2_i32 tcg_gen_add2_i32_mipsel +#define tcg_gen_add2_i64 tcg_gen_add2_i64_mipsel #define tcg_gen_add_i32 tcg_gen_add_i32_mipsel #define tcg_gen_add_i64 tcg_gen_add_i64_mipsel #define tcg_gen_addi_i32 tcg_gen_addi_i32_mipsel #define tcg_gen_addi_i64 tcg_gen_addi_i64_mipsel #define tcg_gen_andc_i32 tcg_gen_andc_i32_mipsel +#define tcg_gen_andc_i64 tcg_gen_andc_i64_mipsel #define tcg_gen_and_i32 tcg_gen_and_i32_mipsel #define tcg_gen_and_i64 tcg_gen_and_i64_mipsel #define tcg_gen_andi_i32 tcg_gen_andi_i32_mipsel @@ -2703,8 +2705,12 @@ #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_mipsel #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_mipsel #define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_mipsel +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_mipsel #define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_mipsel +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_mipsel #define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_mipsel +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_mipsel +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_mipsel #define tcg_gen_callN tcg_gen_callN_mipsel #define tcg_gen_code tcg_gen_code_mipsel #define tcg_gen_code_common tcg_gen_code_common_mipsel @@ -2712,16 +2718,36 @@ #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mipsel #define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_mipsel #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mipsel +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mipsel +#define tcg_gen_discard_i64 tcg_gen_discard_i64_mipsel +#define tcg_gen_div_i32 tcg_gen_div_i32_mipsel +#define tcg_gen_div_i64 tcg_gen_div_i64_mipsel +#define tcg_gen_divu_i32 tcg_gen_divu_i32_mipsel +#define tcg_gen_divu_i64 tcg_gen_divu_i64_mipsel +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mipsel +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_mipsel #define tcg_gen_exit_tb tcg_gen_exit_tb_mipsel #define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_mipsel +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_mipsel #define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_mipsel +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_mipsel #define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_mipsel #define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_mipsel #define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_mipsel +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_mipsel #define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_mipsel +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_mipsel #define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mipsel +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mipsel +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mipsel #define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mipsel #define tcg_gen_goto_tb tcg_gen_goto_tb_mipsel +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mipsel +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mipsel +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_mipsel +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_mipsel +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_mipsel +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_mipsel #define tcg_gen_ld_i32 tcg_gen_ld_i32_mipsel #define tcg_gen_ld_i64 tcg_gen_ld_i64_mipsel #define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_mipsel @@ -2733,12 +2759,28 @@ #define tcg_gen_movi_i32 tcg_gen_movi_i32_mipsel #define tcg_gen_movi_i64 tcg_gen_movi_i64_mipsel #define tcg_gen_mul_i32 tcg_gen_mul_i32_mipsel +#define tcg_gen_mul_i64 tcg_gen_mul_i64_mipsel +#define tcg_gen_muli_i32 tcg_gen_muli_i32_mipsel +#define tcg_gen_muli_i64 tcg_gen_muli_i64_mipsel #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mipsel +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mipsel #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mipsel +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mipsel +#define tcg_gen_nand_i32 tcg_gen_nand_i32_mipsel +#define tcg_gen_nand_i64 tcg_gen_nand_i64_mipsel #define tcg_gen_neg_i32 tcg_gen_neg_i32_mipsel #define tcg_gen_neg_i64 tcg_gen_neg_i64_mipsel +#define tcg_gen_nor_i32 tcg_gen_nor_i32_mipsel +#define tcg_gen_nor_i64 tcg_gen_nor_i64_mipsel #define tcg_gen_not_i32 tcg_gen_not_i32_mipsel +#define tcg_gen_not_i64 tcg_gen_not_i64_mipsel #define tcg_gen_op0 tcg_gen_op0_mipsel +#define tcg_gen_op1 tcg_gen_op1_mipsel +#define tcg_gen_op2 tcg_gen_op2_mipsel +#define tcg_gen_op3 tcg_gen_op3_mipsel +#define tcg_gen_op4 tcg_gen_op4_mipsel +#define tcg_gen_op5 tcg_gen_op5_mipsel +#define tcg_gen_op6 tcg_gen_op6_mipsel #define tcg_gen_op1i tcg_gen_op1i_mipsel #define tcg_gen_op2_i32 tcg_gen_op2_i32_mipsel #define tcg_gen_op2_i64 tcg_gen_op2_i64_mipsel @@ -2755,20 +2797,35 @@ #define tcg_gen_op6i_i32 tcg_gen_op6i_i32_mipsel #define tcg_gen_op6i_i64 tcg_gen_op6i_i64_mipsel #define tcg_gen_orc_i32 tcg_gen_orc_i32_mipsel +#define tcg_gen_orc_i64 tcg_gen_orc_i64_mipsel #define tcg_gen_or_i32 tcg_gen_or_i32_mipsel #define tcg_gen_or_i64 tcg_gen_or_i64_mipsel #define tcg_gen_ori_i32 tcg_gen_ori_i32_mipsel +#define tcg_gen_ori_i64 tcg_gen_ori_i64_mipsel #define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_mipsel #define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_mipsel #define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_mipsel #define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_mipsel +#define tcg_gen_rem_i32 tcg_gen_rem_i32_mipsel +#define tcg_gen_rem_i64 tcg_gen_rem_i64_mipsel +#define tcg_gen_remu_i32 tcg_gen_remu_i32_mipsel +#define tcg_gen_remu_i64 tcg_gen_remu_i64_mipsel #define tcg_gen_rotl_i32 tcg_gen_rotl_i32_mipsel +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_mipsel #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mipsel +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mipsel #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mipsel +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mipsel #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mipsel +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_mipsel #define tcg_gen_sar_i32 tcg_gen_sar_i32_mipsel +#define tcg_gen_sar_i64 tcg_gen_sar_i64_mipsel #define tcg_gen_sari_i32 tcg_gen_sari_i32_mipsel +#define tcg_gen_sari_i64 tcg_gen_sari_i64_mipsel #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mipsel +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mipsel +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mipsel +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_mipsel #define tcg_gen_shl_i32 tcg_gen_shl_i32_mipsel #define tcg_gen_shl_i64 tcg_gen_shl_i64_mipsel #define tcg_gen_shli_i32 tcg_gen_shli_i32_mipsel @@ -2780,14 +2837,20 @@ #define tcg_gen_shri_i64 tcg_gen_shri_i64_mipsel #define tcg_gen_st_i32 tcg_gen_st_i32_mipsel #define tcg_gen_st_i64 tcg_gen_st_i64_mipsel +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_mipsel +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_mipsel #define tcg_gen_sub_i32 tcg_gen_sub_i32_mipsel #define tcg_gen_sub_i64 tcg_gen_sub_i64_mipsel +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_mipsel +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mipsel #define tcg_gen_subi_i32 tcg_gen_subi_i32_mipsel +#define tcg_gen_subi_i64 tcg_gen_subi_i64_mipsel #define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_mipsel #define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_mipsel #define tcg_gen_xor_i32 tcg_gen_xor_i32_mipsel #define tcg_gen_xor_i64 tcg_gen_xor_i64_mipsel #define tcg_gen_xori_i32 tcg_gen_xori_i32_mipsel +#define tcg_gen_xori_i64 tcg_gen_xori_i64_mipsel #define tcg_get_arg_str_i32 tcg_get_arg_str_i32_mipsel #define tcg_get_arg_str_i64 tcg_get_arg_str_i64_mipsel #define tcg_get_arg_str_idx tcg_get_arg_str_idx_mipsel diff --git a/qemu/powerpc.h b/qemu/powerpc.h index 998f1f3b..a08b8e90 100644 --- a/qemu/powerpc.h +++ b/qemu/powerpc.h @@ -2690,11 +2690,13 @@ #define tcg_func_start tcg_func_start_powerpc #define tcg_gen_abs_i32 tcg_gen_abs_i32_powerpc #define tcg_gen_add2_i32 tcg_gen_add2_i32_powerpc +#define tcg_gen_add2_i64 tcg_gen_add2_i64_powerpc #define tcg_gen_add_i32 tcg_gen_add_i32_powerpc #define tcg_gen_add_i64 tcg_gen_add_i64_powerpc #define tcg_gen_addi_i32 tcg_gen_addi_i32_powerpc #define tcg_gen_addi_i64 tcg_gen_addi_i64_powerpc #define tcg_gen_andc_i32 tcg_gen_andc_i32_powerpc +#define tcg_gen_andc_i64 tcg_gen_andc_i64_powerpc #define tcg_gen_and_i32 tcg_gen_and_i32_powerpc #define tcg_gen_and_i64 tcg_gen_and_i64_powerpc #define tcg_gen_andi_i32 tcg_gen_andi_i32_powerpc @@ -2703,8 +2705,12 @@ #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_powerpc #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_powerpc #define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_powerpc +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_powerpc #define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_powerpc +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_powerpc #define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_powerpc +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_powerpc +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_powerpc #define tcg_gen_callN tcg_gen_callN_powerpc #define tcg_gen_code tcg_gen_code_powerpc #define tcg_gen_code_common tcg_gen_code_common_powerpc @@ -2712,16 +2718,36 @@ #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_powerpc #define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_powerpc #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_powerpc +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_powerpc +#define tcg_gen_discard_i64 tcg_gen_discard_i64_powerpc +#define tcg_gen_div_i32 tcg_gen_div_i32_powerpc +#define tcg_gen_div_i64 tcg_gen_div_i64_powerpc +#define tcg_gen_divu_i32 tcg_gen_divu_i32_powerpc +#define tcg_gen_divu_i64 tcg_gen_divu_i64_powerpc +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_powerpc +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_powerpc #define tcg_gen_exit_tb tcg_gen_exit_tb_powerpc #define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_powerpc +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_powerpc #define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_powerpc +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_powerpc #define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_powerpc #define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_powerpc #define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_powerpc +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_powerpc #define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_powerpc +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_powerpc #define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_powerpc +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_powerpc +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_powerpc #define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_powerpc #define tcg_gen_goto_tb tcg_gen_goto_tb_powerpc +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_powerpc +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_powerpc +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_powerpc +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_powerpc +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_powerpc +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_powerpc #define tcg_gen_ld_i32 tcg_gen_ld_i32_powerpc #define tcg_gen_ld_i64 tcg_gen_ld_i64_powerpc #define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_powerpc @@ -2733,12 +2759,28 @@ #define tcg_gen_movi_i32 tcg_gen_movi_i32_powerpc #define tcg_gen_movi_i64 tcg_gen_movi_i64_powerpc #define tcg_gen_mul_i32 tcg_gen_mul_i32_powerpc +#define tcg_gen_mul_i64 tcg_gen_mul_i64_powerpc +#define tcg_gen_muli_i32 tcg_gen_muli_i32_powerpc +#define tcg_gen_muli_i64 tcg_gen_muli_i64_powerpc #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_powerpc +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_powerpc #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_powerpc +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_powerpc +#define tcg_gen_nand_i32 tcg_gen_nand_i32_powerpc +#define tcg_gen_nand_i64 tcg_gen_nand_i64_powerpc #define tcg_gen_neg_i32 tcg_gen_neg_i32_powerpc #define tcg_gen_neg_i64 tcg_gen_neg_i64_powerpc +#define tcg_gen_nor_i32 tcg_gen_nor_i32_powerpc +#define tcg_gen_nor_i64 tcg_gen_nor_i64_powerpc #define tcg_gen_not_i32 tcg_gen_not_i32_powerpc +#define tcg_gen_not_i64 tcg_gen_not_i64_powerpc #define tcg_gen_op0 tcg_gen_op0_powerpc +#define tcg_gen_op1 tcg_gen_op1_powerpc +#define tcg_gen_op2 tcg_gen_op2_powerpc +#define tcg_gen_op3 tcg_gen_op3_powerpc +#define tcg_gen_op4 tcg_gen_op4_powerpc +#define tcg_gen_op5 tcg_gen_op5_powerpc +#define tcg_gen_op6 tcg_gen_op6_powerpc #define tcg_gen_op1i tcg_gen_op1i_powerpc #define tcg_gen_op2_i32 tcg_gen_op2_i32_powerpc #define tcg_gen_op2_i64 tcg_gen_op2_i64_powerpc @@ -2755,20 +2797,35 @@ #define tcg_gen_op6i_i32 tcg_gen_op6i_i32_powerpc #define tcg_gen_op6i_i64 tcg_gen_op6i_i64_powerpc #define tcg_gen_orc_i32 tcg_gen_orc_i32_powerpc +#define tcg_gen_orc_i64 tcg_gen_orc_i64_powerpc #define tcg_gen_or_i32 tcg_gen_or_i32_powerpc #define tcg_gen_or_i64 tcg_gen_or_i64_powerpc #define tcg_gen_ori_i32 tcg_gen_ori_i32_powerpc +#define tcg_gen_ori_i64 tcg_gen_ori_i64_powerpc #define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_powerpc #define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_powerpc #define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_powerpc #define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_powerpc +#define tcg_gen_rem_i32 tcg_gen_rem_i32_powerpc +#define tcg_gen_rem_i64 tcg_gen_rem_i64_powerpc +#define tcg_gen_remu_i32 tcg_gen_remu_i32_powerpc +#define tcg_gen_remu_i64 tcg_gen_remu_i64_powerpc #define tcg_gen_rotl_i32 tcg_gen_rotl_i32_powerpc +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_powerpc #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_powerpc +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_powerpc #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_powerpc +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_powerpc #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_powerpc +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_powerpc #define tcg_gen_sar_i32 tcg_gen_sar_i32_powerpc +#define tcg_gen_sar_i64 tcg_gen_sar_i64_powerpc #define tcg_gen_sari_i32 tcg_gen_sari_i32_powerpc +#define tcg_gen_sari_i64 tcg_gen_sari_i64_powerpc #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_powerpc +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_powerpc +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_powerpc +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_powerpc #define tcg_gen_shl_i32 tcg_gen_shl_i32_powerpc #define tcg_gen_shl_i64 tcg_gen_shl_i64_powerpc #define tcg_gen_shli_i32 tcg_gen_shli_i32_powerpc @@ -2780,14 +2837,20 @@ #define tcg_gen_shri_i64 tcg_gen_shri_i64_powerpc #define tcg_gen_st_i32 tcg_gen_st_i32_powerpc #define tcg_gen_st_i64 tcg_gen_st_i64_powerpc +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_powerpc +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_powerpc #define tcg_gen_sub_i32 tcg_gen_sub_i32_powerpc #define tcg_gen_sub_i64 tcg_gen_sub_i64_powerpc +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_powerpc +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_powerpc #define tcg_gen_subi_i32 tcg_gen_subi_i32_powerpc +#define tcg_gen_subi_i64 tcg_gen_subi_i64_powerpc #define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_powerpc #define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_powerpc #define tcg_gen_xor_i32 tcg_gen_xor_i32_powerpc #define tcg_gen_xor_i64 tcg_gen_xor_i64_powerpc #define tcg_gen_xori_i32 tcg_gen_xori_i32_powerpc +#define tcg_gen_xori_i64 tcg_gen_xori_i64_powerpc #define tcg_get_arg_str_i32 tcg_get_arg_str_i32_powerpc #define tcg_get_arg_str_i64 tcg_get_arg_str_i64_powerpc #define tcg_get_arg_str_idx tcg_get_arg_str_idx_powerpc diff --git a/qemu/sparc.h b/qemu/sparc.h index 4fbf55e7..fd3c016e 100644 --- a/qemu/sparc.h +++ b/qemu/sparc.h @@ -2690,11 +2690,13 @@ #define tcg_func_start tcg_func_start_sparc #define tcg_gen_abs_i32 tcg_gen_abs_i32_sparc #define tcg_gen_add2_i32 tcg_gen_add2_i32_sparc +#define tcg_gen_add2_i64 tcg_gen_add2_i64_sparc #define tcg_gen_add_i32 tcg_gen_add_i32_sparc #define tcg_gen_add_i64 tcg_gen_add_i64_sparc #define tcg_gen_addi_i32 tcg_gen_addi_i32_sparc #define tcg_gen_addi_i64 tcg_gen_addi_i64_sparc #define tcg_gen_andc_i32 tcg_gen_andc_i32_sparc +#define tcg_gen_andc_i64 tcg_gen_andc_i64_sparc #define tcg_gen_and_i32 tcg_gen_and_i32_sparc #define tcg_gen_and_i64 tcg_gen_and_i64_sparc #define tcg_gen_andi_i32 tcg_gen_andi_i32_sparc @@ -2703,8 +2705,12 @@ #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_sparc #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_sparc #define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_sparc +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_sparc #define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_sparc +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_sparc #define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_sparc +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_sparc +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_sparc #define tcg_gen_callN tcg_gen_callN_sparc #define tcg_gen_code tcg_gen_code_sparc #define tcg_gen_code_common tcg_gen_code_common_sparc @@ -2712,16 +2718,36 @@ #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_sparc #define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_sparc #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_sparc +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_sparc +#define tcg_gen_discard_i64 tcg_gen_discard_i64_sparc +#define tcg_gen_div_i32 tcg_gen_div_i32_sparc +#define tcg_gen_div_i64 tcg_gen_div_i64_sparc +#define tcg_gen_divu_i32 tcg_gen_divu_i32_sparc +#define tcg_gen_divu_i64 tcg_gen_divu_i64_sparc +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_sparc +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_sparc #define tcg_gen_exit_tb tcg_gen_exit_tb_sparc #define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_sparc +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_sparc #define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_sparc +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_sparc #define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_sparc #define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_sparc #define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_sparc +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_sparc #define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_sparc +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_sparc #define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_sparc +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_sparc +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_sparc #define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc #define tcg_gen_goto_tb tcg_gen_goto_tb_sparc +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_sparc +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_sparc +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_sparc +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_sparc +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_sparc +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_sparc #define tcg_gen_ld_i32 tcg_gen_ld_i32_sparc #define tcg_gen_ld_i64 tcg_gen_ld_i64_sparc #define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_sparc @@ -2733,12 +2759,28 @@ #define tcg_gen_movi_i32 tcg_gen_movi_i32_sparc #define tcg_gen_movi_i64 tcg_gen_movi_i64_sparc #define tcg_gen_mul_i32 tcg_gen_mul_i32_sparc +#define tcg_gen_mul_i64 tcg_gen_mul_i64_sparc +#define tcg_gen_muli_i32 tcg_gen_muli_i32_sparc +#define tcg_gen_muli_i64 tcg_gen_muli_i64_sparc #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_sparc +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_sparc #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_sparc +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_sparc +#define tcg_gen_nand_i32 tcg_gen_nand_i32_sparc +#define tcg_gen_nand_i64 tcg_gen_nand_i64_sparc #define tcg_gen_neg_i32 tcg_gen_neg_i32_sparc #define tcg_gen_neg_i64 tcg_gen_neg_i64_sparc +#define tcg_gen_nor_i32 tcg_gen_nor_i32_sparc +#define tcg_gen_nor_i64 tcg_gen_nor_i64_sparc #define tcg_gen_not_i32 tcg_gen_not_i32_sparc +#define tcg_gen_not_i64 tcg_gen_not_i64_sparc #define tcg_gen_op0 tcg_gen_op0_sparc +#define tcg_gen_op1 tcg_gen_op1_sparc +#define tcg_gen_op2 tcg_gen_op2_sparc +#define tcg_gen_op3 tcg_gen_op3_sparc +#define tcg_gen_op4 tcg_gen_op4_sparc +#define tcg_gen_op5 tcg_gen_op5_sparc +#define tcg_gen_op6 tcg_gen_op6_sparc #define tcg_gen_op1i tcg_gen_op1i_sparc #define tcg_gen_op2_i32 tcg_gen_op2_i32_sparc #define tcg_gen_op2_i64 tcg_gen_op2_i64_sparc @@ -2755,20 +2797,35 @@ #define tcg_gen_op6i_i32 tcg_gen_op6i_i32_sparc #define tcg_gen_op6i_i64 tcg_gen_op6i_i64_sparc #define tcg_gen_orc_i32 tcg_gen_orc_i32_sparc +#define tcg_gen_orc_i64 tcg_gen_orc_i64_sparc #define tcg_gen_or_i32 tcg_gen_or_i32_sparc #define tcg_gen_or_i64 tcg_gen_or_i64_sparc #define tcg_gen_ori_i32 tcg_gen_ori_i32_sparc +#define tcg_gen_ori_i64 tcg_gen_ori_i64_sparc #define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_sparc #define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_sparc #define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_sparc #define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_sparc +#define tcg_gen_rem_i32 tcg_gen_rem_i32_sparc +#define tcg_gen_rem_i64 tcg_gen_rem_i64_sparc +#define tcg_gen_remu_i32 tcg_gen_remu_i32_sparc +#define tcg_gen_remu_i64 tcg_gen_remu_i64_sparc #define tcg_gen_rotl_i32 tcg_gen_rotl_i32_sparc +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_sparc #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_sparc +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_sparc #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_sparc +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_sparc #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_sparc +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_sparc #define tcg_gen_sar_i32 tcg_gen_sar_i32_sparc +#define tcg_gen_sar_i64 tcg_gen_sar_i64_sparc #define tcg_gen_sari_i32 tcg_gen_sari_i32_sparc +#define tcg_gen_sari_i64 tcg_gen_sari_i64_sparc #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_sparc +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_sparc +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_sparc +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_sparc #define tcg_gen_shl_i32 tcg_gen_shl_i32_sparc #define tcg_gen_shl_i64 tcg_gen_shl_i64_sparc #define tcg_gen_shli_i32 tcg_gen_shli_i32_sparc @@ -2780,14 +2837,20 @@ #define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc #define tcg_gen_st_i32 tcg_gen_st_i32_sparc #define tcg_gen_st_i64 tcg_gen_st_i64_sparc +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_sparc +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_sparc #define tcg_gen_sub_i32 tcg_gen_sub_i32_sparc #define tcg_gen_sub_i64 tcg_gen_sub_i64_sparc +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_sparc +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc #define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc +#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc #define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_sparc #define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_sparc #define tcg_gen_xor_i32 tcg_gen_xor_i32_sparc #define tcg_gen_xor_i64 tcg_gen_xor_i64_sparc #define tcg_gen_xori_i32 tcg_gen_xori_i32_sparc +#define tcg_gen_xori_i64 tcg_gen_xori_i64_sparc #define tcg_get_arg_str_i32 tcg_get_arg_str_i32_sparc #define tcg_get_arg_str_i64 tcg_get_arg_str_i64_sparc #define tcg_get_arg_str_idx tcg_get_arg_str_idx_sparc diff --git a/qemu/sparc64.h b/qemu/sparc64.h index f3895222..848153cd 100644 --- a/qemu/sparc64.h +++ b/qemu/sparc64.h @@ -2690,11 +2690,13 @@ #define tcg_func_start tcg_func_start_sparc64 #define tcg_gen_abs_i32 tcg_gen_abs_i32_sparc64 #define tcg_gen_add2_i32 tcg_gen_add2_i32_sparc64 +#define tcg_gen_add2_i64 tcg_gen_add2_i64_sparc64 #define tcg_gen_add_i32 tcg_gen_add_i32_sparc64 #define tcg_gen_add_i64 tcg_gen_add_i64_sparc64 #define tcg_gen_addi_i32 tcg_gen_addi_i32_sparc64 #define tcg_gen_addi_i64 tcg_gen_addi_i64_sparc64 #define tcg_gen_andc_i32 tcg_gen_andc_i32_sparc64 +#define tcg_gen_andc_i64 tcg_gen_andc_i64_sparc64 #define tcg_gen_and_i32 tcg_gen_and_i32_sparc64 #define tcg_gen_and_i64 tcg_gen_and_i64_sparc64 #define tcg_gen_andi_i32 tcg_gen_andi_i32_sparc64 @@ -2703,8 +2705,12 @@ #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_sparc64 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_sparc64 #define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_sparc64 +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_sparc64 #define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_sparc64 +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_sparc64 #define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_sparc64 +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_sparc64 +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_sparc64 #define tcg_gen_callN tcg_gen_callN_sparc64 #define tcg_gen_code tcg_gen_code_sparc64 #define tcg_gen_code_common tcg_gen_code_common_sparc64 @@ -2712,16 +2718,36 @@ #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_sparc64 #define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_sparc64 #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_sparc64 +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_sparc64 +#define tcg_gen_discard_i64 tcg_gen_discard_i64_sparc64 +#define tcg_gen_div_i32 tcg_gen_div_i32_sparc64 +#define tcg_gen_div_i64 tcg_gen_div_i64_sparc64 +#define tcg_gen_divu_i32 tcg_gen_divu_i32_sparc64 +#define tcg_gen_divu_i64 tcg_gen_divu_i64_sparc64 +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_sparc64 +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_sparc64 #define tcg_gen_exit_tb tcg_gen_exit_tb_sparc64 #define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_sparc64 +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_sparc64 #define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_sparc64 +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_sparc64 #define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_sparc64 #define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_sparc64 #define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_sparc64 +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_sparc64 #define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_sparc64 +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_sparc64 #define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_sparc64 +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_sparc64 +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_sparc64 #define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc64 #define tcg_gen_goto_tb tcg_gen_goto_tb_sparc64 +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_sparc64 +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_sparc64 +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_sparc64 +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_sparc64 +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_sparc64 +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_sparc64 #define tcg_gen_ld_i32 tcg_gen_ld_i32_sparc64 #define tcg_gen_ld_i64 tcg_gen_ld_i64_sparc64 #define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_sparc64 @@ -2733,12 +2759,28 @@ #define tcg_gen_movi_i32 tcg_gen_movi_i32_sparc64 #define tcg_gen_movi_i64 tcg_gen_movi_i64_sparc64 #define tcg_gen_mul_i32 tcg_gen_mul_i32_sparc64 +#define tcg_gen_mul_i64 tcg_gen_mul_i64_sparc64 +#define tcg_gen_muli_i32 tcg_gen_muli_i32_sparc64 +#define tcg_gen_muli_i64 tcg_gen_muli_i64_sparc64 #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_sparc64 +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_sparc64 #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_sparc64 +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_sparc64 +#define tcg_gen_nand_i32 tcg_gen_nand_i32_sparc64 +#define tcg_gen_nand_i64 tcg_gen_nand_i64_sparc64 #define tcg_gen_neg_i32 tcg_gen_neg_i32_sparc64 #define tcg_gen_neg_i64 tcg_gen_neg_i64_sparc64 +#define tcg_gen_nor_i32 tcg_gen_nor_i32_sparc64 +#define tcg_gen_nor_i64 tcg_gen_nor_i64_sparc64 #define tcg_gen_not_i32 tcg_gen_not_i32_sparc64 +#define tcg_gen_not_i64 tcg_gen_not_i64_sparc64 #define tcg_gen_op0 tcg_gen_op0_sparc64 +#define tcg_gen_op1 tcg_gen_op1_sparc64 +#define tcg_gen_op2 tcg_gen_op2_sparc64 +#define tcg_gen_op3 tcg_gen_op3_sparc64 +#define tcg_gen_op4 tcg_gen_op4_sparc64 +#define tcg_gen_op5 tcg_gen_op5_sparc64 +#define tcg_gen_op6 tcg_gen_op6_sparc64 #define tcg_gen_op1i tcg_gen_op1i_sparc64 #define tcg_gen_op2_i32 tcg_gen_op2_i32_sparc64 #define tcg_gen_op2_i64 tcg_gen_op2_i64_sparc64 @@ -2755,20 +2797,35 @@ #define tcg_gen_op6i_i32 tcg_gen_op6i_i32_sparc64 #define tcg_gen_op6i_i64 tcg_gen_op6i_i64_sparc64 #define tcg_gen_orc_i32 tcg_gen_orc_i32_sparc64 +#define tcg_gen_orc_i64 tcg_gen_orc_i64_sparc64 #define tcg_gen_or_i32 tcg_gen_or_i32_sparc64 #define tcg_gen_or_i64 tcg_gen_or_i64_sparc64 #define tcg_gen_ori_i32 tcg_gen_ori_i32_sparc64 +#define tcg_gen_ori_i64 tcg_gen_ori_i64_sparc64 #define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_sparc64 #define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_sparc64 #define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_sparc64 #define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_sparc64 +#define tcg_gen_rem_i32 tcg_gen_rem_i32_sparc64 +#define tcg_gen_rem_i64 tcg_gen_rem_i64_sparc64 +#define tcg_gen_remu_i32 tcg_gen_remu_i32_sparc64 +#define tcg_gen_remu_i64 tcg_gen_remu_i64_sparc64 #define tcg_gen_rotl_i32 tcg_gen_rotl_i32_sparc64 +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_sparc64 #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_sparc64 +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_sparc64 #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_sparc64 +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_sparc64 #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_sparc64 +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_sparc64 #define tcg_gen_sar_i32 tcg_gen_sar_i32_sparc64 +#define tcg_gen_sar_i64 tcg_gen_sar_i64_sparc64 #define tcg_gen_sari_i32 tcg_gen_sari_i32_sparc64 +#define tcg_gen_sari_i64 tcg_gen_sari_i64_sparc64 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_sparc64 +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_sparc64 +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_sparc64 +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_sparc64 #define tcg_gen_shl_i32 tcg_gen_shl_i32_sparc64 #define tcg_gen_shl_i64 tcg_gen_shl_i64_sparc64 #define tcg_gen_shli_i32 tcg_gen_shli_i32_sparc64 @@ -2780,14 +2837,20 @@ #define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc64 #define tcg_gen_st_i32 tcg_gen_st_i32_sparc64 #define tcg_gen_st_i64 tcg_gen_st_i64_sparc64 +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_sparc64 +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_sparc64 #define tcg_gen_sub_i32 tcg_gen_sub_i32_sparc64 #define tcg_gen_sub_i64 tcg_gen_sub_i64_sparc64 +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_sparc64 +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc64 #define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc64 +#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc64 #define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_sparc64 #define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_sparc64 #define tcg_gen_xor_i32 tcg_gen_xor_i32_sparc64 #define tcg_gen_xor_i64 tcg_gen_xor_i64_sparc64 #define tcg_gen_xori_i32 tcg_gen_xori_i32_sparc64 +#define tcg_gen_xori_i64 tcg_gen_xori_i64_sparc64 #define tcg_get_arg_str_i32 tcg_get_arg_str_i32_sparc64 #define tcg_get_arg_str_i64 tcg_get_arg_str_i64_sparc64 #define tcg_get_arg_str_idx tcg_get_arg_str_idx_sparc64 diff --git a/qemu/tcg/tcg-op.c b/qemu/tcg/tcg-op.c new file mode 100644 index 00000000..63848195 --- /dev/null +++ b/qemu/tcg/tcg-op.c @@ -0,0 +1,2011 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2008 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "tcg.h" +#include "tcg-op.h" + + +void tcg_gen_op0(TCGContext *ctx, TCGOpcode opc) +{ + *ctx->gen_opc_ptr++ = opc; +} + +void tcg_gen_op1(TCGContext *ctx, TCGOpcode opc, TCGArg a1) +{ + uint16_t *op = ctx->gen_opc_ptr; + TCGArg *opp = ctx->gen_opparam_ptr; + + op[0] = opc; + opp[0] = a1; + + ctx->gen_opc_ptr = op + 1; + ctx->gen_opparam_ptr = opp + 1; +} + +void tcg_gen_op2(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2) +{ + uint16_t *op = ctx->gen_opc_ptr; + TCGArg *opp = ctx->gen_opparam_ptr; + + op[0] = opc; + opp[0] = a1; + opp[1] = a2; + + ctx->gen_opc_ptr = op + 1; + ctx->gen_opparam_ptr = opp + 2; +} + +void tcg_gen_op3(TCGContext *ctx, TCGOpcode opc, TCGArg a1, + TCGArg a2, TCGArg a3) +{ + uint16_t *op = ctx->gen_opc_ptr; + TCGArg *opp = ctx->gen_opparam_ptr; + + op[0] = opc; + opp[0] = a1; + opp[1] = a2; + opp[2] = a3; + + ctx->gen_opc_ptr = op + 1; + ctx->gen_opparam_ptr = opp + 3; +} + +void tcg_gen_op4(TCGContext *ctx, TCGOpcode opc, TCGArg a1, + TCGArg a2, TCGArg a3, TCGArg a4) +{ + uint16_t *op = ctx->gen_opc_ptr; + TCGArg *opp = ctx->gen_opparam_ptr; + + op[0] = opc; + opp[0] = a1; + opp[1] = a2; + opp[2] = a3; + opp[3] = a4; + + ctx->gen_opc_ptr = op + 1; + ctx->gen_opparam_ptr = opp + 4; +} + +void tcg_gen_op5(TCGContext *ctx, TCGOpcode opc, TCGArg a1, + TCGArg a2, TCGArg a3, TCGArg a4, TCGArg a5) +{ + uint16_t *op = ctx->gen_opc_ptr; + TCGArg *opp = ctx->gen_opparam_ptr; + + op[0] = opc; + opp[0] = a1; + opp[1] = a2; + opp[2] = a3; + opp[3] = a4; + opp[4] = a5; + + ctx->gen_opc_ptr = op + 1; + ctx->gen_opparam_ptr = opp + 5; +} + +void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2, + TCGArg a3, TCGArg a4, TCGArg a5, TCGArg a6) +{ + uint16_t *op = ctx->gen_opc_ptr; + TCGArg *opp = ctx->gen_opparam_ptr; + + op[0] = opc; + opp[0] = a1; + opp[1] = a2; + opp[2] = a3; + opp[3] = a4; + opp[4] = a5; + opp[5] = a6; + + ctx->gen_opc_ptr = op + 1; + ctx->gen_opparam_ptr = opp + 6; +} + +/* 32 bit ops */ + +void tcg_gen_addi_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) +{ + /* some cases can be optimized here */ + if (arg2 == 0) { + tcg_gen_mov_i32(s, ret, arg1); + } else { + TCGv_i32 t0 = tcg_const_i32(s, arg2); + tcg_gen_add_i32(s, ret, arg1, t0); + tcg_temp_free_i32(s, t0); + } +} + +void tcg_gen_subfi_i32(TCGContext *s, TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) +{ + if (arg1 == 0 && TCG_TARGET_HAS_neg_i32) { + /* Don't recurse with tcg_gen_neg_i32. */ + tcg_gen_op2_i32(s, INDEX_op_neg_i32, ret, arg2); + } else { + TCGv_i32 t0 = tcg_const_i32(s, arg1); + tcg_gen_sub_i32(s, ret, t0, arg2); + tcg_temp_free_i32(s, t0); + } +} + +void tcg_gen_subi_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) +{ + /* some cases can be optimized here */ + if (arg2 == 0) { + tcg_gen_mov_i32(s, ret, arg1); + } else { + TCGv_i32 t0 = tcg_const_i32(s, arg2); + tcg_gen_sub_i32(s, ret, arg1, t0); + tcg_temp_free_i32(s, t0); + } +} + +void tcg_gen_andi_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) +{ + TCGv_i32 t0; + /* Some cases can be optimized here. */ + switch (arg2) { + case 0: + tcg_gen_movi_i32(s, ret, 0); + return; + case 0xffffffffu: + tcg_gen_mov_i32(s, ret, arg1); + return; + case 0xffu: + /* Don't recurse with tcg_gen_ext8u_i32. */ + if (TCG_TARGET_HAS_ext8u_i32) { + tcg_gen_op2_i32(s, INDEX_op_ext8u_i32, ret, arg1); + return; + } + break; + case 0xffffu: + if (TCG_TARGET_HAS_ext16u_i32) { + tcg_gen_op2_i32(s, INDEX_op_ext16u_i32, ret, arg1); + return; + } + break; + } + t0 = tcg_const_i32(s, arg2); + tcg_gen_and_i32(s, ret, arg1, t0); + tcg_temp_free_i32(s, t0); +} + +void tcg_gen_ori_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) +{ + /* Some cases can be optimized here. */ + if (arg2 == -1) { + tcg_gen_movi_i32(s, ret, -1); + } else if (arg2 == 0) { + tcg_gen_mov_i32(s, ret, arg1); + } else { + TCGv_i32 t0 = tcg_const_i32(s, arg2); + tcg_gen_or_i32(s, ret, arg1, t0); + tcg_temp_free_i32(s, t0); + } +} + +void tcg_gen_xori_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) +{ + /* Some cases can be optimized here. */ + if (arg2 == 0) { + tcg_gen_mov_i32(s, ret, arg1); + } else if (arg2 == -1 && TCG_TARGET_HAS_not_i32) { + /* Don't recurse with tcg_gen_not_i32. */ + tcg_gen_op2_i32(s, INDEX_op_not_i32, ret, arg1); + } else { + TCGv_i32 t0 = tcg_const_i32(s, arg2); + tcg_gen_xor_i32(s, ret, arg1, t0); + tcg_temp_free_i32(s, t0); + } +} + +void tcg_gen_shli_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2) +{ + tcg_debug_assert(arg2 < 32); + if (arg2 == 0) { + tcg_gen_mov_i32(s, ret, arg1); + } else { + TCGv_i32 t0 = tcg_const_i32(s, arg2); + tcg_gen_shl_i32(s, ret, arg1, t0); + tcg_temp_free_i32(s, t0); + } +} + +void tcg_gen_shri_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2) +{ + tcg_debug_assert(arg2 < 32); + if (arg2 == 0) { + tcg_gen_mov_i32(s, ret, arg1); + } else { + TCGv_i32 t0 = tcg_const_i32(s, arg2); + tcg_gen_shr_i32(s, ret, arg1, t0); + tcg_temp_free_i32(s, t0); + } +} + +void tcg_gen_sari_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2) +{ + tcg_debug_assert(arg2 < 32); + if (arg2 == 0) { + tcg_gen_mov_i32(s, ret, arg1); + } else { + TCGv_i32 t0 = tcg_const_i32(s, arg2); + tcg_gen_sar_i32(s, ret, arg1, t0); + tcg_temp_free_i32(s, t0); + } +} + +void tcg_gen_brcond_i32(TCGContext *s, TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, int label) +{ + if (cond == TCG_COND_ALWAYS) { + tcg_gen_br(s, label); + } else if (cond != TCG_COND_NEVER) { + tcg_gen_op4ii_i32(s, INDEX_op_brcond_i32, arg1, arg2, cond, label); + } +} + +void tcg_gen_brcondi_i32(TCGContext *s, TCGCond cond, TCGv_i32 arg1, int32_t arg2, int label) +{ + TCGv_i32 t0 = tcg_const_i32(s, arg2); + tcg_gen_brcond_i32(s, cond, arg1, t0, label); + tcg_temp_free_i32(s, t0); +} + +void tcg_gen_setcond_i32(TCGContext *s, TCGCond cond, TCGv_i32 ret, + TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (cond == TCG_COND_ALWAYS) { + tcg_gen_movi_i32(s, ret, 1); + } else if (cond == TCG_COND_NEVER) { + tcg_gen_movi_i32(s, ret, 0); + } else { + tcg_gen_op4i_i32(s, INDEX_op_setcond_i32, ret, arg1, arg2, cond); + } +} + +void tcg_gen_setcondi_i32(TCGContext *s, TCGCond cond, TCGv_i32 ret, + TCGv_i32 arg1, int32_t arg2) +{ + TCGv_i32 t0 = tcg_const_i32(s, arg2); + tcg_gen_setcond_i32(s, cond, ret, arg1, t0); + tcg_temp_free_i32(s, t0); +} + +void tcg_gen_muli_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) +{ + TCGv_i32 t0 = tcg_const_i32(s, arg2); + tcg_gen_mul_i32(s, ret, arg1, t0); + tcg_temp_free_i32(s, t0); +} + +void tcg_gen_div_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_div_i32) { + tcg_gen_op3_i32(s, INDEX_op_div_i32, ret, arg1, arg2); + } else if (TCG_TARGET_HAS_div2_i32) { + TCGv_i32 t0 = tcg_temp_new_i32(s); + tcg_gen_sari_i32(s, t0, arg1, 31); + tcg_gen_op5_i32(s, INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); + tcg_temp_free_i32(s, t0); + } else { + gen_helper_div_i32(s, ret, arg1, arg2); + } +} + +void tcg_gen_rem_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_rem_i32) { + tcg_gen_op3_i32(s, INDEX_op_rem_i32, ret, arg1, arg2); + } else if (TCG_TARGET_HAS_div_i32) { + TCGv_i32 t0 = tcg_temp_new_i32(s); + tcg_gen_op3_i32(s, INDEX_op_div_i32, t0, arg1, arg2); + tcg_gen_mul_i32(s, t0, t0, arg2); + tcg_gen_sub_i32(s, ret, arg1, t0); + tcg_temp_free_i32(s, t0); + } else if (TCG_TARGET_HAS_div2_i32) { + TCGv_i32 t0 = tcg_temp_new_i32(s); + tcg_gen_sari_i32(s, t0, arg1, 31); + tcg_gen_op5_i32(s, INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); + tcg_temp_free_i32(s, t0); + } else { + gen_helper_rem_i32(s, ret, arg1, arg2); + } +} + +void tcg_gen_divu_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_div_i32) { + tcg_gen_op3_i32(s, INDEX_op_divu_i32, ret, arg1, arg2); + } else if (TCG_TARGET_HAS_div2_i32) { + TCGv_i32 t0 = tcg_temp_new_i32(s); + tcg_gen_movi_i32(s, t0, 0); + tcg_gen_op5_i32(s, INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); + tcg_temp_free_i32(s, t0); + } else { + gen_helper_divu_i32(s, ret, arg1, arg2); + } +} + +void tcg_gen_remu_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_rem_i32) { + tcg_gen_op3_i32(s, INDEX_op_remu_i32, ret, arg1, arg2); + } else if (TCG_TARGET_HAS_div_i32) { + TCGv_i32 t0 = tcg_temp_new_i32(s); + tcg_gen_op3_i32(s, INDEX_op_divu_i32, t0, arg1, arg2); + tcg_gen_mul_i32(s, t0, t0, arg2); + tcg_gen_sub_i32(s, ret, arg1, t0); + tcg_temp_free_i32(s, t0); + } else if (TCG_TARGET_HAS_div2_i32) { + TCGv_i32 t0 = tcg_temp_new_i32(s); + tcg_gen_movi_i32(s, t0, 0); + tcg_gen_op5_i32(s, INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); + tcg_temp_free_i32(s, t0); + } else { + gen_helper_remu_i32(s, ret, arg1, arg2); + } +} + +void tcg_gen_andc_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_andc_i32) { + tcg_gen_op3_i32(s, INDEX_op_andc_i32, ret, arg1, arg2); + } else { + TCGv_i32 t0 = tcg_temp_new_i32(s); + tcg_gen_not_i32(s, t0, arg2); + tcg_gen_and_i32(s, ret, arg1, t0); + tcg_temp_free_i32(s, t0); + } +} + +void tcg_gen_eqv_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_eqv_i32) { + tcg_gen_op3_i32(s, INDEX_op_eqv_i32, ret, arg1, arg2); + } else { + tcg_gen_xor_i32(s, ret, arg1, arg2); + tcg_gen_not_i32(s, ret, ret); + } +} + +void tcg_gen_nand_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_nand_i32) { + tcg_gen_op3_i32(s, INDEX_op_nand_i32, ret, arg1, arg2); + } else { + tcg_gen_and_i32(s, ret, arg1, arg2); + tcg_gen_not_i32(s, ret, ret); + } +} + +void tcg_gen_nor_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_nor_i32) { + tcg_gen_op3_i32(s, INDEX_op_nor_i32, ret, arg1, arg2); + } else { + tcg_gen_or_i32(s, ret, arg1, arg2); + tcg_gen_not_i32(s, ret, ret); + } +} + +void tcg_gen_orc_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_orc_i32) { + tcg_gen_op3_i32(s, INDEX_op_orc_i32, ret, arg1, arg2); + } else { + TCGv_i32 t0 = tcg_temp_new_i32(s); + tcg_gen_not_i32(s, t0, arg2); + tcg_gen_or_i32(s, ret, arg1, t0); + tcg_temp_free_i32(s, t0); + } +} + +void tcg_gen_rotl_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_rot_i32) { + tcg_gen_op3_i32(s, INDEX_op_rotl_i32, ret, arg1, arg2); + } else { + TCGv_i32 t0, t1; + + t0 = tcg_temp_new_i32(s); + t1 = tcg_temp_new_i32(s); + tcg_gen_shl_i32(s, t0, arg1, arg2); + tcg_gen_subfi_i32(s, t1, 32, arg2); + tcg_gen_shr_i32(s, t1, arg1, t1); + tcg_gen_or_i32(s, ret, t0, t1); + tcg_temp_free_i32(s, t0); + tcg_temp_free_i32(s, t1); + } +} + +void tcg_gen_rotli_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2) +{ + tcg_debug_assert(arg2 < 32); + /* some cases can be optimized here */ + if (arg2 == 0) { + tcg_gen_mov_i32(s, ret, arg1); + } else if (TCG_TARGET_HAS_rot_i32) { + TCGv_i32 t0 = tcg_const_i32(s, arg2); + tcg_gen_rotl_i32(s, ret, arg1, t0); + tcg_temp_free_i32(s, t0); + } else { + TCGv_i32 t0, t1; + t0 = tcg_temp_new_i32(s); + t1 = tcg_temp_new_i32(s); + tcg_gen_shli_i32(s, t0, arg1, arg2); + tcg_gen_shri_i32(s, t1, arg1, 32 - arg2); + tcg_gen_or_i32(s, ret, t0, t1); + tcg_temp_free_i32(s, t0); + tcg_temp_free_i32(s, t1); + } +} + +void tcg_gen_rotr_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_rot_i32) { + tcg_gen_op3_i32(s, INDEX_op_rotr_i32, ret, arg1, arg2); + } else { + TCGv_i32 t0, t1; + + t0 = tcg_temp_new_i32(s); + t1 = tcg_temp_new_i32(s); + tcg_gen_shr_i32(s, t0, arg1, arg2); + tcg_gen_subfi_i32(s, t1, 32, arg2); + tcg_gen_shl_i32(s, t1, arg1, t1); + tcg_gen_or_i32(s, ret, t0, t1); + tcg_temp_free_i32(s, t0); + tcg_temp_free_i32(s, t1); + } +} + +void tcg_gen_rotri_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2) +{ + tcg_debug_assert(arg2 < 32); + /* some cases can be optimized here */ + if (arg2 == 0) { + tcg_gen_mov_i32(s, ret, arg1); + } else { + tcg_gen_rotli_i32(s, ret, arg1, 32 - arg2); + } +} + +void tcg_gen_deposit_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, + unsigned int ofs, unsigned int len) +{ + uint32_t mask; + TCGv_i32 t1; + + tcg_debug_assert(ofs < 32); + tcg_debug_assert(len <= 32); + tcg_debug_assert(ofs + len <= 32); + + if (ofs == 0 && len == 32) { + tcg_gen_mov_i32(s, ret, arg2); + return; + } + if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) { + tcg_gen_op5ii_i32(s, INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len); + return; + } + + mask = (1u << len) - 1; + t1 = tcg_temp_new_i32(s); + + if (ofs + len < 32) { + tcg_gen_andi_i32(s, t1, arg2, mask); + tcg_gen_shli_i32(s, t1, t1, ofs); + } else { + tcg_gen_shli_i32(s, t1, arg2, ofs); + } + tcg_gen_andi_i32(s, ret, arg1, ~(mask << ofs)); + tcg_gen_or_i32(s, ret, ret, t1); + + tcg_temp_free_i32(s, t1); +} + +void tcg_gen_movcond_i32(TCGContext *s, TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, + TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2) +{ + if (TCG_TARGET_HAS_movcond_i32) { + tcg_gen_op6i_i32(s, INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond); + } else { + TCGv_i32 t0 = tcg_temp_new_i32(s); + TCGv_i32 t1 = tcg_temp_new_i32(s); + tcg_gen_setcond_i32(s, cond, t0, c1, c2); + tcg_gen_neg_i32(s, t0, t0); + tcg_gen_and_i32(s, t1, v1, t0); + tcg_gen_andc_i32(s, ret, v2, t0); + tcg_gen_or_i32(s, ret, ret, t1); + tcg_temp_free_i32(s, t0); + tcg_temp_free_i32(s, t1); + } +} + +void tcg_gen_add2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, + TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) +{ + if (TCG_TARGET_HAS_add2_i32) { + tcg_gen_op6_i32(s, INDEX_op_add2_i32, rl, rh, al, ah, bl, bh); + /* Allow the optimizer room to replace add2 with two moves. */ + tcg_gen_op0(s, INDEX_op_nop); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(s); + TCGv_i64 t1 = tcg_temp_new_i64(s); + tcg_gen_concat_i32_i64(s, t0, al, ah); + tcg_gen_concat_i32_i64(s, t1, bl, bh); + tcg_gen_add_i64(s, t0, t0, t1); + tcg_gen_extr_i64_i32(s, rl, rh, t0); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + } +} + +void tcg_gen_sub2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, + TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) +{ + if (TCG_TARGET_HAS_sub2_i32) { + tcg_gen_op6_i32(s, INDEX_op_sub2_i32, rl, rh, al, ah, bl, bh); + /* Allow the optimizer room to replace sub2 with two moves. */ + tcg_gen_op0(s, INDEX_op_nop); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(s); + TCGv_i64 t1 = tcg_temp_new_i64(s); + tcg_gen_concat_i32_i64(s, t0, al, ah); + tcg_gen_concat_i32_i64(s, t1, bl, bh); + tcg_gen_sub_i64(s, t0, t0, t1); + tcg_gen_extr_i64_i32(s, rl, rh, t0); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + } +} + +void tcg_gen_mulu2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_mulu2_i32) { + tcg_gen_op4_i32(s, INDEX_op_mulu2_i32, rl, rh, arg1, arg2); + /* Allow the optimizer room to replace mulu2 with two moves. */ + tcg_gen_op0(s, INDEX_op_nop); + } else if (TCG_TARGET_HAS_muluh_i32) { + TCGv_i32 t = tcg_temp_new_i32(s); + tcg_gen_op3_i32(s, INDEX_op_mul_i32, t, arg1, arg2); + tcg_gen_op3_i32(s, INDEX_op_muluh_i32, rh, arg1, arg2); + tcg_gen_mov_i32(s, rl, t); + tcg_temp_free_i32(s, t); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(s); + TCGv_i64 t1 = tcg_temp_new_i64(s); + tcg_gen_extu_i32_i64(s, t0, arg1); + tcg_gen_extu_i32_i64(s, t1, arg2); + tcg_gen_mul_i64(s, t0, t0, t1); + tcg_gen_extr_i64_i32(s, rl, rh, t0); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + } +} + +void tcg_gen_muls2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_muls2_i32) { + tcg_gen_op4_i32(s, INDEX_op_muls2_i32, rl, rh, arg1, arg2); + /* Allow the optimizer room to replace muls2 with two moves. */ + tcg_gen_op0(s, INDEX_op_nop); + } else if (TCG_TARGET_HAS_mulsh_i32) { + TCGv_i32 t = tcg_temp_new_i32(s); + tcg_gen_op3_i32(s, INDEX_op_mul_i32, t, arg1, arg2); + tcg_gen_op3_i32(s, INDEX_op_mulsh_i32, rh, arg1, arg2); + tcg_gen_mov_i32(s, rl, t); + tcg_temp_free_i32(s, t); + } else if (TCG_TARGET_REG_BITS == 32) { + TCGv_i32 t0 = tcg_temp_new_i32(s); + TCGv_i32 t1 = tcg_temp_new_i32(s); + TCGv_i32 t2 = tcg_temp_new_i32(s); + TCGv_i32 t3 = tcg_temp_new_i32(s); + tcg_gen_mulu2_i32(s, t0, t1, arg1, arg2); + /* Adjust for negative inputs. */ + tcg_gen_sari_i32(s, t2, arg1, 31); + tcg_gen_sari_i32(s, t3, arg2, 31); + tcg_gen_and_i32(s, t2, t2, arg2); + tcg_gen_and_i32(s, t3, t3, arg1); + tcg_gen_sub_i32(s, rh, t1, t2); + tcg_gen_sub_i32(s, rh, rh, t3); + tcg_gen_mov_i32(s, rl, t0); + tcg_temp_free_i32(s, t0); + tcg_temp_free_i32(s, t1); + tcg_temp_free_i32(s, t2); + tcg_temp_free_i32(s, t3); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(s); + TCGv_i64 t1 = tcg_temp_new_i64(s); + tcg_gen_ext_i32_i64(s, t0, arg1); + tcg_gen_ext_i32_i64(s, t1, arg2); + tcg_gen_mul_i64(s, t0, t0, t1); + tcg_gen_extr_i64_i32(s, rl, rh, t0); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + } +} + +void tcg_gen_ext8s_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) +{ + if (TCG_TARGET_HAS_ext8s_i32) { + tcg_gen_op2_i32(s, INDEX_op_ext8s_i32, ret, arg); + } else { + tcg_gen_shli_i32(s, ret, arg, 24); + tcg_gen_sari_i32(s, ret, ret, 24); + } +} + +void tcg_gen_ext16s_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) +{ + if (TCG_TARGET_HAS_ext16s_i32) { + tcg_gen_op2_i32(s, INDEX_op_ext16s_i32, ret, arg); + } else { + tcg_gen_shli_i32(s, ret, arg, 16); + tcg_gen_sari_i32(s, ret, ret, 16); + } +} + +void tcg_gen_ext8u_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) +{ + if (TCG_TARGET_HAS_ext8u_i32) { + tcg_gen_op2_i32(s, INDEX_op_ext8u_i32, ret, arg); + } else { + tcg_gen_andi_i32(s, ret, arg, 0xffu); + } +} + +void tcg_gen_ext16u_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) +{ + if (TCG_TARGET_HAS_ext16u_i32) { + tcg_gen_op2_i32(s, INDEX_op_ext16u_i32, ret, arg); + } else { + tcg_gen_andi_i32(s, ret, arg, 0xffffu); + } +} + +/* Note: we assume the two high bytes are set to zero */ +void tcg_gen_bswap16_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) +{ + if (TCG_TARGET_HAS_bswap16_i32) { + tcg_gen_op2_i32(s, INDEX_op_bswap16_i32, ret, arg); + } else { + TCGv_i32 t0 = tcg_temp_new_i32(s); + + tcg_gen_ext8u_i32(s, t0, arg); + tcg_gen_shli_i32(s, t0, t0, 8); + tcg_gen_shri_i32(s, ret, arg, 8); + tcg_gen_or_i32(s, ret, ret, t0); + tcg_temp_free_i32(s, t0); + } +} + +void tcg_gen_bswap32_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) +{ + if (TCG_TARGET_HAS_bswap32_i32) { + tcg_gen_op2_i32(s, INDEX_op_bswap32_i32, ret, arg); + } else { + TCGv_i32 t0, t1; + t0 = tcg_temp_new_i32(s); + t1 = tcg_temp_new_i32(s); + + tcg_gen_shli_i32(s, t0, arg, 24); + + tcg_gen_andi_i32(s, t1, arg, 0x0000ff00); + tcg_gen_shli_i32(s, t1, t1, 8); + tcg_gen_or_i32(s, t0, t0, t1); + + tcg_gen_shri_i32(s, t1, arg, 8); + tcg_gen_andi_i32(s, t1, t1, 0x0000ff00); + tcg_gen_or_i32(s, t0, t0, t1); + + tcg_gen_shri_i32(s, t1, arg, 24); + tcg_gen_or_i32(s, ret, t0, t1); + tcg_temp_free_i32(s, t0); + tcg_temp_free_i32(s, t1); + } +} + +/* 64-bit ops */ + +#if TCG_TARGET_REG_BITS == 32 +/* These are all inline for TCG_TARGET_REG_BITS == 64. */ + +void tcg_gen_discard_i64(TCGContext *s, TCGv_i64 arg) +{ + tcg_gen_discard_i32(s, TCGV_LOW(arg)); + tcg_gen_discard_i32(s, TCGV_HIGH(arg)); +} + +void tcg_gen_mov_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) +{ + tcg_gen_mov_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); + tcg_gen_mov_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg)); +} + +void tcg_gen_movi_i64(TCGContext *s, TCGv_i64 ret, int64_t arg) +{ + tcg_gen_movi_i32(s, TCGV_LOW(ret), arg); + tcg_gen_movi_i32(s, TCGV_HIGH(ret), arg >> 32); +} + +void tcg_gen_ld8u_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +{ + tcg_gen_ld8u_i32(s, TCGV_LOW(ret), arg2, offset); + tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); +} + +void tcg_gen_ld8s_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +{ + tcg_gen_ld8s_i32(s, TCGV_LOW(ret), arg2, offset); + tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_HIGH(ret), 31); +} + +void tcg_gen_ld16u_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +{ + tcg_gen_ld16u_i32(s, TCGV_LOW(ret), arg2, offset); + tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); +} + +void tcg_gen_ld16s_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +{ + tcg_gen_ld16s_i32(s, TCGV_LOW(ret), arg2, offset); + tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_LOW(ret), 31); +} + +void tcg_gen_ld32u_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +{ + tcg_gen_ld_i32(s, TCGV_LOW(ret), arg2, offset); + tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); +} + +void tcg_gen_ld32s_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +{ + tcg_gen_ld_i32(s, TCGV_LOW(ret), arg2, offset); + tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_LOW(ret), 31); +} + +void tcg_gen_ld_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +{ + /* Since arg2 and ret have different types, + they cannot be the same temporary */ +#ifdef TCG_TARGET_WORDS_BIGENDIAN + tcg_gen_ld_i32(s, TCGV_HIGH(ret), arg2, offset); + tcg_gen_ld_i32(s, TCGV_LOW(ret), arg2, offset + 4); +#else + tcg_gen_ld_i32(s, TCGV_LOW(ret), arg2, offset); + tcg_gen_ld_i32(s, TCGV_HIGH(ret), arg2, offset + 4); +#endif +} + +void tcg_gen_st_i64(TCGContext *s, TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) +{ +#ifdef TCG_TARGET_WORDS_BIGENDIAN + tcg_gen_st_i32(s, TCGV_HIGH(arg1), arg2, offset); + tcg_gen_st_i32(s, TCGV_LOW(arg1), arg2, offset + 4); +#else + tcg_gen_st_i32(s, TCGV_LOW(arg1), arg2, offset); + tcg_gen_st_i32(s, TCGV_HIGH(arg1), arg2, offset + 4); +#endif +} + +void tcg_gen_and_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + tcg_gen_and_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_and_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); +} + +void tcg_gen_or_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + tcg_gen_or_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_or_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); +} + +void tcg_gen_xor_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + tcg_gen_xor_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_xor_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); +} + +void tcg_gen_shl_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + gen_helper_shl_i64(s, ret, arg1, arg2); +} + +void tcg_gen_shr_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + gen_helper_shr_i64(s, ret, arg1, arg2); +} + +void tcg_gen_sar_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + gen_helper_sar_i64(s, ret, arg1, arg2); +} + +void tcg_gen_mul_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + TCGv_i64 t0; + TCGv_i32 t1; + + t0 = tcg_temp_new_i64(s); + t1 = tcg_temp_new_i32(s); + + tcg_gen_mulu2_i32(s, TCGV_LOW(t0), TCGV_HIGH(t0), + TCGV_LOW(arg1), TCGV_LOW(arg2)); + + tcg_gen_mul_i32(s, t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); + tcg_gen_add_i32(s, TCGV_HIGH(t0), TCGV_HIGH(t0), t1); + tcg_gen_mul_i32(s, t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); + tcg_gen_add_i32(s, TCGV_HIGH(t0), TCGV_HIGH(t0), t1); + + tcg_gen_mov_i64(s, ret, t0); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i32(s, t1); +} +#endif /* TCG_TARGET_REG_SIZE == 32 */ + +void tcg_gen_addi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) +{ + /* some cases can be optimized here */ + if (arg2 == 0) { + tcg_gen_mov_i64(s, ret, arg1); + } else { + TCGv_i64 t0 = tcg_const_i64(s, arg2); + tcg_gen_add_i64(s, ret, arg1, t0); + tcg_temp_free_i64(s, t0); + } +} + +void tcg_gen_subfi_i64(TCGContext *s, TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) +{ + if (arg1 == 0 && TCG_TARGET_HAS_neg_i64) { + /* Don't recurse with tcg_gen_neg_i64. */ + tcg_gen_op2_i64(s, INDEX_op_neg_i64, ret, arg2); + } else { + TCGv_i64 t0 = tcg_const_i64(s, arg1); + tcg_gen_sub_i64(s, ret, t0, arg2); + tcg_temp_free_i64(s, t0); + } +} + +void tcg_gen_subi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) +{ + /* some cases can be optimized here */ + if (arg2 == 0) { + tcg_gen_mov_i64(s, ret, arg1); + } else { + TCGv_i64 t0 = tcg_const_i64(s, arg2); + tcg_gen_sub_i64(s, ret, arg1, t0); + tcg_temp_free_i64(s, t0); + } +} + +void tcg_gen_andi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_andi_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), arg2); + tcg_gen_andi_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); +#else + TCGv_i64 t0; + /* Some cases can be optimized here. */ + switch (arg2) { + case 0: + tcg_gen_movi_i64(s, ret, 0); + return; + case 0xffffffffffffffffull: + tcg_gen_mov_i64(s, ret, arg1); + return; + case 0xffull: + /* Don't recurse with tcg_gen_ext8u_i64. */ + if (TCG_TARGET_HAS_ext8u_i64) { + tcg_gen_op2_i64(s, INDEX_op_ext8u_i64, ret, arg1); + return; + } + break; + case 0xffffu: + if (TCG_TARGET_HAS_ext16u_i64) { + tcg_gen_op2_i64(s, INDEX_op_ext16u_i64, ret, arg1); + return; + } + break; + case 0xffffffffull: + if (TCG_TARGET_HAS_ext32u_i64) { + tcg_gen_op2_i64(s, INDEX_op_ext32u_i64, ret, arg1); + return; + } + break; + } + t0 = tcg_const_i64(s, arg2); + tcg_gen_and_i64(s, ret, arg1, t0); + tcg_temp_free_i64(s, t0); +#endif +} + +void tcg_gen_ori_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_ori_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), arg2); + tcg_gen_ori_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); +#else + /* Some cases can be optimized here. */ + if (arg2 == -1) { + tcg_gen_movi_i64(s, ret, -1); + } else if (arg2 == 0) { + tcg_gen_mov_i64(s, ret, arg1); + } else { + TCGv_i64 t0 = tcg_const_i64(s, arg2); + tcg_gen_or_i64(s, ret, arg1, t0); + tcg_temp_free_i64(s, t0); + } +#endif +} + +void tcg_gen_xori_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_xori_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), arg2); + tcg_gen_xori_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); +#else + /* Some cases can be optimized here. */ + if (arg2 == 0) { + tcg_gen_mov_i64(s, ret, arg1); + } else if (arg2 == -1 && TCG_TARGET_HAS_not_i64) { + /* Don't recurse with tcg_gen_not_i64. */ + tcg_gen_op2_i64(s, INDEX_op_not_i64, ret, arg1); + } else { + TCGv_i64 t0 = tcg_const_i64(s, arg2); + tcg_gen_xor_i64(s, ret, arg1, t0); + tcg_temp_free_i64(s, t0); + } +#endif +} + +#if TCG_TARGET_REG_BITS == 32 +static inline void tcg_gen_shifti_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, + unsigned c, bool right, bool arith) +{ + tcg_debug_assert(c < 64); + if (c == 0) { + tcg_gen_mov_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1)); + tcg_gen_mov_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1)); + } else if (c >= 32) { + c -= 32; + if (right) { + if (arith) { + tcg_gen_sari_i32(s, TCGV_LOW(ret), TCGV_HIGH(arg1), c); + tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), 31); + } else { + tcg_gen_shri_i32(s, TCGV_LOW(ret), TCGV_HIGH(arg1), c); + tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); + } + } else { + tcg_gen_shli_i32(s, TCGV_HIGH(ret), TCGV_LOW(arg1), c); + tcg_gen_movi_i32(s, TCGV_LOW(ret), 0); + } + } else { + TCGv_i32 t0, t1; + + t0 = tcg_temp_new_i32(s); + t1 = tcg_temp_new_i32(s); + if (right) { + tcg_gen_shli_i32(s, t0, TCGV_HIGH(arg1), 32 - c); + if (arith) { + tcg_gen_sari_i32(s, t1, TCGV_HIGH(arg1), c); + } else { + tcg_gen_shri_i32(s, t1, TCGV_HIGH(arg1), c); + } + tcg_gen_shri_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), c); + tcg_gen_or_i32(s, TCGV_LOW(ret), TCGV_LOW(ret), t0); + tcg_gen_mov_i32(s, TCGV_HIGH(ret), t1); + } else { + tcg_gen_shri_i32(s, t0, TCGV_LOW(arg1), 32 - c); + /* Note: ret can be the same as arg1, so we use t1 */ + tcg_gen_shli_i32(s, t1, TCGV_LOW(arg1), c); + tcg_gen_shli_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), c); + tcg_gen_or_i32(s, TCGV_HIGH(ret), TCGV_HIGH(ret), t0); + tcg_gen_mov_i32(s, TCGV_LOW(ret), t1); + } + tcg_temp_free_i32(s, t0); + tcg_temp_free_i32(s, t1); + } +} + +void tcg_gen_shli_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) +{ + tcg_gen_shifti_i64(s, ret, arg1, arg2, 0, 0); +} + +void tcg_gen_shri_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) +{ + tcg_gen_shifti_i64(s, ret, arg1, arg2, 1, 0); +} + +void tcg_gen_sari_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) +{ + tcg_gen_shifti_i64(s, ret, arg1, arg2, 1, 1); +} +#else /* TCG_TARGET_REG_SIZE == 64 */ +void tcg_gen_shli_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) +{ + tcg_debug_assert(arg2 < 64); + if (arg2 == 0) { + tcg_gen_mov_i64(s, ret, arg1); + } else { + TCGv_i64 t0 = tcg_const_i64(s, arg2); + tcg_gen_shl_i64(s, ret, arg1, t0); + tcg_temp_free_i64(s, t0); + } +} + +void tcg_gen_shri_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) +{ + tcg_debug_assert(arg2 < 64); + if (arg2 == 0) { + tcg_gen_mov_i64(s, ret, arg1); + } else { + TCGv_i64 t0 = tcg_const_i64(s, arg2); + tcg_gen_shr_i64(s, ret, arg1, t0); + tcg_temp_free_i64(s, t0); + } +} + +void tcg_gen_sari_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) +{ + tcg_debug_assert(arg2 < 64); + if (arg2 == 0) { + tcg_gen_mov_i64(s, ret, arg1); + } else { + TCGv_i64 t0 = tcg_const_i64(s, arg2); + tcg_gen_sar_i64(s, ret, arg1, t0); + tcg_temp_free_i64(s, t0); + } +} +#endif /* TCG_TARGET_REG_SIZE */ + +void tcg_gen_brcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, int label) +{ + if (cond == TCG_COND_ALWAYS) { + tcg_gen_br(s, label); + } else if (cond != TCG_COND_NEVER) { +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_op6ii_i32(s, INDEX_op_brcond2_i32, TCGV_LOW(arg1), + TCGV_HIGH(arg1), TCGV_LOW(arg2), + TCGV_HIGH(arg2), cond, label); +#else + tcg_gen_op4ii_i64(s, INDEX_op_brcond_i64, arg1, arg2, cond, label); +#endif + } +} + +void tcg_gen_brcondi_i64(TCGContext *s, TCGCond cond, TCGv_i64 arg1, int64_t arg2, int label) +{ + if (cond == TCG_COND_ALWAYS) { + tcg_gen_br(s, label); + } else if (cond != TCG_COND_NEVER) { + TCGv_i64 t0 = tcg_const_i64(s, arg2); + tcg_gen_brcond_i64(s, cond, arg1, t0, label); + tcg_temp_free_i64(s, t0); + } +} + +void tcg_gen_setcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 ret, + TCGv_i64 arg1, TCGv_i64 arg2) +{ + if (cond == TCG_COND_ALWAYS) { + tcg_gen_movi_i64(s, ret, 1); + } else if (cond == TCG_COND_NEVER) { + tcg_gen_movi_i64(s, ret, 0); + } else { +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_op6i_i32(s, INDEX_op_setcond2_i32, TCGV_LOW(ret), + TCGV_LOW(arg1), TCGV_HIGH(arg1), + TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); + tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); +#else + tcg_gen_op4i_i64(s, INDEX_op_setcond_i64, ret, arg1, arg2, cond); +#endif + } +} + +void tcg_gen_setcondi_i64(TCGContext *s, TCGCond cond, TCGv_i64 ret, + TCGv_i64 arg1, int64_t arg2) +{ + TCGv_i64 t0 = tcg_const_i64(s, arg2); + tcg_gen_setcond_i64(s, cond, ret, arg1, t0); + tcg_temp_free_i64(s, t0); +} + +void tcg_gen_muli_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) +{ + TCGv_i64 t0 = tcg_const_i64(s, arg2); + tcg_gen_mul_i64(s, ret, arg1, t0); + tcg_temp_free_i64(s, t0); +} + +void tcg_gen_div_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + if (TCG_TARGET_HAS_div_i64) { + tcg_gen_op3_i64(s, INDEX_op_div_i64, ret, arg1, arg2); + } else if (TCG_TARGET_HAS_div2_i64) { + TCGv_i64 t0 = tcg_temp_new_i64(s); + tcg_gen_sari_i64(s, t0, arg1, 63); + tcg_gen_op5_i64(s, INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); + tcg_temp_free_i64(s, t0); + } else { + gen_helper_div_i64(s, ret, arg1, arg2); + } +} + +void tcg_gen_rem_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + if (TCG_TARGET_HAS_rem_i64) { + tcg_gen_op3_i64(s, INDEX_op_rem_i64, ret, arg1, arg2); + } else if (TCG_TARGET_HAS_div_i64) { + TCGv_i64 t0 = tcg_temp_new_i64(s); + tcg_gen_op3_i64(s, INDEX_op_div_i64, t0, arg1, arg2); + tcg_gen_mul_i64(s, t0, t0, arg2); + tcg_gen_sub_i64(s, ret, arg1, t0); + tcg_temp_free_i64(s, t0); + } else if (TCG_TARGET_HAS_div2_i64) { + TCGv_i64 t0 = tcg_temp_new_i64(s); + tcg_gen_sari_i64(s, t0, arg1, 63); + tcg_gen_op5_i64(s, INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); + tcg_temp_free_i64(s, t0); + } else { + gen_helper_rem_i64(s, ret, arg1, arg2); + } +} + +void tcg_gen_divu_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + if (TCG_TARGET_HAS_div_i64) { + tcg_gen_op3_i64(s, INDEX_op_divu_i64, ret, arg1, arg2); + } else if (TCG_TARGET_HAS_div2_i64) { + TCGv_i64 t0 = tcg_temp_new_i64(s); + tcg_gen_movi_i64(s, t0, 0); + tcg_gen_op5_i64(s, INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); + tcg_temp_free_i64(s, t0); + } else { + gen_helper_divu_i64(s, ret, arg1, arg2); + } +} + +void tcg_gen_remu_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + if (TCG_TARGET_HAS_rem_i64) { + tcg_gen_op3_i64(s, INDEX_op_remu_i64, ret, arg1, arg2); + } else if (TCG_TARGET_HAS_div_i64) { + TCGv_i64 t0 = tcg_temp_new_i64(s); + tcg_gen_op3_i64(s, INDEX_op_divu_i64, t0, arg1, arg2); + tcg_gen_mul_i64(s, t0, t0, arg2); + tcg_gen_sub_i64(s, ret, arg1, t0); + tcg_temp_free_i64(s, t0); + } else if (TCG_TARGET_HAS_div2_i64) { + TCGv_i64 t0 = tcg_temp_new_i64(s); + tcg_gen_movi_i64(s, t0, 0); + tcg_gen_op5_i64(s, INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); + tcg_temp_free_i64(s, t0); + } else { + gen_helper_remu_i64(s, ret, arg1, arg2); + } +} + +void tcg_gen_ext8s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_ext8s_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); + tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_LOW(ret), 31); +#else + if (TCG_TARGET_HAS_ext8s_i64) { + tcg_gen_op2_i64(s, INDEX_op_ext8s_i64, ret, arg); + } else { + tcg_gen_shli_i64(s, ret, arg, 56); + tcg_gen_sari_i64(s, ret, ret, 56); + } +#endif +} + +void tcg_gen_ext16s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_ext16s_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); + tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_LOW(ret), 31); +#else + if (TCG_TARGET_HAS_ext16s_i64) { + tcg_gen_op2_i64(s, INDEX_op_ext16s_i64, ret, arg); + } else { + tcg_gen_shli_i64(s, ret, arg, 48); + tcg_gen_sari_i64(s, ret, ret, 48); + } +#endif +} + +void tcg_gen_ext32s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_mov_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); + tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_LOW(ret), 31); +#else + if (TCG_TARGET_HAS_ext32s_i64) { + tcg_gen_op2_i64(s, INDEX_op_ext32s_i64, ret, arg); + } else { + tcg_gen_shli_i64(s, ret, arg, 32); + tcg_gen_sari_i64(s, ret, ret, 32); + } +#endif +} + +void tcg_gen_ext8u_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_ext8u_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); + tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); +#else + if (TCG_TARGET_HAS_ext8u_i64) { + tcg_gen_op2_i64(s, INDEX_op_ext8u_i64, ret, arg); + } else { + tcg_gen_andi_i64(s, ret, arg, 0xffu); + } +#endif +} + +void tcg_gen_ext16u_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_ext16u_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); + tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); +#else + if (TCG_TARGET_HAS_ext16u_i64) { + tcg_gen_op2_i64(s, INDEX_op_ext16u_i64, ret, arg); + } else { + tcg_gen_andi_i64(s, ret, arg, 0xffffu); + } +#endif +} + +void tcg_gen_ext32u_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_mov_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); + tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); +#else + if (TCG_TARGET_HAS_ext32u_i64) { + tcg_gen_op2_i64(s, INDEX_op_ext32u_i64, ret, arg); + } else { + tcg_gen_andi_i64(s, ret, arg, 0xffffffffu); + } +#endif +} + +/* Note: we assume the six high bytes are set to zero */ +void tcg_gen_bswap16_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_bswap16_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); + tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); +#else + if (TCG_TARGET_HAS_bswap16_i64) { + tcg_gen_op2_i64(s, INDEX_op_bswap16_i64, ret, arg); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(s); + + tcg_gen_ext8u_i64(s, t0, arg); + tcg_gen_shli_i64(s, t0, t0, 8); + tcg_gen_shri_i64(s, ret, arg, 8); + tcg_gen_or_i64(s, ret, ret, t0); + tcg_temp_free_i64(s, t0); + } +#endif +} + +/* Note: we assume the four high bytes are set to zero */ +void tcg_gen_bswap32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_bswap32_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); + tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); +#else + if (TCG_TARGET_HAS_bswap32_i64) { + tcg_gen_op2_i64(s, INDEX_op_bswap32_i64, ret, arg); + } else { + TCGv_i64 t0, t1; + t0 = tcg_temp_new_i64(s); + t1 = tcg_temp_new_i64(s); + + tcg_gen_shli_i64(s, t0, arg, 24); + tcg_gen_ext32u_i64(s, t0, t0); + + tcg_gen_andi_i64(s, t1, arg, 0x0000ff00); + tcg_gen_shli_i64(s, t1, t1, 8); + tcg_gen_or_i64(s, t0, t0, t1); + + tcg_gen_shri_i64(s, t1, arg, 8); + tcg_gen_andi_i64(s, t1, t1, 0x0000ff00); + tcg_gen_or_i64(s, t0, t0, t1); + + tcg_gen_shri_i64(s, t1, arg, 24); + tcg_gen_or_i64(s, ret, t0, t1); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + } +#endif +} + +void tcg_gen_bswap64_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) +{ +#if TCG_TARGET_REG_BITS == 32 + TCGv_i32 t0, t1; + t0 = tcg_temp_new_i32(s); + t1 = tcg_temp_new_i32(s); + + tcg_gen_bswap32_i32(s, t0, TCGV_LOW(arg)); + tcg_gen_bswap32_i32(s, t1, TCGV_HIGH(arg)); + tcg_gen_mov_i32(s, TCGV_LOW(ret), t1); + tcg_gen_mov_i32(s, TCGV_HIGH(ret), t0); + tcg_temp_free_i32(s, t0); + tcg_temp_free_i32(s, t1); +#else + if (TCG_TARGET_HAS_bswap64_i64) { + tcg_gen_op2_i64(s, INDEX_op_bswap64_i64, ret, arg); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(s); + TCGv_i64 t1 = tcg_temp_new_i64(s); + + tcg_gen_shli_i64(s, t0, arg, 56); + + tcg_gen_andi_i64(s, t1, arg, 0x0000ff00); + tcg_gen_shli_i64(s, t1, t1, 40); + tcg_gen_or_i64(s, t0, t0, t1); + + tcg_gen_andi_i64(s, t1, arg, 0x00ff0000); + tcg_gen_shli_i64(s, t1, t1, 24); + tcg_gen_or_i64(s, t0, t0, t1); + + tcg_gen_andi_i64(s, t1, arg, 0xff000000); + tcg_gen_shli_i64(s, t1, t1, 8); + tcg_gen_or_i64(s, t0, t0, t1); + + tcg_gen_shri_i64(s, t1, arg, 8); + tcg_gen_andi_i64(s, t1, t1, 0xff000000); + tcg_gen_or_i64(s, t0, t0, t1); + + tcg_gen_shri_i64(s, t1, arg, 24); + tcg_gen_andi_i64(s, t1, t1, 0x00ff0000); + tcg_gen_or_i64(s, t0, t0, t1); + + tcg_gen_shri_i64(s, t1, arg, 40); + tcg_gen_andi_i64(s, t1, t1, 0x0000ff00); + tcg_gen_or_i64(s, t0, t0, t1); + + tcg_gen_shri_i64(s, t1, arg, 56); + tcg_gen_or_i64(s, ret, t0, t1); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + } +#endif +} + +void tcg_gen_not_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) +{ +#if TCG_TARGET_REG_BITS == 64 + if (TCG_TARGET_HAS_not_i64) { + tcg_gen_op2_i64(s, INDEX_op_not_i64, ret, arg); + } else { + tcg_gen_xori_i64(s, ret, arg, -1); + } +#else + tcg_gen_not_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); + tcg_gen_not_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg)); +#endif +} + +void tcg_gen_andc_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ +#if TCG_TARGET_REG_BITS == 64 + if (TCG_TARGET_HAS_andc_i64) { + tcg_gen_op3_i64(s, INDEX_op_andc_i64, ret, arg1, arg2); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(s); + tcg_gen_not_i64(s, t0, arg2); + tcg_gen_and_i64(s, ret, arg1, t0); + tcg_temp_free_i64(s, t0); + } +#else + tcg_gen_andc_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_andc_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); +#endif +} + +void tcg_gen_eqv_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ +#if TCG_TARGET_REG_BITS == 64 + if (TCG_TARGET_HAS_eqv_i64) { + tcg_gen_op3_i64(s, INDEX_op_eqv_i64, ret, arg1, arg2); + } else { + tcg_gen_xor_i64(s, ret, arg1, arg2); + tcg_gen_not_i64(s, ret, ret); + } +#else + tcg_gen_eqv_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_eqv_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); +#endif +} + +void tcg_gen_nand_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ +#if TCG_TARGET_REG_BITS == 64 + if (TCG_TARGET_HAS_nand_i64) { + tcg_gen_op3_i64(s, INDEX_op_nand_i64, ret, arg1, arg2); + } else { + tcg_gen_and_i64(s, ret, arg1, arg2); + tcg_gen_not_i64(s, ret, ret); + } +#else + tcg_gen_nand_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_nand_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); +#endif +} + +void tcg_gen_nor_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ +#if TCG_TARGET_REG_BITS == 64 + if (TCG_TARGET_HAS_nor_i64) { + tcg_gen_op3_i64(s, INDEX_op_nor_i64, ret, arg1, arg2); + } else { + tcg_gen_or_i64(s, ret, arg1, arg2); + tcg_gen_not_i64(s, ret, ret); + } +#else + tcg_gen_nor_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_nor_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); +#endif +} + +void tcg_gen_orc_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ +#if TCG_TARGET_REG_BITS == 64 + if (TCG_TARGET_HAS_orc_i64) { + tcg_gen_op3_i64(s, INDEX_op_orc_i64, ret, arg1, arg2); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(s); + tcg_gen_not_i64(s, t0, arg2); + tcg_gen_or_i64(s, ret, arg1, t0); + tcg_temp_free_i64(s, t0); + } +#else + tcg_gen_orc_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_orc_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); +#endif +} + +void tcg_gen_rotl_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + if (TCG_TARGET_HAS_rot_i64) { + tcg_gen_op3_i64(s, INDEX_op_rotl_i64, ret, arg1, arg2); + } else { + TCGv_i64 t0, t1; + t0 = tcg_temp_new_i64(s); + t1 = tcg_temp_new_i64(s); + tcg_gen_shl_i64(s, t0, arg1, arg2); + tcg_gen_subfi_i64(s, t1, 64, arg2); + tcg_gen_shr_i64(s, t1, arg1, t1); + tcg_gen_or_i64(s, ret, t0, t1); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + } +} + +void tcg_gen_rotli_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) +{ + tcg_debug_assert(arg2 < 64); + /* some cases can be optimized here */ + if (arg2 == 0) { + tcg_gen_mov_i64(s, ret, arg1); + } else if (TCG_TARGET_HAS_rot_i64) { + TCGv_i64 t0 = tcg_const_i64(s, arg2); + tcg_gen_rotl_i64(s, ret, arg1, t0); + tcg_temp_free_i64(s, t0); + } else { + TCGv_i64 t0, t1; + t0 = tcg_temp_new_i64(s); + t1 = tcg_temp_new_i64(s); + tcg_gen_shli_i64(s, t0, arg1, arg2); + tcg_gen_shri_i64(s, t1, arg1, 64 - arg2); + tcg_gen_or_i64(s, ret, t0, t1); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + } +} + +void tcg_gen_rotr_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + if (TCG_TARGET_HAS_rot_i64) { + tcg_gen_op3_i64(s, INDEX_op_rotr_i64, ret, arg1, arg2); + } else { + TCGv_i64 t0, t1; + t0 = tcg_temp_new_i64(s); + t1 = tcg_temp_new_i64(s); + tcg_gen_shr_i64(s, t0, arg1, arg2); + tcg_gen_subfi_i64(s, t1, 64, arg2); + tcg_gen_shl_i64(s, t1, arg1, t1); + tcg_gen_or_i64(s, ret, t0, t1); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + } +} + +void tcg_gen_rotri_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2) +{ + tcg_debug_assert(arg2 < 64); + /* some cases can be optimized here */ + if (arg2 == 0) { + tcg_gen_mov_i64(s, ret, arg1); + } else { + tcg_gen_rotli_i64(s, ret, arg1, 64 - arg2); + } +} + +void tcg_gen_deposit_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, + unsigned int ofs, unsigned int len) +{ + uint64_t mask; + TCGv_i64 t1; + + tcg_debug_assert(ofs < 64); + tcg_debug_assert(len <= 64); + tcg_debug_assert(ofs + len <= 64); + + if (ofs == 0 && len == 64) { + tcg_gen_mov_i64(s, ret, arg2); + return; + } + if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) { + tcg_gen_op5ii_i64(s, INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len); + return; + } + +#if TCG_TARGET_REG_BITS == 32 + if (ofs >= 32) { + tcg_gen_deposit_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), + TCGV_LOW(arg2), ofs - 32, len); + tcg_gen_mov_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1)); + return; + } + if (ofs + len <= 32) { + tcg_gen_deposit_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), + TCGV_LOW(arg2), ofs, len); + tcg_gen_mov_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1)); + return; + } +#endif + + mask = (1ull << len) - 1; + t1 = tcg_temp_new_i64(s); + + if (ofs + len < 64) { + tcg_gen_andi_i64(s, t1, arg2, mask); + tcg_gen_shli_i64(s, t1, t1, ofs); + } else { + tcg_gen_shli_i64(s, t1, arg2, ofs); + } + tcg_gen_andi_i64(s, ret, arg1, ~(mask << ofs)); + tcg_gen_or_i64(s, ret, ret, t1); + + tcg_temp_free_i64(s, t1); +} + +void tcg_gen_movcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, + TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2) +{ +#if TCG_TARGET_REG_BITS == 32 + TCGv_i32 t0 = tcg_temp_new_i32(s); + TCGv_i32 t1 = tcg_temp_new_i32(s); + tcg_gen_op6i_i32(s, INDEX_op_setcond2_i32, t0, + TCGV_LOW(c1), TCGV_HIGH(c1), + TCGV_LOW(c2), TCGV_HIGH(c2), cond); + + if (TCG_TARGET_HAS_movcond_i32) { + tcg_gen_movi_i32(s, t1, 0); + tcg_gen_movcond_i32(s, TCG_COND_NE, TCGV_LOW(ret), t0, t1, + TCGV_LOW(v1), TCGV_LOW(v2)); + tcg_gen_movcond_i32(s, TCG_COND_NE, TCGV_HIGH(ret), t0, t1, + TCGV_HIGH(v1), TCGV_HIGH(v2)); + } else { + tcg_gen_neg_i32(s, t0, t0); + + tcg_gen_and_i32(s, t1, TCGV_LOW(v1), t0); + tcg_gen_andc_i32(s, TCGV_LOW(ret), TCGV_LOW(v2), t0); + tcg_gen_or_i32(s, TCGV_LOW(ret), TCGV_LOW(ret), t1); + + tcg_gen_and_i32(s, t1, TCGV_HIGH(v1), t0); + tcg_gen_andc_i32(s, TCGV_HIGH(ret), TCGV_HIGH(v2), t0); + tcg_gen_or_i32(s, TCGV_HIGH(ret), TCGV_HIGH(ret), t1); + } + tcg_temp_free_i32(s, t0); + tcg_temp_free_i32(s, t1); +#else + if (TCG_TARGET_HAS_movcond_i64) { + tcg_gen_op6i_i64(s, INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(s); + TCGv_i64 t1 = tcg_temp_new_i64(s); + tcg_gen_setcond_i64(s, cond, t0, c1, c2); + tcg_gen_neg_i64(s, t0, t0); + tcg_gen_and_i64(s, t1, v1, t0); + tcg_gen_andc_i64(s, ret, v2, t0); + tcg_gen_or_i64(s, ret, ret, t1); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + } +#endif +} + +void tcg_gen_add2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, + TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) +{ + if (TCG_TARGET_HAS_add2_i64) { + tcg_gen_op6_i64(s, INDEX_op_add2_i64, rl, rh, al, ah, bl, bh); + /* Allow the optimizer room to replace add2 with two moves. */ + tcg_gen_op0(s, INDEX_op_nop); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(s); + TCGv_i64 t1 = tcg_temp_new_i64(s); + tcg_gen_add_i64(s, t0, al, bl); + tcg_gen_setcond_i64(s, TCG_COND_LTU, t1, t0, al); + tcg_gen_add_i64(s, rh, ah, bh); + tcg_gen_add_i64(s, rh, rh, t1); + tcg_gen_mov_i64(s, rl, t0); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + } +} + +void tcg_gen_sub2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, + TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) +{ + if (TCG_TARGET_HAS_sub2_i64) { + tcg_gen_op6_i64(s, INDEX_op_sub2_i64, rl, rh, al, ah, bl, bh); + /* Allow the optimizer room to replace sub2 with two moves. */ + tcg_gen_op0(s, INDEX_op_nop); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(s); + TCGv_i64 t1 = tcg_temp_new_i64(s); + tcg_gen_sub_i64(s, t0, al, bl); + tcg_gen_setcond_i64(s, TCG_COND_LTU, t1, al, bl); + tcg_gen_sub_i64(s, rh, ah, bh); + tcg_gen_sub_i64(s, rh, rh, t1); + tcg_gen_mov_i64(s, rl, t0); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + } +} + +void tcg_gen_mulu2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) +{ + if (TCG_TARGET_HAS_mulu2_i64) { + tcg_gen_op4_i64(s, INDEX_op_mulu2_i64, rl, rh, arg1, arg2); + /* Allow the optimizer room to replace mulu2 with two moves. */ + tcg_gen_op0(s, INDEX_op_nop); + } else if (TCG_TARGET_HAS_muluh_i64) { + TCGv_i64 t = tcg_temp_new_i64(s); + tcg_gen_op3_i64(s, INDEX_op_mul_i64, t, arg1, arg2); + tcg_gen_op3_i64(s, INDEX_op_muluh_i64, rh, arg1, arg2); + tcg_gen_mov_i64(s, rl, t); + tcg_temp_free_i64(s, t); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(s); + tcg_gen_mul_i64(s, t0, arg1, arg2); + gen_helper_muluh_i64(s, rh, arg1, arg2); + tcg_gen_mov_i64(s, rl, t0); + tcg_temp_free_i64(s, t0); + } +} + +void tcg_gen_muls2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) +{ + if (TCG_TARGET_HAS_muls2_i64) { + tcg_gen_op4_i64(s, INDEX_op_muls2_i64, rl, rh, arg1, arg2); + /* Allow the optimizer room to replace muls2 with two moves. */ + tcg_gen_op0(s, INDEX_op_nop); + } else if (TCG_TARGET_HAS_mulsh_i64) { + TCGv_i64 t = tcg_temp_new_i64(s); + tcg_gen_op3_i64(s, INDEX_op_mul_i64, t, arg1, arg2); + tcg_gen_op3_i64(s, INDEX_op_mulsh_i64, rh, arg1, arg2); + tcg_gen_mov_i64(s, rl, t); + tcg_temp_free_i64(s, t); + } else if (TCG_TARGET_HAS_mulu2_i64 || TCG_TARGET_HAS_muluh_i64) { + TCGv_i64 t0 = tcg_temp_new_i64(s); + TCGv_i64 t1 = tcg_temp_new_i64(s); + TCGv_i64 t2 = tcg_temp_new_i64(s); + TCGv_i64 t3 = tcg_temp_new_i64(s); + tcg_gen_mulu2_i64(s, t0, t1, arg1, arg2); + /* Adjust for negative inputs. */ + tcg_gen_sari_i64(s, t2, arg1, 63); + tcg_gen_sari_i64(s, t3, arg2, 63); + tcg_gen_and_i64(s, t2, t2, arg2); + tcg_gen_and_i64(s, t3, t3, arg1); + tcg_gen_sub_i64(s, rh, t1, t2); + tcg_gen_sub_i64(s, rh, rh, t3); + tcg_gen_mov_i64(s, rl, t0); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + tcg_temp_free_i64(s, t2); + tcg_temp_free_i64(s, t3); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(s); + tcg_gen_mul_i64(s, t0, arg1, arg2); + gen_helper_mulsh_i64(s, rh, arg1, arg2); + tcg_gen_mov_i64(s, rl, t0); + tcg_temp_free_i64(s, t0); + } +} + +/* Size changing operations. */ + +void tcg_gen_trunc_shr_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg, unsigned count) +{ + tcg_debug_assert(count < 64); +#if TCG_TARGET_REG_BITS == 32 + if (count >= 32) { + tcg_gen_shri_i32(s, ret, TCGV_HIGH(arg), count - 32); + } else if (count == 0) { + tcg_gen_mov_i32(s, ret, TCGV_LOW(arg)); + } else { + TCGv_i64 t = tcg_temp_new_i64(s); + tcg_gen_shri_i64(s, t, arg, count); + tcg_gen_mov_i32(s, ret, TCGV_LOW(t)); + tcg_temp_free_i64(s, t); + } +#else + if (TCG_TARGET_HAS_trunc_shr_i32) { + tcg_gen_op3i_i32(s, INDEX_op_trunc_shr_i32, ret, + MAKE_TCGV_I32(GET_TCGV_I64(arg)), count); + } else if (count == 0) { + tcg_gen_mov_i32(s, ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); + } else { + TCGv_i64 t = tcg_temp_new_i64(s); + tcg_gen_shri_i64(s, t, arg, count); + tcg_gen_mov_i32(s, ret, MAKE_TCGV_I32(GET_TCGV_I64(t))); + tcg_temp_free_i64(s, t); + } +#endif +} + +void tcg_gen_extu_i32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i32 arg) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_mov_i32(s, TCGV_LOW(ret), arg); + tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); +#else + /* Note: we assume the target supports move between + 32 and 64 bit registers. */ + tcg_gen_ext32u_i64(s, ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); +#endif +} + +void tcg_gen_ext_i32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i32 arg) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_mov_i32(s, TCGV_LOW(ret), arg); + tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_LOW(ret), 31); +#else + /* Note: we assume the target supports move between + 32 and 64 bit registers. */ + tcg_gen_ext32s_i64(s, ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); +#endif +} + +void tcg_gen_concat_i32_i64(TCGContext *s, TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_mov_i32(s, TCGV_LOW(dest), low); + tcg_gen_mov_i32(s, TCGV_HIGH(dest), high); +#else + TCGv_i64 tmp = tcg_temp_new_i64(s); + /* These extensions are only needed for type correctness. + We may be able to do better given target specific information. */ + tcg_gen_extu_i32_i64(s, tmp, high); + tcg_gen_extu_i32_i64(s, dest, low); + /* If deposit is available, use it. Otherwise use the extra + knowledge that we have of the zero-extensions above. */ + if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(32, 32)) { + tcg_gen_deposit_i64(s, dest, dest, tmp, 32, 32); + } else { + tcg_gen_shli_i64(s, tmp, tmp, 32); + tcg_gen_or_i64(s, dest, dest, tmp); + } + tcg_temp_free_i64(s, tmp); +#endif +} + +void tcg_gen_extr_i64_i32(TCGContext *s, TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_mov_i32(s, lo, TCGV_LOW(arg)); + tcg_gen_mov_i32(s, hi, TCGV_HIGH(arg)); +#else + tcg_gen_trunc_shr_i64_i32(s, lo, arg, 0); + tcg_gen_trunc_shr_i64_i32(s, hi, arg, 32); +#endif +} + +void tcg_gen_extr32_i64(TCGContext *s, TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg) +{ + tcg_gen_ext32u_i64(s, lo, arg); + tcg_gen_shri_i64(s, hi, arg, 32); +} + +/* QEMU specific operations. */ + +void tcg_gen_goto_tb(TCGContext *s, unsigned idx) +{ + /* We only support two chained exits. */ + tcg_debug_assert(idx <= 1); +#ifdef CONFIG_DEBUG_TCG + /* Verify that we havn't seen this numbered exit before. */ + tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) == 0); + tcg_ctx.goto_tb_issue_mask |= 1 << idx; +#endif + tcg_gen_op1i(s, INDEX_op_goto_tb, idx); +} + +static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st) +{ + switch (op & MO_SIZE) { + case MO_8: + op &= ~MO_BSWAP; + break; + case MO_16: + break; + case MO_32: + if (!is64) { + op &= ~MO_SIGN; + } + break; + case MO_64: + if (!is64) { + tcg_abort(); + } + break; + } + if (st) { + op &= ~MO_SIGN; + } + return op; +} + +static inline void tcg_add_param_i32(TCGContext *tcg_ctx, TCGv_i32 val) +{ + *tcg_ctx->gen_opparam_ptr++ = GET_TCGV_I32(val); +} + +static inline void tcg_add_param_i64(TCGContext *tcg_ctx, TCGv_i64 val) +{ +#if TCG_TARGET_REG_BITS == 32 + *tcg_ctx->gen_opparam_ptr++ = GET_TCGV_I32(TCGV_LOW(val)); + *tcg_ctx->gen_opparam_ptr++ = GET_TCGV_I32(TCGV_HIGH(val)); +#else + *tcg_ctx->gen_opparam_ptr++ = GET_TCGV_I64(val); +#endif +} + +#if TARGET_LONG_BITS == 32 +# define tcg_add_param_tl tcg_add_param_i32 +#else +# define tcg_add_param_tl tcg_add_param_i64 +#endif + +// Unicorn engine +// check if the last memory access was invalid +// if so, we jump to the block epilogue to quit immediately. +void check_exit_request(TCGContext *tcg_ctx) +{ + TCGv_i32 flag; + + flag = tcg_temp_new_i32(tcg_ctx); + tcg_gen_ld_i32(tcg_ctx, flag, tcg_ctx->cpu_env, + offsetof(CPUState, tcg_exit_req) - ENV_OFFSET); + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, flag, 0, tcg_ctx->exitreq_label); + tcg_temp_free_i32(tcg_ctx, flag); +} + +void tcg_gen_qemu_ld_i32(struct uc_struct *uc, TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) +{ + TCGContext *tcg_ctx = uc->tcg_ctx; + + memop = tcg_canonicalize_memop(memop, 0, 0); + + *tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_ld_i32; + tcg_add_param_i32(tcg_ctx, val); + tcg_add_param_tl(tcg_ctx, addr); + *tcg_ctx->gen_opparam_ptr++ = memop; + *tcg_ctx->gen_opparam_ptr++ = idx; + + check_exit_request(tcg_ctx); +} + +void tcg_gen_qemu_st_i32(struct uc_struct *uc, TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) +{ + TCGContext *tcg_ctx = uc->tcg_ctx; + + memop = tcg_canonicalize_memop(memop, 0, 1); + + *tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_st_i32; + tcg_add_param_i32(tcg_ctx, val); + tcg_add_param_tl(tcg_ctx, addr); + *tcg_ctx->gen_opparam_ptr++ = memop; + *tcg_ctx->gen_opparam_ptr++ = idx; + + check_exit_request(tcg_ctx); +} + +void tcg_gen_qemu_ld_i64(struct uc_struct *uc, TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) +{ + TCGContext *tcg_ctx = uc->tcg_ctx; + + memop = tcg_canonicalize_memop(memop, 1, 0); + +#if TCG_TARGET_REG_BITS == 32 + if ((memop & MO_SIZE) < MO_64) { + tcg_gen_qemu_ld_i32(uc, TCGV_LOW(val), addr, idx, memop); + if (memop & MO_SIGN) { + tcg_gen_sari_i32(tcg_ctx, TCGV_HIGH(val), TCGV_LOW(val), 31); + } else { + tcg_gen_movi_i32(tcg_ctx, TCGV_HIGH(val), 0); + } + + check_exit_request(tcg_ctx); + return; + } +#endif + + *tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_ld_i64; + tcg_add_param_i64(tcg_ctx, val); + tcg_add_param_tl(tcg_ctx, addr); + *tcg_ctx->gen_opparam_ptr++ = memop; + *tcg_ctx->gen_opparam_ptr++ = idx; + + check_exit_request(tcg_ctx); +} + +void tcg_gen_qemu_st_i64(struct uc_struct *uc, TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) +{ + TCGContext *tcg_ctx = uc->tcg_ctx; + + memop = tcg_canonicalize_memop(memop, 1, 1); + +#if TCG_TARGET_REG_BITS == 32 + if ((memop & MO_SIZE) < MO_64) { + tcg_gen_qemu_st_i32(uc, TCGV_LOW(val), addr, idx, memop); + check_exit_request(tcg_ctx); + return; + } +#endif + + *tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_st_i64; + tcg_add_param_i64(tcg_ctx, val); + tcg_add_param_tl(tcg_ctx, addr); + *tcg_ctx->gen_opparam_ptr++ = memop; + *tcg_ctx->gen_opparam_ptr++ = idx; + + check_exit_request(tcg_ctx); +} \ No newline at end of file diff --git a/qemu/tcg/tcg-op.h b/qemu/tcg/tcg-op.h index 5d2edee5..ae39884d 100644 --- a/qemu/tcg/tcg-op.h +++ b/qemu/tcg/tcg-op.h @@ -21,11 +21,21 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ + #include "tcg.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" -int gen_new_label(TCGContext *); +/* Basic output routines. Not for general consumption. */ +void tcg_gen_op0(TCGContext *, TCGOpcode); +void tcg_gen_op1(TCGContext *, TCGOpcode, TCGArg); +void tcg_gen_op2(TCGContext *, TCGOpcode, TCGArg, TCGArg); +void tcg_gen_op3(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg); +void tcg_gen_op4(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg); +void tcg_gen_op5(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, + TCGArg, TCGArg); +void tcg_gen_op6(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, + TCGArg, TCGArg, TCGArg); static inline void gen_uc_tracecode(TCGContext *tcg_ctx, int32_t size, int32_t type, void *uc, uint64_t pc) { @@ -36,353 +46,292 @@ static inline void gen_uc_tracecode(TCGContext *tcg_ctx, int32_t size, int32_t t gen_helper_uc_tracecode(tcg_ctx, tsize, ttype, tuc, tpc); } -static inline void tcg_gen_op0(TCGContext *s, TCGOpcode opc) +static inline void tcg_gen_op1_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 a1) { - *s->gen_opc_ptr++ = opc; + tcg_gen_op1(s, opc, GET_TCGV_I32(a1)); } -static inline void tcg_gen_op1_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 arg1) +static inline void tcg_gen_op1_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 a1) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg1); + tcg_gen_op1(s, opc, GET_TCGV_I64(a1)); } -static inline void tcg_gen_op1_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 arg1) +static inline void tcg_gen_op1i(TCGContext *s, TCGOpcode opc, TCGArg a1) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg1); + tcg_gen_op1(s, opc, a1); } -static inline void tcg_gen_op1i(TCGContext *s, TCGOpcode opc, TCGArg arg1) +static inline void tcg_gen_op2_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = arg1; + tcg_gen_op2(s, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2)); } -static inline void tcg_gen_op2_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2) +static inline void tcg_gen_op2_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg2); + tcg_gen_op2(s, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2)); } -static inline void tcg_gen_op2_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2) +static inline void tcg_gen_op2i_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 a1, TCGArg a2) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg2); + tcg_gen_op2(s, opc, GET_TCGV_I32(a1), a2); } -static inline void tcg_gen_op2i_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2) +static inline void tcg_gen_op2i_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 a1, TCGArg a2) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg1); - *s->gen_opparam_ptr++ = arg2; + tcg_gen_op2(s, opc, GET_TCGV_I64(a1), a2); } -static inline void tcg_gen_op2i_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2) +static inline void tcg_gen_op2ii(TCGContext *s, TCGOpcode opc, TCGArg a1, TCGArg a2) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg1); - *s->gen_opparam_ptr++ = arg2; + tcg_gen_op2(s, opc, a1, a2); } -static inline void tcg_gen_op2ii(TCGContext *s, TCGOpcode opc, TCGArg arg1, TCGArg arg2) +static inline void tcg_gen_op3_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = arg1; - *s->gen_opparam_ptr++ = arg2; + tcg_gen_op3(s, opc, GET_TCGV_I32(a1), + GET_TCGV_I32(a2), GET_TCGV_I32(a3)); } -static inline void tcg_gen_op3_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, - TCGv_i32 arg3) +static inline void tcg_gen_op3_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg3); + tcg_gen_op3(s, opc, GET_TCGV_I64(a1), + GET_TCGV_I64(a2), GET_TCGV_I64(a3)); } -static inline void tcg_gen_op3_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, - TCGv_i64 arg3) +static inline void tcg_gen_op3i_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 a1, + TCGv_i32 a2, TCGArg a3) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg3); + tcg_gen_op3(s, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3); } -static inline void tcg_gen_op3i_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 arg1, - TCGv_i32 arg2, TCGArg arg3) +static inline void tcg_gen_op3i_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 a1, + TCGv_i64 a2, TCGArg a3) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg2); - *s->gen_opparam_ptr++ = arg3; -} - -static inline void tcg_gen_op3i_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 arg1, - TCGv_i64 arg2, TCGArg arg3) -{ - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg2); - *s->gen_opparam_ptr++ = arg3; + tcg_gen_op3(s, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3); } static inline void tcg_gen_ldst_op_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 val, TCGv_ptr base, TCGArg offset) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(val); - *s->gen_opparam_ptr++ = GET_TCGV_PTR(base); - *s->gen_opparam_ptr++ = offset; + tcg_gen_op3(s, opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offset); } static inline void tcg_gen_ldst_op_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 val, TCGv_ptr base, TCGArg offset) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(val); - *s->gen_opparam_ptr++ = GET_TCGV_PTR(base); - *s->gen_opparam_ptr++ = offset; + tcg_gen_op3(s, opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offset); } -static inline void tcg_gen_op4_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, - TCGv_i32 arg3, TCGv_i32 arg4) +static inline void tcg_gen_op4_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGv_i32 a4) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg3); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg4); + tcg_gen_op4(s, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + GET_TCGV_I32(a3), GET_TCGV_I32(a4)); } -static inline void tcg_gen_op4_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, - TCGv_i64 arg3, TCGv_i64 arg4) +static inline void tcg_gen_op4_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGv_i64 a4) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg3); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg4); + tcg_gen_op4(s, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + GET_TCGV_I64(a3), GET_TCGV_I64(a4)); } -static inline void tcg_gen_op4i_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, - TCGv_i32 arg3, TCGArg arg4) +static inline void tcg_gen_op4i_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGArg a4) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg3); - *s->gen_opparam_ptr++ = arg4; + tcg_gen_op4(s, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + GET_TCGV_I32(a3), a4); } -static inline void tcg_gen_op4i_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, - TCGv_i64 arg3, TCGArg arg4) +static inline void tcg_gen_op4i_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGArg a4) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg3); - *s->gen_opparam_ptr++ = arg4; + tcg_gen_op4(s, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + GET_TCGV_I64(a3), a4); } -static inline void tcg_gen_op4ii_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, - TCGArg arg3, TCGArg arg4) +static inline void tcg_gen_op4ii_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGArg a3, TCGArg a4) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg2); - *s->gen_opparam_ptr++ = arg3; - *s->gen_opparam_ptr++ = arg4; + tcg_gen_op4(s, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4); } -static inline void tcg_gen_op4ii_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, - TCGArg arg3, TCGArg arg4) +static inline void tcg_gen_op4ii_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGArg a3, TCGArg a4) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg2); - *s->gen_opparam_ptr++ = arg3; - *s->gen_opparam_ptr++ = arg4; + tcg_gen_op4(s, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4); } -static inline void tcg_gen_op5_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, - TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5) +static inline void tcg_gen_op5_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg3); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg4); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg5); + tcg_gen_op5(s, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5)); } -static inline void tcg_gen_op5_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, - TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5) +static inline void tcg_gen_op5_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg3); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg4); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg5); + tcg_gen_op5(s, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5)); } -static inline void tcg_gen_op5i_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, - TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5) +static inline void tcg_gen_op5i_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg3); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg4); - *s->gen_opparam_ptr++ = arg5; + tcg_gen_op5(s, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5); } -static inline void tcg_gen_op5i_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, - TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5) +static inline void tcg_gen_op5i_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg3); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg4); - *s->gen_opparam_ptr++ = arg5; + tcg_gen_op5(s, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5); } -static inline void tcg_gen_op5ii_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 arg1, - TCGv_i32 arg2, TCGv_i32 arg3, - TCGArg arg4, TCGArg arg5) +static inline void tcg_gen_op5ii_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 a1, + TCGv_i32 a2, TCGv_i32 a3, + TCGArg a4, TCGArg a5) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg3); - *s->gen_opparam_ptr++ = arg4; - *s->gen_opparam_ptr++ = arg5; + tcg_gen_op5(s, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + GET_TCGV_I32(a3), a4, a5); } -static inline void tcg_gen_op5ii_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 arg1, - TCGv_i64 arg2, TCGv_i64 arg3, - TCGArg arg4, TCGArg arg5) +static inline void tcg_gen_op5ii_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 a1, + TCGv_i64 a2, TCGv_i64 a3, + TCGArg a4, TCGArg a5) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg3); - *s->gen_opparam_ptr++ = arg4; - *s->gen_opparam_ptr++ = arg5; + tcg_gen_op5(s, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + GET_TCGV_I64(a3), a4, a5); } -static inline void tcg_gen_op6_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, - TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, - TCGv_i32 arg6) +static inline void tcg_gen_op6_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5, + TCGv_i32 a6) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg3); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg4); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg5); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg6); + tcg_gen_op6(s, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), + GET_TCGV_I32(a6)); } -static inline void tcg_gen_op6_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, - TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5, - TCGv_i64 arg6) +static inline void tcg_gen_op6_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5, + TCGv_i64 a6) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg3); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg4); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg5); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg6); + tcg_gen_op6(s, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), + GET_TCGV_I64(a6)); } -static inline void tcg_gen_op6i_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, - TCGv_i32 arg3, TCGv_i32 arg4, - TCGv_i32 arg5, TCGArg arg6) +static inline void tcg_gen_op6i_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGv_i32 a4, + TCGv_i32 a5, TCGArg a6) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg3); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg4); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg5); - *s->gen_opparam_ptr++ = arg6; + tcg_gen_op6(s, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), a6); } -static inline void tcg_gen_op6i_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, - TCGv_i64 arg3, TCGv_i64 arg4, - TCGv_i64 arg5, TCGArg arg6) +static inline void tcg_gen_op6i_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGv_i64 a4, + TCGv_i64 a5, TCGArg a6) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg3); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg4); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg5); - *s->gen_opparam_ptr++ = arg6; + tcg_gen_op6(s, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), a6); } -static inline void tcg_gen_op6ii_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 arg1, - TCGv_i32 arg2, TCGv_i32 arg3, - TCGv_i32 arg4, TCGArg arg5, TCGArg arg6) +static inline void tcg_gen_op6ii_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 a1, + TCGv_i32 a2, TCGv_i32 a3, + TCGv_i32 a4, TCGArg a5, TCGArg a6) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg3); - *s->gen_opparam_ptr++ = GET_TCGV_I32(arg4); - *s->gen_opparam_ptr++ = arg5; - *s->gen_opparam_ptr++ = arg6; + tcg_gen_op6(s, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5, a6); } -static inline void tcg_gen_op6ii_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 arg1, - TCGv_i64 arg2, TCGv_i64 arg3, - TCGv_i64 arg4, TCGArg arg5, TCGArg arg6) +static inline void tcg_gen_op6ii_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 a1, + TCGv_i64 a2, TCGv_i64 a3, + TCGv_i64 a4, TCGArg a5, TCGArg a6) { - *s->gen_opc_ptr++ = opc; - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg1); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg2); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg3); - *s->gen_opparam_ptr++ = GET_TCGV_I64(arg4); - *s->gen_opparam_ptr++ = arg5; - *s->gen_opparam_ptr++ = arg6; + tcg_gen_op6(s, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5, a6); } -static inline void tcg_add_param_i32(TCGContext *s, TCGv_i32 val) -{ - *s->gen_opparam_ptr++ = GET_TCGV_I32(val); -} +/* Generic ops. */ -static inline void tcg_add_param_i64(TCGContext *s, TCGv_i64 val) -{ -#if TCG_TARGET_REG_BITS == 32 - *s->gen_opparam_ptr++ = GET_TCGV_I32(TCGV_LOW(val)); - *s->gen_opparam_ptr++ = GET_TCGV_I32(TCGV_HIGH(val)); -#else - *s->gen_opparam_ptr++ = GET_TCGV_I64(val); -#endif -} +int gen_new_label(TCGContext *s); static inline void gen_set_label(TCGContext *s, int n) { - tcg_gen_op1i(s, INDEX_op_set_label, n); + tcg_gen_op1(s, INDEX_op_set_label, n); } static inline void tcg_gen_br(TCGContext *s, int label) { - tcg_gen_op1i(s, INDEX_op_br, label); + tcg_gen_op1(s, INDEX_op_br, label); +} + +/* Helper calls. */ + +/* 32 bit ops */ + +void tcg_gen_addi_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_subfi_i32(TCGContext *s, TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); +void tcg_gen_subi_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_andi_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); +void tcg_gen_ori_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_xori_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_shli_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); +void tcg_gen_shri_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); +void tcg_gen_sari_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); +void tcg_gen_muli_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_div_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_rem_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_divu_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_remu_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_andc_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_eqv_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_nand_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_nor_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_orc_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_rotl_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_rotli_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); +void tcg_gen_rotr_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_rotri_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); +void tcg_gen_deposit_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, + unsigned int ofs, unsigned int len); +void tcg_gen_brcond_i32(TCGContext *s, TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, int label); +void tcg_gen_brcondi_i32(TCGContext *s, TCGCond cond, TCGv_i32 arg1, int32_t arg2, int label); +void tcg_gen_setcond_i32(TCGContext *s, TCGCond cond, TCGv_i32 ret, + TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_setcondi_i32(TCGContext *s, TCGCond cond, TCGv_i32 ret, + TCGv_i32 arg1, int32_t arg2); +void tcg_gen_movcond_i32(TCGContext *s, TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, + TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); +void tcg_gen_add2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, + TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); +void tcg_gen_sub2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, + TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); +void tcg_gen_mulu2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_muls2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_ext8s_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_ext16s_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_ext8u_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_ext16u_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_bswap16_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_bswap32_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); + +static inline void tcg_gen_discard_i32(TCGContext *s, TCGv_i32 arg) +{ + tcg_gen_op1_i32(s, INDEX_op_discard, arg); } static inline void tcg_gen_mov_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) { - if (!TCGV_EQUAL_I32(ret, arg)) + if (!TCGV_EQUAL_I32(ret, arg)) { tcg_gen_op2_i32(s, INDEX_op_mov_i32, ret, arg); + } } static inline void tcg_gen_movi_i32(TCGContext *s, TCGv_i32 ret, int32_t arg) @@ -390,8 +339,6 @@ static inline void tcg_gen_movi_i32(TCGContext *s, TCGv_i32 ret, int32_t arg) tcg_gen_op2i_i32(s, INDEX_op_movi_i32, ret, arg); } -/* 32 bit ops */ - static inline void tcg_gen_ld8u_i32(TCGContext *s, TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(s, INDEX_op_ld8u_i32, ret, arg2, offset); @@ -437,126 +384,24 @@ static inline void tcg_gen_add_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, T tcg_gen_op3_i32(s, INDEX_op_add_i32, ret, arg1, arg2); } -static inline void tcg_gen_addi_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - /* some cases can be optimized here */ - if (arg2 == 0) { - tcg_gen_mov_i32(s, ret, arg1); - } else { - TCGv_i32 t0 = tcg_const_i32(s, arg2); - tcg_gen_add_i32(s, ret, arg1, t0); - tcg_temp_free_i32(s, t0); - } -} - static inline void tcg_gen_sub_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(s, INDEX_op_sub_i32, ret, arg1, arg2); } -static inline void tcg_gen_subfi_i32(TCGContext *s, TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) -{ - TCGv_i32 t0 = tcg_const_i32(s, arg1); - tcg_gen_sub_i32(s, ret, t0, arg2); - tcg_temp_free_i32(s, t0); -} - -static inline void tcg_gen_subi_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - /* some cases can be optimized here */ - if (arg2 == 0) { - tcg_gen_mov_i32(s, ret, arg1); - } else { - TCGv_i32 t0 = tcg_const_i32(s, arg2); - tcg_gen_sub_i32(s, ret, arg1, t0); - tcg_temp_free_i32(s, t0); - } -} - static inline void tcg_gen_and_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { - if (TCGV_EQUAL_I32(arg1, arg2)) { - tcg_gen_mov_i32(s, ret, arg1); - } else { - tcg_gen_op3_i32(s, INDEX_op_and_i32, ret, arg1, arg2); - } -} - -static inline void tcg_gen_andi_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) -{ - TCGv_i32 t0; - /* Some cases can be optimized here. */ - switch (arg2) { - case 0: - tcg_gen_movi_i32(s, ret, 0); - return; - case 0xffffffffu: - tcg_gen_mov_i32(s, ret, arg1); - return; - case 0xffu: - /* Don't recurse with tcg_gen_ext8u_i32. */ - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_op2_i32(s, INDEX_op_ext8u_i32, ret, arg1); - return; - } - break; - case 0xffffu: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_op2_i32(s, INDEX_op_ext16u_i32, ret, arg1); - return; - } - break; - } - t0 = tcg_const_i32(s, arg2); - tcg_gen_and_i32(s, ret, arg1, t0); - tcg_temp_free_i32(s, t0); + tcg_gen_op3_i32(s, INDEX_op_and_i32, ret, arg1, arg2); } static inline void tcg_gen_or_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { - if (TCGV_EQUAL_I32(arg1, arg2)) { - tcg_gen_mov_i32(s, ret, arg1); - } else { - tcg_gen_op3_i32(s, INDEX_op_or_i32, ret, arg1, arg2); - } -} - -static inline void tcg_gen_ori_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - /* Some cases can be optimized here. */ - if (arg2 == -1) { - tcg_gen_movi_i32(s, ret, -1); - } else if (arg2 == 0) { - tcg_gen_mov_i32(s, ret, arg1); - } else { - TCGv_i32 t0 = tcg_const_i32(s, arg2); - tcg_gen_or_i32(s, ret, arg1, t0); - tcg_temp_free_i32(s, t0); - } + tcg_gen_op3_i32(s, INDEX_op_or_i32, ret, arg1, arg2); } static inline void tcg_gen_xor_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { - if (TCGV_EQUAL_I32(arg1, arg2)) { - tcg_gen_movi_i32(s, ret, 0); - } else { - tcg_gen_op3_i32(s, INDEX_op_xor_i32, ret, arg1, arg2); - } -} - -static inline void tcg_gen_xori_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - /* Some cases can be optimized here. */ - if (arg2 == 0) { - tcg_gen_mov_i32(s, ret, arg1); - } else if (arg2 == -1 && TCG_TARGET_HAS_not_i32) { - /* Don't recurse with tcg_gen_not_i32. */ - tcg_gen_op2_i32(s, INDEX_op_not_i32, ret, arg1); - } else { - TCGv_i32 t0 = tcg_const_i32(s, arg2); - tcg_gen_xor_i32(s, ret, arg1, t0); - tcg_temp_free_i32(s, t0); - } + tcg_gen_op3_i32(s, INDEX_op_xor_i32, ret, arg1, arg2); } static inline void tcg_gen_shl_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) @@ -564,449 +409,102 @@ static inline void tcg_gen_shl_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, T tcg_gen_op3_i32(s, INDEX_op_shl_i32, ret, arg1, arg2); } -static inline void tcg_gen_shli_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - if (arg2 == 0) { - tcg_gen_mov_i32(s, ret, arg1); - } else { - TCGv_i32 t0 = tcg_const_i32(s, arg2); - tcg_gen_shl_i32(s, ret, arg1, t0); - tcg_temp_free_i32(s, t0); - } -} - static inline void tcg_gen_shr_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(s, INDEX_op_shr_i32, ret, arg1, arg2); } -static inline void tcg_gen_shri_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - if (arg2 == 0) { - tcg_gen_mov_i32(s, ret, arg1); - } else { - TCGv_i32 t0 = tcg_const_i32(s, arg2); - tcg_gen_shr_i32(s, ret, arg1, t0); - tcg_temp_free_i32(s, t0); - } -} - static inline void tcg_gen_sar_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(s, INDEX_op_sar_i32, ret, arg1, arg2); } -static inline void tcg_gen_sari_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - if (arg2 == 0) { - tcg_gen_mov_i32(s, ret, arg1); - } else { - TCGv_i32 t0 = tcg_const_i32(s, arg2); - tcg_gen_sar_i32(s, ret, arg1, t0); - tcg_temp_free_i32(s, t0); - } -} - -static inline void tcg_gen_brcond_i32(TCGContext *s, TCGCond cond, TCGv_i32 arg1, - TCGv_i32 arg2, int label_index) -{ - if (cond == TCG_COND_ALWAYS) { - tcg_gen_br(s, label_index); - } else if (cond != TCG_COND_NEVER) { - tcg_gen_op4ii_i32(s, INDEX_op_brcond_i32, arg1, arg2, cond, label_index); - } -} - -static inline void tcg_gen_brcondi_i32(TCGContext *s, TCGCond cond, TCGv_i32 arg1, - int32_t arg2, int label_index) -{ - if (cond == TCG_COND_ALWAYS) { - tcg_gen_br(s, label_index); - } else if (cond != TCG_COND_NEVER) { - TCGv_i32 t0 = tcg_const_i32(s, arg2); - tcg_gen_brcond_i32(s, cond, arg1, t0, label_index); - tcg_temp_free_i32(s, t0); - } -} - -static inline void tcg_gen_setcond_i32(TCGContext *s, TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (cond == TCG_COND_ALWAYS) { - tcg_gen_movi_i32(s, ret, 1); - } else if (cond == TCG_COND_NEVER) { - tcg_gen_movi_i32(s, ret, 0); - } else { - tcg_gen_op4i_i32(s, INDEX_op_setcond_i32, ret, arg1, arg2, cond); - } -} - -static inline void tcg_gen_setcondi_i32(TCGContext *s, TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, int32_t arg2) -{ - if (cond == TCG_COND_ALWAYS) { - tcg_gen_movi_i32(s, ret, 1); - } else if (cond == TCG_COND_NEVER) { - tcg_gen_movi_i32(s, ret, 0); - } else { - TCGv_i32 t0 = tcg_const_i32(s, arg2); - tcg_gen_setcond_i32(s, cond, ret, arg1, t0); - tcg_temp_free_i32(s, t0); - } -} - static inline void tcg_gen_mul_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(s, INDEX_op_mul_i32, ret, arg1, arg2); } -static inline void tcg_gen_muli_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) +static inline void tcg_gen_neg_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) { - TCGv_i32 t0 = tcg_const_i32(s, arg2); - tcg_gen_mul_i32(s, ret, arg1, t0); - tcg_temp_free_i32(s, t0); -} - -static inline void tcg_gen_div_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (TCG_TARGET_HAS_div_i32) { - tcg_gen_op3_i32(s, INDEX_op_div_i32, ret, arg1, arg2); - } else if (TCG_TARGET_HAS_div2_i32) { - TCGv_i32 t0 = tcg_temp_new_i32(s); - tcg_gen_sari_i32(s, t0, arg1, 31); - tcg_gen_op5_i32(s, INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); - tcg_temp_free_i32(s, t0); + if (TCG_TARGET_HAS_neg_i32) { + tcg_gen_op2_i32(s, INDEX_op_neg_i32, ret, arg); } else { - gen_helper_div_i32(s, ret, arg1, arg2); + tcg_gen_subfi_i32(s, ret, 0, arg); } } -static inline void tcg_gen_rem_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +static inline void tcg_gen_not_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) { - if (TCG_TARGET_HAS_rem_i32) { - tcg_gen_op3_i32(s, INDEX_op_rem_i32, ret, arg1, arg2); - } else if (TCG_TARGET_HAS_div_i32) { - TCGv_i32 t0 = tcg_temp_new_i32(s); - tcg_gen_op3_i32(s, INDEX_op_div_i32, t0, arg1, arg2); - tcg_gen_mul_i32(s, t0, t0, arg2); - tcg_gen_sub_i32(s, ret, arg1, t0); - tcg_temp_free_i32(s, t0); - } else if (TCG_TARGET_HAS_div2_i32) { - TCGv_i32 t0 = tcg_temp_new_i32(s); - tcg_gen_sari_i32(s, t0, arg1, 31); - tcg_gen_op5_i32(s, INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); - tcg_temp_free_i32(s, t0); + if (TCG_TARGET_HAS_not_i32) { + tcg_gen_op2_i32(s, INDEX_op_not_i32, ret, arg); } else { - gen_helper_rem_i32(s, ret, arg1, arg2); + tcg_gen_xori_i32(s, ret, arg, -1); } } -static inline void tcg_gen_divu_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (TCG_TARGET_HAS_div_i32) { - tcg_gen_op3_i32(s, INDEX_op_divu_i32, ret, arg1, arg2); - } else if (TCG_TARGET_HAS_div2_i32) { - TCGv_i32 t0 = tcg_temp_new_i32(s); - tcg_gen_movi_i32(s, t0, 0); - tcg_gen_op5_i32(s, INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); - tcg_temp_free_i32(s, t0); - } else { - gen_helper_divu_i32(s, ret, arg1, arg2); - } -} +/* 64 bit ops */ -static inline void tcg_gen_remu_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (TCG_TARGET_HAS_rem_i32) { - tcg_gen_op3_i32(s, INDEX_op_remu_i32, ret, arg1, arg2); - } else if (TCG_TARGET_HAS_div_i32) { - TCGv_i32 t0 = tcg_temp_new_i32(s); - tcg_gen_op3_i32(s, INDEX_op_divu_i32, t0, arg1, arg2); - tcg_gen_mul_i32(s, t0, t0, arg2); - tcg_gen_sub_i32(s, ret, arg1, t0); - tcg_temp_free_i32(s, t0); - } else if (TCG_TARGET_HAS_div2_i32) { - TCGv_i32 t0 = tcg_temp_new_i32(s); - tcg_gen_movi_i32(s, t0, 0); - tcg_gen_op5_i32(s, INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); - tcg_temp_free_i32(s, t0); - } else { - gen_helper_remu_i32(s, ret, arg1, arg2); - } -} +void tcg_gen_addi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_subfi_i64(TCGContext *s, TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); +void tcg_gen_subi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_andi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); +void tcg_gen_ori_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_xori_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_shli_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); +void tcg_gen_shri_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); +void tcg_gen_sari_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); +void tcg_gen_muli_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_div_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_rem_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_divu_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_remu_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_andc_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_eqv_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_nand_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_nor_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_orc_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_rotl_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_rotli_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); +void tcg_gen_rotr_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_rotri_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); +void tcg_gen_deposit_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, + unsigned int ofs, unsigned int len); +void tcg_gen_brcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, int label); +void tcg_gen_brcondi_i64(TCGContext *s, TCGCond cond, TCGv_i64 arg1, int64_t arg2, int label); +void tcg_gen_setcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 ret, + TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_setcondi_i64(TCGContext *s, TCGCond cond, TCGv_i64 ret, + TCGv_i64 arg1, int64_t arg2); +void tcg_gen_movcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, + TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); +void tcg_gen_add2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, + TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); +void tcg_gen_sub2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, + TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); +void tcg_gen_mulu2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_muls2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_not_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext8s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext16s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext32s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext8u_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext16u_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext32u_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_bswap16_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_bswap32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_bswap64_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); -#if TCG_TARGET_REG_BITS == 32 +#if TCG_TARGET_REG_BITS == 64 +static inline void tcg_gen_discard_i64(TCGContext *s, TCGv_i64 arg) +{ + tcg_gen_op1_i64(s, INDEX_op_discard, arg); +} static inline void tcg_gen_mov_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) { if (!TCGV_EQUAL_I64(ret, arg)) { - tcg_gen_mov_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); - tcg_gen_mov_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg)); - } -} - -static inline void tcg_gen_movi_i64(TCGContext *s, TCGv_i64 ret, int64_t arg) -{ - tcg_gen_movi_i32(s, TCGV_LOW(ret), (int32_t)arg); - tcg_gen_movi_i32(s, TCGV_HIGH(ret), arg >> 32); -} - -static inline void tcg_gen_ld8u_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ld8u_i32(s, TCGV_LOW(ret), arg2, offset); - tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); -} - -static inline void tcg_gen_ld8s_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ld8s_i32(s, TCGV_LOW(ret), arg2, offset); - tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_HIGH(ret), 31); -} - -static inline void tcg_gen_ld16u_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ld16u_i32(s, TCGV_LOW(ret), arg2, offset); - tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); -} - -static inline void tcg_gen_ld16s_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ld16s_i32(s, TCGV_LOW(ret), arg2, offset); - tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_LOW(ret), 31); -} - -static inline void tcg_gen_ld32u_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ld_i32(s, TCGV_LOW(ret), arg2, offset); - tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); -} - -static inline void tcg_gen_ld32s_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ld_i32(s, TCGV_LOW(ret), arg2, offset); - tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_LOW(ret), 31); -} - -static inline void tcg_gen_ld_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - /* since arg2 and ret have different types, they cannot be the - same temporary */ -#ifdef HOST_WORDS_BIGENDIAN - tcg_gen_ld_i32(s, TCGV_HIGH(ret), arg2, offset); - tcg_gen_ld_i32(s, TCGV_LOW(ret), arg2, offset + 4); -#else - tcg_gen_ld_i32(s, TCGV_LOW(ret), arg2, offset); - tcg_gen_ld_i32(s, TCGV_HIGH(ret), arg2, offset + 4); -#endif -} - -static inline void tcg_gen_st8_i64(TCGContext *s, TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_st8_i32(s, TCGV_LOW(arg1), arg2, offset); -} - -static inline void tcg_gen_st16_i64(TCGContext *s, TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_st16_i32(s, TCGV_LOW(arg1), arg2, offset); -} - -static inline void tcg_gen_st32_i64(TCGContext *s, TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_st_i32(s, TCGV_LOW(arg1), arg2, offset); -} - -static inline void tcg_gen_st_i64(TCGContext *s, TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ -#ifdef HOST_WORDS_BIGENDIAN - tcg_gen_st_i32(s, TCGV_HIGH(arg1), arg2, offset); - tcg_gen_st_i32(s, TCGV_LOW(arg1), arg2, offset + 4); -#else - tcg_gen_st_i32(s, TCGV_LOW(arg1), arg2, offset); - tcg_gen_st_i32(s, TCGV_HIGH(arg1), arg2, offset + 4); -#endif -} - -static inline void tcg_gen_add_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op6_i32(s, INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), - TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), - TCGV_HIGH(arg2)); - /* Allow the optimizer room to replace add2 with two moves. */ - tcg_gen_op0(s, INDEX_op_nop); -} - -static inline void tcg_gen_sub_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op6_i32(s, INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), - TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), - TCGV_HIGH(arg2)); - /* Allow the optimizer room to replace sub2 with two moves. */ - tcg_gen_op0(s, INDEX_op_nop); -} - -static inline void tcg_gen_and_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_and_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_and_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); -} - -static inline void tcg_gen_andi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - tcg_gen_andi_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), (uint32_t)arg2); - tcg_gen_andi_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); -} - -static inline void tcg_gen_or_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_or_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_or_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); -} - -static inline void tcg_gen_ori_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - tcg_gen_ori_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), (uint32_t)arg2); - tcg_gen_ori_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); -} - -static inline void tcg_gen_xor_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_xor_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_xor_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); -} - -static inline void tcg_gen_xori_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - tcg_gen_xori_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), (int32_t)arg2); - tcg_gen_xori_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); -} - -/* XXX: use generic code when basic block handling is OK or CPU - specific code (x86) */ -static inline void tcg_gen_shl_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - gen_helper_shl_i64(s, ret, arg1, arg2); -} - -static inline void tcg_gen_shli_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - tcg_gen_shifti_i64(s, ret, arg1, (int)arg2, 0, 0); -} - -static inline void tcg_gen_shr_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - gen_helper_shr_i64(s, ret, arg1, arg2); -} - -static inline void tcg_gen_shri_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - tcg_gen_shifti_i64(s, ret, arg1, (int)arg2, 1, 0); -} - -static inline void tcg_gen_sar_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - gen_helper_sar_i64(s, ret, arg1, arg2); -} - -static inline void tcg_gen_sari_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - tcg_gen_shifti_i64(s, ret, arg1, (int)arg2, 1, 1); -} - -static inline void tcg_gen_brcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 arg1, - TCGv_i64 arg2, int label_index) -{ - if (cond == TCG_COND_ALWAYS) { - tcg_gen_br(s, label_index); - } else if (cond != TCG_COND_NEVER) { - tcg_gen_op6ii_i32(s, INDEX_op_brcond2_i32, - TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), - TCGV_HIGH(arg2), cond, label_index); - } -} - -static inline void tcg_gen_setcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (cond == TCG_COND_ALWAYS) { - tcg_gen_movi_i32(s, TCGV_LOW(ret), 1); - } else if (cond == TCG_COND_NEVER) { - tcg_gen_movi_i32(s, TCGV_LOW(ret), 0); - } else { - tcg_gen_op6i_i32(s, INDEX_op_setcond2_i32, TCGV_LOW(ret), - TCGV_LOW(arg1), TCGV_HIGH(arg1), - TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); - } - tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); -} - -static inline void tcg_gen_mul_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - TCGv_i64 t0; - TCGv_i32 t1; - - t0 = tcg_temp_new_i64(s); - t1 = tcg_temp_new_i32(s); - - if (TCG_TARGET_HAS_mulu2_i32) { - tcg_gen_op4_i32(s, INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0), - TCGV_LOW(arg1), TCGV_LOW(arg2)); - /* Allow the optimizer room to replace mulu2 with two moves. */ - tcg_gen_op0(s, INDEX_op_nop); - } else { - tcg_debug_assert(TCG_TARGET_HAS_muluh_i32); - tcg_gen_op3_i32(s, INDEX_op_mul_i32, TCGV_LOW(t0), - TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_op3_i32(s, INDEX_op_muluh_i32, TCGV_HIGH(t0), - TCGV_LOW(arg1), TCGV_LOW(arg2)); - } - - tcg_gen_mul_i32(s, t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); - tcg_gen_add_i32(s, TCGV_HIGH(t0), TCGV_HIGH(t0), t1); - tcg_gen_mul_i32(s, t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); - tcg_gen_add_i32(s, TCGV_HIGH(t0), TCGV_HIGH(t0), t1); - - tcg_gen_mov_i64(s, ret, t0); - tcg_temp_free_i64(s, t0); - tcg_temp_free_i32(s, t1); -} - -static inline void tcg_gen_div_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - gen_helper_div_i64(s, ret, arg1, arg2); -} - -static inline void tcg_gen_rem_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - gen_helper_rem_i64(s, ret, arg1, arg2); -} - -static inline void tcg_gen_divu_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - gen_helper_divu_i64(s, ret, arg1, arg2); -} - -static inline void tcg_gen_remu_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - gen_helper_remu_i64(s, ret, arg1, arg2); -} - -#else - -static inline void tcg_gen_mov_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - if (!TCGV_EQUAL_I64(ret, arg)) tcg_gen_op2_i64(s, INDEX_op_mov_i64, ret, arg); + } } static inline void tcg_gen_movi_i64(TCGContext *s, TCGv_i64 ret, int64_t arg) @@ -1050,7 +548,8 @@ static inline void tcg_gen_ld32s_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_gen_ldst_op_i64(s, INDEX_op_ld32s_i64, ret, arg2, offset); } -static inline void tcg_gen_ld_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +static inline void tcg_gen_ld_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) { tcg_gen_ldst_op_i64(s, INDEX_op_ld_i64, ret, arg2, offset); } @@ -1073,7 +572,8 @@ static inline void tcg_gen_st32_i64(TCGContext *s, TCGv_i64 arg1, TCGv_ptr arg2, tcg_gen_ldst_op_i64(s, INDEX_op_st32_i64, arg1, arg2, offset); } -static inline void tcg_gen_st_i64(TCGContext *s, TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) +static inline void tcg_gen_st_i64(TCGContext *s, TCGv_i64 arg1, TCGv_ptr arg2, + tcg_target_long offset) { tcg_gen_ldst_op_i64(s, INDEX_op_st_i64, arg1, arg2, offset); } @@ -1090,94 +590,17 @@ static inline void tcg_gen_sub_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, T static inline void tcg_gen_and_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCGV_EQUAL_I64(arg1, arg2)) { - tcg_gen_mov_i64(s, ret, arg1); - } else { - tcg_gen_op3_i64(s, INDEX_op_and_i64, ret, arg1, arg2); - } -} - -static inline void tcg_gen_andi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) -{ - TCGv_i64 t0; - /* Some cases can be optimized here. */ - switch (arg2) { - case 0: - tcg_gen_movi_i64(s, ret, 0); - return; - case 0xffffffffffffffffull: - tcg_gen_mov_i64(s, ret, arg1); - return; - case 0xffull: - /* Don't recurse with tcg_gen_ext8u_i32. */ - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_op2_i64(s, INDEX_op_ext8u_i64, ret, arg1); - return; - } - break; - case 0xffffu: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_op2_i64(s, INDEX_op_ext16u_i64, ret, arg1); - return; - } - break; - case 0xffffffffull: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_op2_i64(s, INDEX_op_ext32u_i64, ret, arg1); - return; - } - break; - } - t0 = tcg_const_i64(s, arg2); - tcg_gen_and_i64(s, ret, arg1, t0); - tcg_temp_free_i64(s, t0); + tcg_gen_op3_i64(s, INDEX_op_and_i64, ret, arg1, arg2); } static inline void tcg_gen_or_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCGV_EQUAL_I64(arg1, arg2)) { - tcg_gen_mov_i64(s, ret, arg1); - } else { - tcg_gen_op3_i64(s, INDEX_op_or_i64, ret, arg1, arg2); - } -} - -static inline void tcg_gen_ori_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - /* Some cases can be optimized here. */ - if (arg2 == -1) { - tcg_gen_movi_i64(s, ret, -1); - } else if (arg2 == 0) { - tcg_gen_mov_i64(s, ret, arg1); - } else { - TCGv_i64 t0 = tcg_const_i64(s, arg2); - tcg_gen_or_i64(s, ret, arg1, t0); - tcg_temp_free_i64(s, t0); - } + tcg_gen_op3_i64(s, INDEX_op_or_i64, ret, arg1, arg2); } static inline void tcg_gen_xor_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCGV_EQUAL_I64(arg1, arg2)) { - tcg_gen_movi_i64(s, ret, 0); - } else { - tcg_gen_op3_i64(s, INDEX_op_xor_i64, ret, arg1, arg2); - } -} - -static inline void tcg_gen_xori_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - /* Some cases can be optimized here. */ - if (arg2 == 0) { - tcg_gen_mov_i64(s, ret, arg1); - } else if (arg2 == -1 && TCG_TARGET_HAS_not_i64) { - /* Don't recurse with tcg_gen_not_i64. */ - tcg_gen_op2_i64(s, INDEX_op_not_i64, ret, arg1); - } else { - TCGv_i64 t0 = tcg_const_i64(s, arg2); - tcg_gen_xor_i64(s, ret, arg1, t0); - tcg_temp_free_i64(s, t0); - } + tcg_gen_op3_i64(s, INDEX_op_xor_i64, ret, arg1, arg2); } static inline void tcg_gen_shl_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) @@ -1185,993 +608,92 @@ static inline void tcg_gen_shl_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, T tcg_gen_op3_i64(s, INDEX_op_shl_i64, ret, arg1, arg2); } -static inline void tcg_gen_shli_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - if (arg2 == 0) { - tcg_gen_mov_i64(s, ret, arg1); - } else { - TCGv_i64 t0 = tcg_const_i64(s, arg2); - tcg_gen_shl_i64(s, ret, arg1, t0); - tcg_temp_free_i64(s, t0); - } -} - static inline void tcg_gen_shr_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(s, INDEX_op_shr_i64, ret, arg1, arg2); } -static inline void tcg_gen_shri_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - if (arg2 == 0) { - tcg_gen_mov_i64(s, ret, arg1); - } else { - TCGv_i64 t0 = tcg_const_i64(s, arg2); - tcg_gen_shr_i64(s, ret, arg1, t0); - tcg_temp_free_i64(s, t0); - } -} - static inline void tcg_gen_sar_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(s, INDEX_op_sar_i64, ret, arg1, arg2); } -static inline void tcg_gen_sari_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - if (arg2 == 0) { - tcg_gen_mov_i64(s, ret, arg1); - } else { - TCGv_i64 t0 = tcg_const_i64(s, arg2); - tcg_gen_sar_i64(s, ret, arg1, t0); - tcg_temp_free_i64(s, t0); - } -} - -static inline void tcg_gen_brcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 arg1, - TCGv_i64 arg2, int label_index) -{ - if (cond == TCG_COND_ALWAYS) { - tcg_gen_br(s, label_index); - } else if (cond != TCG_COND_NEVER) { - tcg_gen_op4ii_i64(s, INDEX_op_brcond_i64, arg1, arg2, cond, label_index); - } -} - -static inline void tcg_gen_setcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (cond == TCG_COND_ALWAYS) { - tcg_gen_movi_i64(s, ret, 1); - } else if (cond == TCG_COND_NEVER) { - tcg_gen_movi_i64(s, ret, 0); - } else { - tcg_gen_op4i_i64(s, INDEX_op_setcond_i64, ret, arg1, arg2, cond); - } -} - static inline void tcg_gen_mul_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(s, INDEX_op_mul_i64, ret, arg1, arg2); } - -static inline void tcg_gen_div_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +#else /* TCG_TARGET_REG_BITS == 32 */ +static inline void tcg_gen_st8_i64(TCGContext *s, TCGv_i64 arg1, TCGv_ptr arg2, + tcg_target_long offset) { - if (TCG_TARGET_HAS_div_i64) { - tcg_gen_op3_i64(s, INDEX_op_div_i64, ret, arg1, arg2); - } else if (TCG_TARGET_HAS_div2_i64) { - TCGv_i64 t0 = tcg_temp_new_i64(s); - tcg_gen_sari_i64(s, t0, arg1, 63); - tcg_gen_op5_i64(s, INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); - tcg_temp_free_i64(s, t0); - } else { - gen_helper_div_i64(s, ret, arg1, arg2); - } + tcg_gen_st8_i32(s, TCGV_LOW(arg1), arg2, offset); } -static inline void tcg_gen_rem_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +static inline void tcg_gen_st16_i64(TCGContext *s, TCGv_i64 arg1, TCGv_ptr arg2, + tcg_target_long offset) { - if (TCG_TARGET_HAS_rem_i64) { - tcg_gen_op3_i64(s, INDEX_op_rem_i64, ret, arg1, arg2); - } else if (TCG_TARGET_HAS_div_i64) { - TCGv_i64 t0 = tcg_temp_new_i64(s); - tcg_gen_op3_i64(s, INDEX_op_div_i64, t0, arg1, arg2); - tcg_gen_mul_i64(s, t0, t0, arg2); - tcg_gen_sub_i64(s, ret, arg1, t0); - tcg_temp_free_i64(s, t0); - } else if (TCG_TARGET_HAS_div2_i64) { - TCGv_i64 t0 = tcg_temp_new_i64(s); - tcg_gen_sari_i64(s, t0, arg1, 63); - tcg_gen_op5_i64(s, INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); - tcg_temp_free_i64(s, t0); - } else { - gen_helper_rem_i64(s, ret, arg1, arg2); - } + tcg_gen_st16_i32(s, TCGV_LOW(arg1), arg2, offset); } -static inline void tcg_gen_divu_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +static inline void tcg_gen_st32_i64(TCGContext *s, TCGv_i64 arg1, TCGv_ptr arg2, + tcg_target_long offset) { - if (TCG_TARGET_HAS_div_i64) { - tcg_gen_op3_i64(s, INDEX_op_divu_i64, ret, arg1, arg2); - } else if (TCG_TARGET_HAS_div2_i64) { - TCGv_i64 t0 = tcg_temp_new_i64(s); - tcg_gen_movi_i64(s, t0, 0); - tcg_gen_op5_i64(s, INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); - tcg_temp_free_i64(s, t0); - } else { - gen_helper_divu_i64(s, ret, arg1, arg2); - } + tcg_gen_st_i32(s, TCGV_LOW(arg1), arg2, offset); } -static inline void tcg_gen_remu_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +static inline void tcg_gen_add_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_HAS_rem_i64) { - tcg_gen_op3_i64(s, INDEX_op_remu_i64, ret, arg1, arg2); - } else if (TCG_TARGET_HAS_div_i64) { - TCGv_i64 t0 = tcg_temp_new_i64(s); - tcg_gen_op3_i64(s, INDEX_op_divu_i64, t0, arg1, arg2); - tcg_gen_mul_i64(s, t0, t0, arg2); - tcg_gen_sub_i64(s, ret, arg1, t0); - tcg_temp_free_i64(s, t0); - } else if (TCG_TARGET_HAS_div2_i64) { - TCGv_i64 t0 = tcg_temp_new_i64(s); - tcg_gen_movi_i64(s, t0, 0); - tcg_gen_op5_i64(s, INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); - tcg_temp_free_i64(s, t0); - } else { - gen_helper_remu_i64(s, ret, arg1, arg2); - } -} -#endif /* TCG_TARGET_REG_BITS == 32 */ - -static inline void tcg_gen_addi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - /* some cases can be optimized here */ - if (arg2 == 0) { - tcg_gen_mov_i64(s, ret, arg1); - } else { - TCGv_i64 t0 = tcg_const_i64(s, arg2); - tcg_gen_add_i64(s, ret, arg1, t0); - tcg_temp_free_i64(s, t0); - } + tcg_gen_add2_i32(s, TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), + TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); } -static inline void tcg_gen_subfi_i64(TCGContext *s, TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) +static inline void tcg_gen_sub_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - TCGv_i64 t0 = tcg_const_i64(s, arg1); - tcg_gen_sub_i64(s, ret, t0, arg2); - tcg_temp_free_i64(s, t0); + tcg_gen_sub2_i32(s, TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), + TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); } -static inline void tcg_gen_subi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - /* some cases can be optimized here */ - if (arg2 == 0) { - tcg_gen_mov_i64(s, ret, arg1); - } else { - TCGv_i64 t0 = tcg_const_i64(s, arg2); - tcg_gen_sub_i64(s, ret, arg1, t0); - tcg_temp_free_i64(s, t0); - } -} -static inline void tcg_gen_brcondi_i64(TCGContext *s, TCGCond cond, TCGv_i64 arg1, - int64_t arg2, int label_index) -{ - if (cond == TCG_COND_ALWAYS) { - tcg_gen_br(s, label_index); - } else if (cond != TCG_COND_NEVER) { - TCGv_i64 t0 = tcg_const_i64(s, arg2); - tcg_gen_brcond_i64(s, cond, arg1, t0, label_index); - tcg_temp_free_i64(s, t0); - } -} - -static inline void tcg_gen_setcondi_i64(TCGContext *s, TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, int64_t arg2) -{ - TCGv_i64 t0 = tcg_const_i64(s, arg2); - tcg_gen_setcond_i64(s, cond, ret, arg1, t0); - tcg_temp_free_i64(s, t0); -} - -static inline void tcg_gen_muli_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - TCGv_i64 t0 = tcg_const_i64(s, arg2); - tcg_gen_mul_i64(s, ret, arg1, t0); - tcg_temp_free_i64(s, t0); -} - - -/***************************************/ -/* optional operations */ - -static inline void tcg_gen_ext8s_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) -{ - if (TCG_TARGET_HAS_ext8s_i32) { - tcg_gen_op2_i32(s, INDEX_op_ext8s_i32, ret, arg); - } else { - tcg_gen_shli_i32(s, ret, arg, 24); - tcg_gen_sari_i32(s, ret, ret, 24); - } -} - -static inline void tcg_gen_ext16s_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) -{ - if (TCG_TARGET_HAS_ext16s_i32) { - tcg_gen_op2_i32(s, INDEX_op_ext16s_i32, ret, arg); - } else { - tcg_gen_shli_i32(s, ret, arg, 16); - tcg_gen_sari_i32(s, ret, ret, 16); - } -} - -static inline void tcg_gen_ext8u_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) -{ - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_op2_i32(s, INDEX_op_ext8u_i32, ret, arg); - } else { - tcg_gen_andi_i32(s, ret, arg, 0xffu); - } -} - -static inline void tcg_gen_ext16u_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) -{ - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_op2_i32(s, INDEX_op_ext16u_i32, ret, arg); - } else { - tcg_gen_andi_i32(s, ret, arg, 0xffffu); - } -} - -/* Note: we assume the two high bytes are set to zero */ -static inline void tcg_gen_bswap16_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) -{ - if (TCG_TARGET_HAS_bswap16_i32) { - tcg_gen_op2_i32(s, INDEX_op_bswap16_i32, ret, arg); - } else { - TCGv_i32 t0 = tcg_temp_new_i32(s); - - tcg_gen_ext8u_i32(s, t0, arg); - tcg_gen_shli_i32(s, t0, t0, 8); - tcg_gen_shri_i32(s, ret, arg, 8); - tcg_gen_or_i32(s, ret, ret, t0); - tcg_temp_free_i32(s, t0); - } -} - -static inline void tcg_gen_bswap32_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) -{ - if (TCG_TARGET_HAS_bswap32_i32) { - tcg_gen_op2_i32(s, INDEX_op_bswap32_i32, ret, arg); - } else { - TCGv_i32 t0, t1; - t0 = tcg_temp_new_i32(s); - t1 = tcg_temp_new_i32(s); - - tcg_gen_shli_i32(s, t0, arg, 24); - - tcg_gen_andi_i32(s, t1, arg, 0x0000ff00); - tcg_gen_shli_i32(s, t1, t1, 8); - tcg_gen_or_i32(s, t0, t0, t1); - - tcg_gen_shri_i32(s, t1, arg, 8); - tcg_gen_andi_i32(s, t1, t1, 0x0000ff00); - tcg_gen_or_i32(s, t0, t0, t1); - - tcg_gen_shri_i32(s, t1, arg, 24); - tcg_gen_or_i32(s, ret, t0, t1); - tcg_temp_free_i32(s, t0); - tcg_temp_free_i32(s, t1); - } -} - -#if TCG_TARGET_REG_BITS == 32 -static inline void tcg_gen_ext8s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - tcg_gen_ext8s_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); - tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_LOW(ret), 31); -} - -static inline void tcg_gen_ext16s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - tcg_gen_ext16s_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); - tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_LOW(ret), 31); -} - -static inline void tcg_gen_ext32s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - tcg_gen_mov_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); - tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_LOW(ret), 31); -} - -static inline void tcg_gen_ext8u_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - tcg_gen_ext8u_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); - tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); -} - -static inline void tcg_gen_ext16u_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - tcg_gen_ext16u_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); - tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); -} - -static inline void tcg_gen_ext32u_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - tcg_gen_mov_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); - tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); -} - -static inline void tcg_gen_trunc_shr_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg, - unsigned int count) -{ - tcg_debug_assert(count < 64); - if (count >= 32) { - tcg_gen_shri_i32(s, ret, TCGV_HIGH(arg), count - 32); - } else if (count == 0) { - tcg_gen_mov_i32(s, ret, TCGV_LOW(arg)); - } else { - TCGv_i64 t = tcg_temp_new_i64(s); - tcg_gen_shri_i64(s, t, arg, count); - tcg_gen_mov_i32(s, ret, TCGV_LOW(t)); - tcg_temp_free_i64(s, t); - } -} - -static inline void tcg_gen_extu_i32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i32 arg) -{ - tcg_gen_mov_i32(s, TCGV_LOW(ret), arg); - tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); -} - -static inline void tcg_gen_ext_i32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i32 arg) -{ - tcg_gen_mov_i32(s, TCGV_LOW(ret), arg); - tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_LOW(ret), 31); -} - -/* Note: we assume the six high bytes are set to zero */ -static inline void tcg_gen_bswap16_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - tcg_gen_mov_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg)); - tcg_gen_bswap16_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); -} - -/* Note: we assume the four high bytes are set to zero */ -static inline void tcg_gen_bswap32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - tcg_gen_mov_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg)); - tcg_gen_bswap32_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); -} - -static inline void tcg_gen_bswap64_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - TCGv_i32 t0, t1; - t0 = tcg_temp_new_i32(s); - t1 = tcg_temp_new_i32(s); - - tcg_gen_bswap32_i32(s, t0, TCGV_LOW(arg)); - tcg_gen_bswap32_i32(s, t1, TCGV_HIGH(arg)); - tcg_gen_mov_i32(s, TCGV_LOW(ret), t1); - tcg_gen_mov_i32(s, TCGV_HIGH(ret), t0); - tcg_temp_free_i32(s, t0); - tcg_temp_free_i32(s, t1); -} -#else - -static inline void tcg_gen_ext8s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - if (TCG_TARGET_HAS_ext8s_i64) { - tcg_gen_op2_i64(s, INDEX_op_ext8s_i64, ret, arg); - } else { - tcg_gen_shli_i64(s, ret, arg, 56); - tcg_gen_sari_i64(s, ret, ret, 56); - } -} - -static inline void tcg_gen_ext16s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - if (TCG_TARGET_HAS_ext16s_i64) { - tcg_gen_op2_i64(s, INDEX_op_ext16s_i64, ret, arg); - } else { - tcg_gen_shli_i64(s, ret, arg, 48); - tcg_gen_sari_i64(s, ret, ret, 48); - } -} - -static inline void tcg_gen_ext32s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - if (TCG_TARGET_HAS_ext32s_i64) { - tcg_gen_op2_i64(s, INDEX_op_ext32s_i64, ret, arg); - } else { - tcg_gen_shli_i64(s, ret, arg, 32); - tcg_gen_sari_i64(s, ret, ret, 32); - } -} - -static inline void tcg_gen_ext8u_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_op2_i64(s, INDEX_op_ext8u_i64, ret, arg); - } else { - tcg_gen_andi_i64(s, ret, arg, 0xffu); - } -} - -static inline void tcg_gen_ext16u_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_op2_i64(s, INDEX_op_ext16u_i64, ret, arg); - } else { - tcg_gen_andi_i64(s, ret, arg, 0xffffu); - } -} - -static inline void tcg_gen_ext32u_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_op2_i64(s, INDEX_op_ext32u_i64, ret, arg); - } else { - tcg_gen_andi_i64(s, ret, arg, 0xffffffffu); - } -} - -static inline void tcg_gen_trunc_shr_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg, - unsigned int count) -{ - tcg_debug_assert(count < 64); - if (TCG_TARGET_HAS_trunc_shr_i32) { - tcg_gen_op3i_i32(s, INDEX_op_trunc_shr_i32, ret, - MAKE_TCGV_I32(GET_TCGV_I64(arg)), count); - } else if (count == 0) { - tcg_gen_mov_i32(s, ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); - } else { - TCGv_i64 t = tcg_temp_new_i64(s); - tcg_gen_shri_i64(s, t, arg, count); - tcg_gen_mov_i32(s, ret, MAKE_TCGV_I32(GET_TCGV_I64(t))); - tcg_temp_free_i64(s, t); - } -} - -/* Note: we assume the target supports move between 32 and 64 bit - registers */ -static inline void tcg_gen_extu_i32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i32 arg) -{ - tcg_gen_ext32u_i64(s, ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); -} - -/* Note: we assume the target supports move between 32 and 64 bit - registers */ -static inline void tcg_gen_ext_i32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i32 arg) -{ - tcg_gen_ext32s_i64(s, ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); -} - -/* Note: we assume the six high bytes are set to zero */ -static inline void tcg_gen_bswap16_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - if (TCG_TARGET_HAS_bswap16_i64) { - tcg_gen_op2_i64(s, INDEX_op_bswap16_i64, ret, arg); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(s); - - tcg_gen_ext8u_i64(s, t0, arg); - tcg_gen_shli_i64(s, t0, t0, 8); - tcg_gen_shri_i64(s, ret, arg, 8); - tcg_gen_or_i64(s, ret, ret, t0); - tcg_temp_free_i64(s, t0); - } -} - -/* Note: we assume the four high bytes are set to zero */ -static inline void tcg_gen_bswap32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - if (TCG_TARGET_HAS_bswap32_i64) { - tcg_gen_op2_i64(s, INDEX_op_bswap32_i64, ret, arg); - } else { - TCGv_i64 t0, t1; - t0 = tcg_temp_new_i64(s); - t1 = tcg_temp_new_i64(s); - - tcg_gen_shli_i64(s, t0, arg, 24); - tcg_gen_ext32u_i64(s, t0, t0); - - tcg_gen_andi_i64(s, t1, arg, 0x0000ff00); - tcg_gen_shli_i64(s, t1, t1, 8); - tcg_gen_or_i64(s, t0, t0, t1); - - tcg_gen_shri_i64(s, t1, arg, 8); - tcg_gen_andi_i64(s, t1, t1, 0x0000ff00); - tcg_gen_or_i64(s, t0, t0, t1); - - tcg_gen_shri_i64(s, t1, arg, 24); - tcg_gen_or_i64(s, ret, t0, t1); - tcg_temp_free_i64(s, t0); - tcg_temp_free_i64(s, t1); - } -} - -static inline void tcg_gen_bswap64_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ - if (TCG_TARGET_HAS_bswap64_i64) { - tcg_gen_op2_i64(s, INDEX_op_bswap64_i64, ret, arg); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(s); - TCGv_i64 t1 = tcg_temp_new_i64(s); - - tcg_gen_shli_i64(s, t0, arg, 56); - - tcg_gen_andi_i64(s, t1, arg, 0x0000ff00); - tcg_gen_shli_i64(s, t1, t1, 40); - tcg_gen_or_i64(s, t0, t0, t1); - - tcg_gen_andi_i64(s, t1, arg, 0x00ff0000); - tcg_gen_shli_i64(s, t1, t1, 24); - tcg_gen_or_i64(s, t0, t0, t1); - - tcg_gen_andi_i64(s, t1, arg, 0xff000000); - tcg_gen_shli_i64(s, t1, t1, 8); - tcg_gen_or_i64(s, t0, t0, t1); - - tcg_gen_shri_i64(s, t1, arg, 8); - tcg_gen_andi_i64(s, t1, t1, 0xff000000); - tcg_gen_or_i64(s, t0, t0, t1); - - tcg_gen_shri_i64(s, t1, arg, 24); - tcg_gen_andi_i64(s, t1, t1, 0x00ff0000); - tcg_gen_or_i64(s, t0, t0, t1); - - tcg_gen_shri_i64(s, t1, arg, 40); - tcg_gen_andi_i64(s, t1, t1, 0x0000ff00); - tcg_gen_or_i64(s, t0, t0, t1); - - tcg_gen_shri_i64(s, t1, arg, 56); - tcg_gen_or_i64(s, ret, t0, t1); - tcg_temp_free_i64(s, t0); - tcg_temp_free_i64(s, t1); - } -} - -#endif - -static inline void tcg_gen_neg_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) -{ - if (TCG_TARGET_HAS_neg_i32) { - tcg_gen_op2_i32(s, INDEX_op_neg_i32, ret, arg); - } else { - TCGv_i32 t0 = tcg_const_i32(s, 0); - tcg_gen_sub_i32(s, ret, t0, arg); - tcg_temp_free_i32(s, t0); - } -} +void tcg_gen_discard_i64(TCGContext *s, TCGv_i64 arg); +void tcg_gen_mov_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_movi_i64(TCGContext *s, TCGv_i64 ret, int64_t arg); +void tcg_gen_ld8u_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld8s_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld16u_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld16s_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld32u_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld32s_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld_i64(TCGContext *s, TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_st_i64(TCGContext *s, TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_and_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_or_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_xor_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_shl_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_shr_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_sar_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_mul_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +#endif /* TCG_TARGET_REG_BITS */ static inline void tcg_gen_neg_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) { if (TCG_TARGET_HAS_neg_i64) { tcg_gen_op2_i64(s, INDEX_op_neg_i64, ret, arg); } else { - TCGv_i64 t0 = tcg_const_i64(s, 0); - tcg_gen_sub_i64(s, ret, t0, arg); - tcg_temp_free_i64(s, t0); + tcg_gen_subfi_i64(s, ret, 0, arg); } } -static inline void tcg_gen_not_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) +/* Size changing operations. */ + +void tcg_gen_extu_i32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i32 arg); +void tcg_gen_ext_i32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i32 arg); +void tcg_gen_concat_i32_i64(TCGContext *s, TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high); +void tcg_gen_trunc_shr_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg, unsigned int c); +void tcg_gen_extr_i64_i32(TCGContext *s, TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); +void tcg_gen_extr32_i64(TCGContext *s, TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); + +static inline void tcg_gen_concat32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) { - if (TCG_TARGET_HAS_not_i32) { - tcg_gen_op2_i32(s, INDEX_op_not_i32, ret, arg); - } else { - tcg_gen_xori_i32(s, ret, arg, -1); - } -} - -static inline void tcg_gen_not_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) -{ -#if TCG_TARGET_REG_BITS == 64 - if (TCG_TARGET_HAS_not_i64) { - tcg_gen_op2_i64(s, INDEX_op_not_i64, ret, arg); - } else { - tcg_gen_xori_i64(s, ret, arg, -1); - } -#else - tcg_gen_not_i32(s, TCGV_LOW(ret), TCGV_LOW(arg)); - tcg_gen_not_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg)); -#endif -} - -static inline void tcg_gen_discard_i32(TCGContext *s, TCGv_i32 arg) -{ - tcg_gen_op1_i32(s, INDEX_op_discard, arg); -} - -static inline void tcg_gen_discard_i64(TCGContext *s, TCGv_i64 arg) -{ -#if TCG_TARGET_REG_BITS == 32 - tcg_gen_discard_i32(s, TCGV_LOW(arg)); - tcg_gen_discard_i32(s, TCGV_HIGH(arg)); -#else - tcg_gen_op1_i64(s, INDEX_op_discard, arg); -#endif -} - -static inline void tcg_gen_andc_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (TCG_TARGET_HAS_andc_i32) { - tcg_gen_op3_i32(s, INDEX_op_andc_i32, ret, arg1, arg2); - } else { - TCGv_i32 t0 = tcg_temp_new_i32(s); - tcg_gen_not_i32(s, t0, arg2); - tcg_gen_and_i32(s, ret, arg1, t0); - tcg_temp_free_i32(s, t0); - } -} - -static inline void tcg_gen_andc_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ -#if TCG_TARGET_REG_BITS == 64 - if (TCG_TARGET_HAS_andc_i64) { - tcg_gen_op3_i64(s, INDEX_op_andc_i64, ret, arg1, arg2); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(s); - tcg_gen_not_i64(s, t0, arg2); - tcg_gen_and_i64(s, ret, arg1, t0); - tcg_temp_free_i64(s, t0); - } -#else - tcg_gen_andc_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_andc_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); -#endif -} - -static inline void tcg_gen_eqv_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (TCG_TARGET_HAS_eqv_i32) { - tcg_gen_op3_i32(s, INDEX_op_eqv_i32, ret, arg1, arg2); - } else { - tcg_gen_xor_i32(s, ret, arg1, arg2); - tcg_gen_not_i32(s, ret, ret); - } -} - -static inline void tcg_gen_eqv_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ -#if TCG_TARGET_REG_BITS == 64 - if (TCG_TARGET_HAS_eqv_i64) { - tcg_gen_op3_i64(s, INDEX_op_eqv_i64, ret, arg1, arg2); - } else { - tcg_gen_xor_i64(s, ret, arg1, arg2); - tcg_gen_not_i64(s, ret, ret); - } -#else - tcg_gen_eqv_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_eqv_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); -#endif -} - -static inline void tcg_gen_nand_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (TCG_TARGET_HAS_nand_i32) { - tcg_gen_op3_i32(s, INDEX_op_nand_i32, ret, arg1, arg2); - } else { - tcg_gen_and_i32(s, ret, arg1, arg2); - tcg_gen_not_i32(s, ret, ret); - } -} - -static inline void tcg_gen_nand_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ -#if TCG_TARGET_REG_BITS == 64 - if (TCG_TARGET_HAS_nand_i64) { - tcg_gen_op3_i64(s, INDEX_op_nand_i64, ret, arg1, arg2); - } else { - tcg_gen_and_i64(s, ret, arg1, arg2); - tcg_gen_not_i64(s, ret, ret); - } -#else - tcg_gen_nand_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_nand_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); -#endif -} - -static inline void tcg_gen_nor_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (TCG_TARGET_HAS_nor_i32) { - tcg_gen_op3_i32(s, INDEX_op_nor_i32, ret, arg1, arg2); - } else { - tcg_gen_or_i32(s, ret, arg1, arg2); - tcg_gen_not_i32(s, ret, ret); - } -} - -static inline void tcg_gen_nor_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ -#if TCG_TARGET_REG_BITS == 64 - if (TCG_TARGET_HAS_nor_i64) { - tcg_gen_op3_i64(s, INDEX_op_nor_i64, ret, arg1, arg2); - } else { - tcg_gen_or_i64(s, ret, arg1, arg2); - tcg_gen_not_i64(s, ret, ret); - } -#else - tcg_gen_nor_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_nor_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); -#endif -} - -static inline void tcg_gen_orc_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (TCG_TARGET_HAS_orc_i32) { - tcg_gen_op3_i32(s, INDEX_op_orc_i32, ret, arg1, arg2); - } else { - TCGv_i32 t0 = tcg_temp_new_i32(s); - tcg_gen_not_i32(s, t0, arg2); - tcg_gen_or_i32(s, ret, arg1, t0); - tcg_temp_free_i32(s, t0); - } -} - -static inline void tcg_gen_orc_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ -#if TCG_TARGET_REG_BITS == 64 - if (TCG_TARGET_HAS_orc_i64) { - tcg_gen_op3_i64(s, INDEX_op_orc_i64, ret, arg1, arg2); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(s); - tcg_gen_not_i64(s, t0, arg2); - tcg_gen_or_i64(s, ret, arg1, t0); - tcg_temp_free_i64(s, t0); - } -#else - tcg_gen_orc_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); - tcg_gen_orc_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); -#endif -} - -static inline void tcg_gen_rotl_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (TCG_TARGET_HAS_rot_i32) { - tcg_gen_op3_i32(s, INDEX_op_rotl_i32, ret, arg1, arg2); - } else { - TCGv_i32 t0, t1; - - t0 = tcg_temp_new_i32(s); - t1 = tcg_temp_new_i32(s); - tcg_gen_shl_i32(s, t0, arg1, arg2); - tcg_gen_subfi_i32(s, t1, 32, arg2); - tcg_gen_shr_i32(s, t1, arg1, t1); - tcg_gen_or_i32(s, ret, t0, t1); - tcg_temp_free_i32(s, t0); - tcg_temp_free_i32(s, t1); - } -} - -static inline void tcg_gen_rotl_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (TCG_TARGET_HAS_rot_i64) { - tcg_gen_op3_i64(s, INDEX_op_rotl_i64, ret, arg1, arg2); - } else { - TCGv_i64 t0, t1; - t0 = tcg_temp_new_i64(s); - t1 = tcg_temp_new_i64(s); - tcg_gen_shl_i64(s, t0, arg1, arg2); - tcg_gen_subfi_i64(s, t1, 64, arg2); - tcg_gen_shr_i64(s, t1, arg1, t1); - tcg_gen_or_i64(s, ret, t0, t1); - tcg_temp_free_i64(s, t0); - tcg_temp_free_i64(s, t1); - } -} - -static inline void tcg_gen_rotli_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - /* some cases can be optimized here */ - if (arg2 == 0) { - tcg_gen_mov_i32(s, ret, arg1); - } else if (TCG_TARGET_HAS_rot_i32) { - TCGv_i32 t0 = tcg_const_i32(s, arg2); - tcg_gen_rotl_i32(s, ret, arg1, t0); - tcg_temp_free_i32(s, t0); - } else { - TCGv_i32 t0, t1; - t0 = tcg_temp_new_i32(s); - t1 = tcg_temp_new_i32(s); - tcg_gen_shli_i32(s, t0, arg1, arg2); - tcg_gen_shri_i32(s, t1, arg1, 32 - arg2); - tcg_gen_or_i32(s, ret, t0, t1); - tcg_temp_free_i32(s, t0); - tcg_temp_free_i32(s, t1); - } -} - -static inline void tcg_gen_rotli_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - /* some cases can be optimized here */ - if (arg2 == 0) { - tcg_gen_mov_i64(s, ret, arg1); - } else if (TCG_TARGET_HAS_rot_i64) { - TCGv_i64 t0 = tcg_const_i64(s, arg2); - tcg_gen_rotl_i64(s, ret, arg1, t0); - tcg_temp_free_i64(s, t0); - } else { - TCGv_i64 t0, t1; - t0 = tcg_temp_new_i64(s); - t1 = tcg_temp_new_i64(s); - tcg_gen_shli_i64(s, t0, arg1, arg2); - tcg_gen_shri_i64(s, t1, arg1, 64 - arg2); - tcg_gen_or_i64(s, ret, t0, t1); - tcg_temp_free_i64(s, t0); - tcg_temp_free_i64(s, t1); - } -} - -static inline void tcg_gen_rotr_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (TCG_TARGET_HAS_rot_i32) { - tcg_gen_op3_i32(s, INDEX_op_rotr_i32, ret, arg1, arg2); - } else { - TCGv_i32 t0, t1; - - t0 = tcg_temp_new_i32(s); - t1 = tcg_temp_new_i32(s); - tcg_gen_shr_i32(s, t0, arg1, arg2); - tcg_gen_subfi_i32(s, t1, 32, arg2); - tcg_gen_shl_i32(s, t1, arg1, t1); - tcg_gen_or_i32(s, ret, t0, t1); - tcg_temp_free_i32(s, t0); - tcg_temp_free_i32(s, t1); - } -} - -static inline void tcg_gen_rotr_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (TCG_TARGET_HAS_rot_i64) { - tcg_gen_op3_i64(s, INDEX_op_rotr_i64, ret, arg1, arg2); - } else { - TCGv_i64 t0, t1; - t0 = tcg_temp_new_i64(s); - t1 = tcg_temp_new_i64(s); - tcg_gen_shr_i64(s, t0, arg1, arg2); - tcg_gen_subfi_i64(s, t1, 64, arg2); - tcg_gen_shl_i64(s, t1, arg1, t1); - tcg_gen_or_i64(s, ret, t0, t1); - tcg_temp_free_i64(s, t0); - tcg_temp_free_i64(s, t1); - } -} - -static inline void tcg_gen_rotri_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - /* some cases can be optimized here */ - if (arg2 == 0) { - tcg_gen_mov_i32(s, ret, arg1); - } else { - tcg_gen_rotli_i32(s, ret, arg1, 32 - arg2); - } -} - -static inline void tcg_gen_rotri_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - /* some cases can be optimized here */ - if (arg2 == 0) { - tcg_gen_mov_i64(s, ret, arg1); - } else { - tcg_gen_rotli_i64(s, ret, arg1, 64 - arg2); - } -} - -static inline void tcg_gen_deposit_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, - TCGv_i32 arg2, unsigned int ofs, - unsigned int len) -{ - uint32_t mask; - TCGv_i32 t1; - - tcg_debug_assert(ofs < 32); - tcg_debug_assert(len <= 32); - tcg_debug_assert(ofs + len <= 32); - - if (ofs == 0 && len == 32) { - tcg_gen_mov_i32(s, ret, arg2); - return; - } - if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) { - tcg_gen_op5ii_i32(s, INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len); - return; - } - - mask = (1u << len) - 1; - t1 = tcg_temp_new_i32(s); - - if (ofs + len < 32) { - tcg_gen_andi_i32(s, t1, arg2, mask); - tcg_gen_shli_i32(s, t1, t1, ofs); - } else { - tcg_gen_shli_i32(s, t1, arg2, ofs); - } - tcg_gen_andi_i32(s, ret, arg1, ~(mask << ofs)); - tcg_gen_or_i32(s, ret, ret, t1); - - tcg_temp_free_i32(s, t1); -} - -static inline void tcg_gen_deposit_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, - TCGv_i64 arg2, unsigned int ofs, - unsigned int len) -{ - uint64_t mask; - TCGv_i64 t1; - - tcg_debug_assert(ofs < 64); - tcg_debug_assert(len <= 64); - tcg_debug_assert(ofs + len <= 64); - - if (ofs == 0 && len == 64) { - tcg_gen_mov_i64(s, ret, arg2); - return; - } - if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) { - tcg_gen_op5ii_i64(s, INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len); - return; - } - -#if TCG_TARGET_REG_BITS == 32 - if (ofs >= 32) { - tcg_gen_deposit_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), - TCGV_LOW(arg2), ofs - 32, len); - tcg_gen_mov_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1)); - return; - } - if (ofs + len <= 32) { - tcg_gen_deposit_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), - TCGV_LOW(arg2), ofs, len); - tcg_gen_mov_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1)); - return; - } -#endif - - mask = (1ull << len) - 1; - t1 = tcg_temp_new_i64(s); - - if (ofs + len < 64) { - tcg_gen_andi_i64(s, t1, arg2, mask); - tcg_gen_shli_i64(s, t1, t1, ofs); - } else { - tcg_gen_shli_i64(s, t1, arg2, ofs); - } - tcg_gen_andi_i64(s, ret, arg1, ~(mask << ofs)); - tcg_gen_or_i64(s, ret, ret, t1); - - tcg_temp_free_i64(s, t1); -} - -static inline void tcg_gen_concat_i32_i64(TCGContext *s, TCGv_i64 dest, TCGv_i32 low, - TCGv_i32 high) -{ -#if TCG_TARGET_REG_BITS == 32 - tcg_gen_mov_i32(s, TCGV_LOW(dest), low); - tcg_gen_mov_i32(s, TCGV_HIGH(dest), high); -#else - TCGv_i64 tmp = tcg_temp_new_i64(s); - /* These extensions are only needed for type correctness. - We may be able to do better given target specific information. */ - tcg_gen_extu_i32_i64(s, tmp, high); - tcg_gen_extu_i32_i64(s, dest, low); - /* If deposit is available, use it. Otherwise use the extra - knowledge that we have of the zero-extensions above. */ - if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(32, 32)) { - tcg_gen_deposit_i64(s, dest, dest, tmp, 32, 32); - } else { - tcg_gen_shli_i64(s, tmp, tmp, 32); - tcg_gen_or_i64(s, dest, dest, tmp); - } - tcg_temp_free_i64(s, tmp); -#endif -} - -static inline void tcg_gen_concat32_i64(TCGContext *s, TCGv_i64 dest, TCGv_i64 low, - TCGv_i64 high) -{ - tcg_gen_deposit_i64(s, dest, low, high, 32, 32); + tcg_gen_deposit_i64(s, ret, lo, hi, 32, 32); } static inline void tcg_gen_trunc_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg) @@ -2179,299 +701,31 @@ static inline void tcg_gen_trunc_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 a tcg_gen_trunc_shr_i64_i32(s, ret, arg, 0); } -static inline void tcg_gen_extr_i64_i32(TCGContext *s, TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg) -{ - tcg_gen_trunc_shr_i64_i32(s, lo, arg, 0); - tcg_gen_trunc_shr_i64_i32(s, hi, arg, 32); -} +/* QEMU specific operations. */ -static inline void tcg_gen_extr32_i64(TCGContext *s, TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg) -{ - tcg_gen_ext32u_i64(s, lo, arg); - tcg_gen_shri_i64(s, hi, arg, 32); -} - -static inline void tcg_gen_movcond_i32(TCGContext *s, TCGCond cond, TCGv_i32 ret, - TCGv_i32 c1, TCGv_i32 c2, - TCGv_i32 v1, TCGv_i32 v2) -{ - if (TCG_TARGET_HAS_movcond_i32) { - tcg_gen_op6i_i32(s, INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond); - } else { - TCGv_i32 t0 = tcg_temp_new_i32(s); - TCGv_i32 t1 = tcg_temp_new_i32(s); - tcg_gen_setcond_i32(s, cond, t0, c1, c2); - tcg_gen_neg_i32(s, t0, t0); - tcg_gen_and_i32(s, t1, v1, t0); - tcg_gen_andc_i32(s, ret, v2, t0); - tcg_gen_or_i32(s, ret, ret, t1); - tcg_temp_free_i32(s, t0); - tcg_temp_free_i32(s, t1); - } -} - -static inline void tcg_gen_movcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 ret, - TCGv_i64 c1, TCGv_i64 c2, - TCGv_i64 v1, TCGv_i64 v2) -{ -#if TCG_TARGET_REG_BITS == 32 - TCGv_i32 t0 = tcg_temp_new_i32(s); - TCGv_i32 t1 = tcg_temp_new_i32(s); - tcg_gen_op6i_i32(s, INDEX_op_setcond2_i32, t0, - TCGV_LOW(c1), TCGV_HIGH(c1), - TCGV_LOW(c2), TCGV_HIGH(c2), cond); - - if (TCG_TARGET_HAS_movcond_i32) { - tcg_gen_movi_i32(s, t1, 0); - tcg_gen_movcond_i32(s, TCG_COND_NE, TCGV_LOW(ret), t0, t1, - TCGV_LOW(v1), TCGV_LOW(v2)); - tcg_gen_movcond_i32(s, TCG_COND_NE, TCGV_HIGH(ret), t0, t1, - TCGV_HIGH(v1), TCGV_HIGH(v2)); - } else { - tcg_gen_neg_i32(s, t0, t0); - - tcg_gen_and_i32(s, t1, TCGV_LOW(v1), t0); - tcg_gen_andc_i32(s, TCGV_LOW(ret), TCGV_LOW(v2), t0); - tcg_gen_or_i32(s, TCGV_LOW(ret), TCGV_LOW(ret), t1); - - tcg_gen_and_i32(s, t1, TCGV_HIGH(v1), t0); - tcg_gen_andc_i32(s, TCGV_HIGH(ret), TCGV_HIGH(v2), t0); - tcg_gen_or_i32(s, TCGV_HIGH(ret), TCGV_HIGH(ret), t1); - } - tcg_temp_free_i32(s, t0); - tcg_temp_free_i32(s, t1); -#else - if (TCG_TARGET_HAS_movcond_i64) { - tcg_gen_op6i_i64(s, INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(s); - TCGv_i64 t1 = tcg_temp_new_i64(s); - tcg_gen_setcond_i64(s, cond, t0, c1, c2); - tcg_gen_neg_i64(s, t0, t0); - tcg_gen_and_i64(s, t1, v1, t0); - tcg_gen_andc_i64(s, ret, v2, t0); - tcg_gen_or_i64(s, ret, ret, t1); - tcg_temp_free_i64(s, t0); - tcg_temp_free_i64(s, t1); - } -#endif -} - -static inline void tcg_gen_add2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, - TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) -{ - if (TCG_TARGET_HAS_add2_i32) { - tcg_gen_op6_i32(s, INDEX_op_add2_i32, rl, rh, al, ah, bl, bh); - /* Allow the optimizer room to replace add2 with two moves. */ - tcg_gen_op0(s, INDEX_op_nop); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(s); - TCGv_i64 t1 = tcg_temp_new_i64(s); - tcg_gen_concat_i32_i64(s, t0, al, ah); - tcg_gen_concat_i32_i64(s, t1, bl, bh); - tcg_gen_add_i64(s, t0, t0, t1); - tcg_gen_extr_i64_i32(s, rl, rh, t0); - tcg_temp_free_i64(s, t0); - tcg_temp_free_i64(s, t1); - } -} - -static inline void tcg_gen_sub2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, - TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) -{ - if (TCG_TARGET_HAS_sub2_i32) { - tcg_gen_op6_i32(s, INDEX_op_sub2_i32, rl, rh, al, ah, bl, bh); - /* Allow the optimizer room to replace sub2 with two moves. */ - tcg_gen_op0(s, INDEX_op_nop); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(s); - TCGv_i64 t1 = tcg_temp_new_i64(s); - tcg_gen_concat_i32_i64(s, t0, al, ah); - tcg_gen_concat_i32_i64(s, t1, bl, bh); - tcg_gen_sub_i64(s, t0, t0, t1); - tcg_gen_extr_i64_i32(s, rl, rh, t0); - tcg_temp_free_i64(s, t0); - tcg_temp_free_i64(s, t1); - } -} - -static inline void tcg_gen_mulu2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, - TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (TCG_TARGET_HAS_mulu2_i32) { - tcg_gen_op4_i32(s, INDEX_op_mulu2_i32, rl, rh, arg1, arg2); - /* Allow the optimizer room to replace mulu2 with two moves. */ - tcg_gen_op0(s, INDEX_op_nop); - } else if (TCG_TARGET_HAS_muluh_i32) { - TCGv_i32 t = tcg_temp_new_i32(s); - tcg_gen_op3_i32(s, INDEX_op_mul_i32, t, arg1, arg2); - tcg_gen_op3_i32(s, INDEX_op_muluh_i32, rh, arg1, arg2); - tcg_gen_mov_i32(s, rl, t); - tcg_temp_free_i32(s, t); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(s); - TCGv_i64 t1 = tcg_temp_new_i64(s); - tcg_gen_extu_i32_i64(s, t0, arg1); - tcg_gen_extu_i32_i64(s, t1, arg2); - tcg_gen_mul_i64(s, t0, t0, t1); - tcg_gen_extr_i64_i32(s, rl, rh, t0); - tcg_temp_free_i64(s, t0); - tcg_temp_free_i64(s, t1); - } -} - -static inline void tcg_gen_muls2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, - TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (TCG_TARGET_HAS_muls2_i32) { - tcg_gen_op4_i32(s, INDEX_op_muls2_i32, rl, rh, arg1, arg2); - /* Allow the optimizer room to replace muls2 with two moves. */ - tcg_gen_op0(s, INDEX_op_nop); - } else if (TCG_TARGET_HAS_mulsh_i32) { - TCGv_i32 t = tcg_temp_new_i32(s); - tcg_gen_op3_i32(s, INDEX_op_mul_i32, t, arg1, arg2); - tcg_gen_op3_i32(s, INDEX_op_mulsh_i32, rh, arg1, arg2); - tcg_gen_mov_i32(s, rl, t); - tcg_temp_free_i32(s, t); - } else if (TCG_TARGET_REG_BITS == 32) { - TCGv_i32 t0 = tcg_temp_new_i32(s); - TCGv_i32 t1 = tcg_temp_new_i32(s); - TCGv_i32 t2 = tcg_temp_new_i32(s); - TCGv_i32 t3 = tcg_temp_new_i32(s); - tcg_gen_mulu2_i32(s, t0, t1, arg1, arg2); - /* Adjust for negative inputs. */ - tcg_gen_sari_i32(s, t2, arg1, 31); - tcg_gen_sari_i32(s, t3, arg2, 31); - tcg_gen_and_i32(s, t2, t2, arg2); - tcg_gen_and_i32(s, t3, t3, arg1); - tcg_gen_sub_i32(s, rh, t1, t2); - tcg_gen_sub_i32(s, rh, rh, t3); - tcg_gen_mov_i32(s, rl, t0); - tcg_temp_free_i32(s, t0); - tcg_temp_free_i32(s, t1); - tcg_temp_free_i32(s, t2); - tcg_temp_free_i32(s, t3); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(s); - TCGv_i64 t1 = tcg_temp_new_i64(s); - tcg_gen_ext_i32_i64(s, t0, arg1); - tcg_gen_ext_i32_i64(s, t1, arg2); - tcg_gen_mul_i64(s, t0, t0, t1); - tcg_gen_extr_i64_i32(s, rl, rh, t0); - tcg_temp_free_i64(s, t0); - tcg_temp_free_i64(s, t1); - } -} - -static inline void tcg_gen_add2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) -{ - if (TCG_TARGET_HAS_add2_i64) { - tcg_gen_op6_i64(s, INDEX_op_add2_i64, rl, rh, al, ah, bl, bh); - /* Allow the optimizer room to replace add2 with two moves. */ - tcg_gen_op0(s, INDEX_op_nop); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(s); - TCGv_i64 t1 = tcg_temp_new_i64(s); - tcg_gen_add_i64(s, t0, al, bl); - tcg_gen_setcond_i64(s, TCG_COND_LTU, t1, t0, al); - tcg_gen_add_i64(s, rh, ah, bh); - tcg_gen_add_i64(s, rh, rh, t1); - tcg_gen_mov_i64(s, rl, t0); - tcg_temp_free_i64(s, t0); - tcg_temp_free_i64(s, t1); - } -} - -static inline void tcg_gen_sub2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) -{ - if (TCG_TARGET_HAS_sub2_i64) { - tcg_gen_op6_i64(s, INDEX_op_sub2_i64, rl, rh, al, ah, bl, bh); - /* Allow the optimizer room to replace sub2 with two moves. */ - tcg_gen_op0(s, INDEX_op_nop); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(s); - TCGv_i64 t1 = tcg_temp_new_i64(s); - tcg_gen_sub_i64(s, t0, al, bl); - tcg_gen_setcond_i64(s, TCG_COND_LTU, t1, al, bl); - tcg_gen_sub_i64(s, rh, ah, bh); - tcg_gen_sub_i64(s, rh, rh, t1); - tcg_gen_mov_i64(s, rl, t0); - tcg_temp_free_i64(s, t0); - tcg_temp_free_i64(s, t1); - } -} - -static inline void tcg_gen_mulu2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, - TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (TCG_TARGET_HAS_mulu2_i64) { - tcg_gen_op4_i64(s, INDEX_op_mulu2_i64, rl, rh, arg1, arg2); - /* Allow the optimizer room to replace mulu2 with two moves. */ - tcg_gen_op0(s, INDEX_op_nop); - } else if (TCG_TARGET_HAS_muluh_i64) { - TCGv_i64 t = tcg_temp_new_i64(s); - tcg_gen_op3_i64(s, INDEX_op_mul_i64, t, arg1, arg2); - tcg_gen_op3_i64(s, INDEX_op_muluh_i64, rh, arg1, arg2); - tcg_gen_mov_i64(s, rl, t); - tcg_temp_free_i64(s, t); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(s); - tcg_gen_mul_i64(s, t0, arg1, arg2); - gen_helper_muluh_i64(s, rh, arg1, arg2); - tcg_gen_mov_i64(s, rl, t0); - tcg_temp_free_i64(s, t0); - } -} - -static inline void tcg_gen_muls2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, - TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (TCG_TARGET_HAS_muls2_i64) { - tcg_gen_op4_i64(s, INDEX_op_muls2_i64, rl, rh, arg1, arg2); - /* Allow the optimizer room to replace muls2 with two moves. */ - tcg_gen_op0(s, INDEX_op_nop); - } else if (TCG_TARGET_HAS_mulsh_i64) { - TCGv_i64 t = tcg_temp_new_i64(s); - tcg_gen_op3_i64(s, INDEX_op_mul_i64, t, arg1, arg2); - tcg_gen_op3_i64(s, INDEX_op_mulsh_i64, rh, arg1, arg2); - tcg_gen_mov_i64(s, rl, t); - tcg_temp_free_i64(s, t); - } else if (TCG_TARGET_HAS_mulu2_i64 || TCG_TARGET_HAS_muluh_i64) { - TCGv_i64 t0 = tcg_temp_new_i64(s); - TCGv_i64 t1 = tcg_temp_new_i64(s); - TCGv_i64 t2 = tcg_temp_new_i64(s); - TCGv_i64 t3 = tcg_temp_new_i64(s); - tcg_gen_mulu2_i64(s, t0, t1, arg1, arg2); - /* Adjust for negative inputs. */ - tcg_gen_sari_i64(s, t2, arg1, 63); - tcg_gen_sari_i64(s, t3, arg2, 63); - tcg_gen_and_i64(s, t2, t2, arg2); - tcg_gen_and_i64(s, t3, t3, arg1); - tcg_gen_sub_i64(s, rh, t1, t2); - tcg_gen_sub_i64(s, rh, rh, t3); - tcg_gen_mov_i64(s, rl, t0); - tcg_temp_free_i64(s, t0); - tcg_temp_free_i64(s, t1); - tcg_temp_free_i64(s, t2); - tcg_temp_free_i64(s, t3); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(s); - tcg_gen_mul_i64(s, t0, arg1, arg2); - gen_helper_mulsh_i64(s, rh, arg1, arg2); - tcg_gen_mov_i64(s, rl, t0); - tcg_temp_free_i64(s, t0); - } -} - -/***************************************/ -/* QEMU specific operations. Their type depend on the QEMU CPU - type. */ #ifndef TARGET_LONG_BITS #error must include QEMU headers #endif +/* debug info: write the PC of the corresponding QEMU CPU instruction */ +static inline void tcg_gen_debug_insn_start(TCGContext *s, uint64_t pc) +{ + /* XXX: must really use a 32 bit size for TCGArg in all cases */ +#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS + tcg_gen_op2ii(s, INDEX_op_debug_insn_start, + (uint32_t)(pc), (uint32_t)(pc >> 32)); +#else + tcg_gen_op1i(s, INDEX_op_debug_insn_start, pc); +#endif +} + +static inline void tcg_gen_exit_tb(TCGContext *s, uintptr_t val) +{ + tcg_gen_op1i(s, INDEX_op_exit_tb, val); +} + +void tcg_gen_goto_tb(TCGContext *s, unsigned idx); + #if TARGET_LONG_BITS == 32 #define TCGv TCGv_i32 #define tcg_temp_new(s) tcg_temp_new_i32(s) @@ -2482,7 +736,6 @@ static inline void tcg_gen_muls2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x) #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) -#define tcg_add_param_tl tcg_add_param_i32 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 #else @@ -2495,41 +748,10 @@ static inline void tcg_gen_muls2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x) #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) -#define tcg_add_param_tl tcg_add_param_i64 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 #endif -/* debug info: write the PC of the corresponding QEMU CPU instruction */ -static inline void tcg_gen_debug_insn_start(TCGContext *s, uint64_t pc) -{ - /* XXX: must really use a 32 bit size for TCGArg in all cases */ -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - tcg_gen_op2ii(s, INDEX_op_debug_insn_start, - (uint32_t)(pc), (uint32_t)(pc >> 32)); -#else - tcg_gen_op1i(s, INDEX_op_debug_insn_start, pc); -#endif -} - -static inline void tcg_gen_exit_tb(TCGContext *s, uintptr_t val) -{ - tcg_gen_op1i(s, INDEX_op_exit_tb, val); -} - -static inline void tcg_gen_goto_tb(TCGContext *s, unsigned idx) -{ - /* We only support two chained exits. */ - tcg_debug_assert(idx <= 1); -#ifdef CONFIG_DEBUG_TCG - /* Verify that we havn't seen this numbered exit before. */ - tcg_debug_assert((s->goto_tb_issue_mask & (1 << idx)) == 0); - s->goto_tb_issue_mask |= 1 << idx; -#endif - tcg_gen_op1i(s, INDEX_op_goto_tb, idx); -} - - void tcg_gen_qemu_ld_i32(struct uc_struct *uc, TCGv_i32, TCGv, TCGArg, TCGMemOp); void tcg_gen_qemu_st_i32(struct uc_struct *uc, TCGv_i32, TCGv, TCGArg, TCGMemOp); void tcg_gen_qemu_ld_i64(struct uc_struct *uc, TCGv_i64, TCGv, TCGArg, TCGMemOp); @@ -2590,6 +812,8 @@ static inline void tcg_gen_qemu_st64(struct uc_struct *uc, TCGv_i64 arg, TCGv ad tcg_gen_qemu_st_i64(uc, arg, addr, mem_index, MO_TEQ); } +void check_exit_request(TCGContext *tcg_ctx); + #if TARGET_LONG_BITS == 64 #define tcg_gen_movi_tl tcg_gen_movi_i64 #define tcg_gen_mov_tl tcg_gen_mov_i64 diff --git a/qemu/tcg/tcg.c b/qemu/tcg/tcg.c index da78da1a..6235a70d 100644 --- a/qemu/tcg/tcg.c +++ b/qemu/tcg/tcg.c @@ -853,176 +853,6 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret, #endif /* TCG_TARGET_EXTEND_ARGS */ } -#if TCG_TARGET_REG_BITS == 32 -void tcg_gen_shifti_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, - int c, int right, int arith) -{ - if (c == 0) { - tcg_gen_mov_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1)); - tcg_gen_mov_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1)); - } else if (c >= 32) { - c -= 32; - if (right) { - if (arith) { - tcg_gen_sari_i32(s, TCGV_LOW(ret), TCGV_HIGH(arg1), c); - tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), 31); - } else { - tcg_gen_shri_i32(s, TCGV_LOW(ret), TCGV_HIGH(arg1), c); - tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); - } - } else { - tcg_gen_shli_i32(s, TCGV_HIGH(ret), TCGV_LOW(arg1), c); - tcg_gen_movi_i32(s, TCGV_LOW(ret), 0); - } - } else { - TCGv_i32 t0, t1; - - t0 = tcg_temp_new_i32(s); - t1 = tcg_temp_new_i32(s); - if (right) { - tcg_gen_shli_i32(s, t0, TCGV_HIGH(arg1), 32 - c); - if (arith) - tcg_gen_sari_i32(s, t1, TCGV_HIGH(arg1), c); - else - tcg_gen_shri_i32(s, t1, TCGV_HIGH(arg1), c); - tcg_gen_shri_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), c); - tcg_gen_or_i32(s, TCGV_LOW(ret), TCGV_LOW(ret), t0); - tcg_gen_mov_i32(s, TCGV_HIGH(ret), t1); - } else { - tcg_gen_shri_i32(s, t0, TCGV_LOW(arg1), 32 - c); - /* Note: ret can be the same as arg1, so we use t1 */ - tcg_gen_shli_i32(s, t1, TCGV_LOW(arg1), c); - tcg_gen_shli_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), c); - tcg_gen_or_i32(s, TCGV_HIGH(ret), TCGV_HIGH(ret), t0); - tcg_gen_mov_i32(s, TCGV_LOW(ret), t1); - } - tcg_temp_free_i32(s, t0); - tcg_temp_free_i32(s, t1); - } -} -#endif - -static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st) -{ - switch (op & MO_SIZE) { - case MO_8: - op &= ~MO_BSWAP; - break; - case MO_16: - break; - case MO_32: - if (!is64) { - op &= ~MO_SIGN; - } - break; - case MO_64: - if (!is64) { - tcg_abort(); - } - break; - } - if (st) { - op &= ~MO_SIGN; - } - return op; -} - -// Unicorn engine -// check if the last memory access was invalid -// if so, we jump to the block epilogue to quit immediately. -void check_exit_request(TCGContext *tcg_ctx) -{ - TCGv_i32 flag; - - flag = tcg_temp_new_i32(tcg_ctx); - tcg_gen_ld_i32(tcg_ctx, flag, tcg_ctx->cpu_env, - offsetof(CPUState, tcg_exit_req) - ENV_OFFSET); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, flag, 0, tcg_ctx->exitreq_label); - tcg_temp_free_i32(tcg_ctx, flag); -} - -void tcg_gen_qemu_ld_i32(struct uc_struct *uc, TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) -{ - TCGContext *tcg_ctx = uc->tcg_ctx; - - memop = tcg_canonicalize_memop(memop, 0, 0); - - *tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_ld_i32; - tcg_add_param_i32(tcg_ctx, val); - tcg_add_param_tl(tcg_ctx, addr); - *tcg_ctx->gen_opparam_ptr++ = memop; - *tcg_ctx->gen_opparam_ptr++ = idx; - - check_exit_request(tcg_ctx); -} - -void tcg_gen_qemu_st_i32(struct uc_struct *uc, TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) -{ - TCGContext *tcg_ctx = uc->tcg_ctx; - - memop = tcg_canonicalize_memop(memop, 0, 1); - - *tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_st_i32; - tcg_add_param_i32(tcg_ctx, val); - tcg_add_param_tl(tcg_ctx, addr); - *tcg_ctx->gen_opparam_ptr++ = memop; - *tcg_ctx->gen_opparam_ptr++ = idx; - - check_exit_request(tcg_ctx); -} - -void tcg_gen_qemu_ld_i64(struct uc_struct *uc, TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) -{ - TCGContext *tcg_ctx = uc->tcg_ctx; - - memop = tcg_canonicalize_memop(memop, 1, 0); - -#if TCG_TARGET_REG_BITS == 32 - if ((memop & MO_SIZE) < MO_64) { - tcg_gen_qemu_ld_i32(uc, TCGV_LOW(val), addr, idx, memop); - if (memop & MO_SIGN) { - tcg_gen_sari_i32(tcg_ctx, TCGV_HIGH(val), TCGV_LOW(val), 31); - } else { - tcg_gen_movi_i32(tcg_ctx, TCGV_HIGH(val), 0); - } - - check_exit_request(tcg_ctx); - return; - } -#endif - - *tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_ld_i64; - tcg_add_param_i64(tcg_ctx, val); - tcg_add_param_tl(tcg_ctx, addr); - *tcg_ctx->gen_opparam_ptr++ = memop; - *tcg_ctx->gen_opparam_ptr++ = idx; - - check_exit_request(tcg_ctx); -} - -void tcg_gen_qemu_st_i64(struct uc_struct *uc, TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) -{ - TCGContext *tcg_ctx = uc->tcg_ctx; - - memop = tcg_canonicalize_memop(memop, 1, 1); - -#if TCG_TARGET_REG_BITS == 32 - if ((memop & MO_SIZE) < MO_64) { - tcg_gen_qemu_st_i32(uc, TCGV_LOW(val), addr, idx, memop); - check_exit_request(tcg_ctx); - return; - } -#endif - - *tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_st_i64; - tcg_add_param_i64(tcg_ctx, val); - tcg_add_param_tl(tcg_ctx, addr); - *tcg_ctx->gen_opparam_ptr++ = memop; - *tcg_ctx->gen_opparam_ptr++ = idx; - - check_exit_request(tcg_ctx); -} - static void tcg_reg_alloc_start(TCGContext *s) { int i; diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h index 588b649a..c30072da 100644 --- a/qemu/tcg/tcg.h +++ b/qemu/tcg/tcg.h @@ -830,9 +830,6 @@ void tcg_add_target_add_op_defs(TCGContext *s, const TCGTargetOpDef *tdefs); void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret, int nargs, TCGArg *args); -void tcg_gen_shifti_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, - int c, int right, int arith); - TCGArg *tcg_optimize(TCGContext *s, uint16_t *tcg_opc_ptr, TCGArg *args, TCGOpDef *tcg_op_def); @@ -1025,8 +1022,6 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, # define helper_ret_stq_mmu helper_le_stq_mmu #endif -void check_exit_request(TCGContext *tcg_ctx); - #endif /* CONFIG_SOFTMMU */ #endif /* TCG_H */ diff --git a/qemu/x86_64.h b/qemu/x86_64.h index 9b05becf..2ceac41f 100644 --- a/qemu/x86_64.h +++ b/qemu/x86_64.h @@ -2690,11 +2690,13 @@ #define tcg_func_start tcg_func_start_x86_64 #define tcg_gen_abs_i32 tcg_gen_abs_i32_x86_64 #define tcg_gen_add2_i32 tcg_gen_add2_i32_x86_64 +#define tcg_gen_add2_i64 tcg_gen_add2_i64_x86_64 #define tcg_gen_add_i32 tcg_gen_add_i32_x86_64 #define tcg_gen_add_i64 tcg_gen_add_i64_x86_64 #define tcg_gen_addi_i32 tcg_gen_addi_i32_x86_64 #define tcg_gen_addi_i64 tcg_gen_addi_i64_x86_64 #define tcg_gen_andc_i32 tcg_gen_andc_i32_x86_64 +#define tcg_gen_andc_i64 tcg_gen_andc_i64_x86_64 #define tcg_gen_and_i32 tcg_gen_and_i32_x86_64 #define tcg_gen_and_i64 tcg_gen_and_i64_x86_64 #define tcg_gen_andi_i32 tcg_gen_andi_i32_x86_64 @@ -2703,8 +2705,12 @@ #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_x86_64 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_x86_64 #define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_x86_64 +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_x86_64 #define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_x86_64 +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_x86_64 #define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_x86_64 +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_x86_64 +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_x86_64 #define tcg_gen_callN tcg_gen_callN_x86_64 #define tcg_gen_code tcg_gen_code_x86_64 #define tcg_gen_code_common tcg_gen_code_common_x86_64 @@ -2712,16 +2718,36 @@ #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_x86_64 #define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_x86_64 #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_x86_64 +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_x86_64 +#define tcg_gen_discard_i64 tcg_gen_discard_i64_x86_64 +#define tcg_gen_div_i32 tcg_gen_div_i32_x86_64 +#define tcg_gen_div_i64 tcg_gen_div_i64_x86_64 +#define tcg_gen_divu_i32 tcg_gen_divu_i32_x86_64 +#define tcg_gen_divu_i64 tcg_gen_divu_i64_x86_64 +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_x86_64 +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_x86_64 #define tcg_gen_exit_tb tcg_gen_exit_tb_x86_64 #define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_x86_64 +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_x86_64 #define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_x86_64 +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_x86_64 #define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_x86_64 #define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_x86_64 #define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_x86_64 +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_x86_64 #define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_x86_64 +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_x86_64 #define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_x86_64 +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_x86_64 +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_x86_64 #define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_x86_64 #define tcg_gen_goto_tb tcg_gen_goto_tb_x86_64 +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_x86_64 +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_x86_64 +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_x86_64 +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_x86_64 +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_x86_64 +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_x86_64 #define tcg_gen_ld_i32 tcg_gen_ld_i32_x86_64 #define tcg_gen_ld_i64 tcg_gen_ld_i64_x86_64 #define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_x86_64 @@ -2733,12 +2759,28 @@ #define tcg_gen_movi_i32 tcg_gen_movi_i32_x86_64 #define tcg_gen_movi_i64 tcg_gen_movi_i64_x86_64 #define tcg_gen_mul_i32 tcg_gen_mul_i32_x86_64 +#define tcg_gen_mul_i64 tcg_gen_mul_i64_x86_64 +#define tcg_gen_muli_i32 tcg_gen_muli_i32_x86_64 +#define tcg_gen_muli_i64 tcg_gen_muli_i64_x86_64 #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_x86_64 +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_x86_64 #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_x86_64 +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_x86_64 +#define tcg_gen_nand_i32 tcg_gen_nand_i32_x86_64 +#define tcg_gen_nand_i64 tcg_gen_nand_i64_x86_64 #define tcg_gen_neg_i32 tcg_gen_neg_i32_x86_64 #define tcg_gen_neg_i64 tcg_gen_neg_i64_x86_64 +#define tcg_gen_nor_i32 tcg_gen_nor_i32_x86_64 +#define tcg_gen_nor_i64 tcg_gen_nor_i64_x86_64 #define tcg_gen_not_i32 tcg_gen_not_i32_x86_64 +#define tcg_gen_not_i64 tcg_gen_not_i64_x86_64 #define tcg_gen_op0 tcg_gen_op0_x86_64 +#define tcg_gen_op1 tcg_gen_op1_x86_64 +#define tcg_gen_op2 tcg_gen_op2_x86_64 +#define tcg_gen_op3 tcg_gen_op3_x86_64 +#define tcg_gen_op4 tcg_gen_op4_x86_64 +#define tcg_gen_op5 tcg_gen_op5_x86_64 +#define tcg_gen_op6 tcg_gen_op6_x86_64 #define tcg_gen_op1i tcg_gen_op1i_x86_64 #define tcg_gen_op2_i32 tcg_gen_op2_i32_x86_64 #define tcg_gen_op2_i64 tcg_gen_op2_i64_x86_64 @@ -2755,20 +2797,35 @@ #define tcg_gen_op6i_i32 tcg_gen_op6i_i32_x86_64 #define tcg_gen_op6i_i64 tcg_gen_op6i_i64_x86_64 #define tcg_gen_orc_i32 tcg_gen_orc_i32_x86_64 +#define tcg_gen_orc_i64 tcg_gen_orc_i64_x86_64 #define tcg_gen_or_i32 tcg_gen_or_i32_x86_64 #define tcg_gen_or_i64 tcg_gen_or_i64_x86_64 #define tcg_gen_ori_i32 tcg_gen_ori_i32_x86_64 +#define tcg_gen_ori_i64 tcg_gen_ori_i64_x86_64 #define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_x86_64 #define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_x86_64 #define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_x86_64 #define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_x86_64 +#define tcg_gen_rem_i32 tcg_gen_rem_i32_x86_64 +#define tcg_gen_rem_i64 tcg_gen_rem_i64_x86_64 +#define tcg_gen_remu_i32 tcg_gen_remu_i32_x86_64 +#define tcg_gen_remu_i64 tcg_gen_remu_i64_x86_64 #define tcg_gen_rotl_i32 tcg_gen_rotl_i32_x86_64 +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_x86_64 #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_x86_64 +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_x86_64 #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_x86_64 +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_x86_64 #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_x86_64 +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_x86_64 #define tcg_gen_sar_i32 tcg_gen_sar_i32_x86_64 +#define tcg_gen_sar_i64 tcg_gen_sar_i64_x86_64 #define tcg_gen_sari_i32 tcg_gen_sari_i32_x86_64 +#define tcg_gen_sari_i64 tcg_gen_sari_i64_x86_64 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_x86_64 +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_x86_64 +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_x86_64 +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_x86_64 #define tcg_gen_shl_i32 tcg_gen_shl_i32_x86_64 #define tcg_gen_shl_i64 tcg_gen_shl_i64_x86_64 #define tcg_gen_shli_i32 tcg_gen_shli_i32_x86_64 @@ -2780,14 +2837,20 @@ #define tcg_gen_shri_i64 tcg_gen_shri_i64_x86_64 #define tcg_gen_st_i32 tcg_gen_st_i32_x86_64 #define tcg_gen_st_i64 tcg_gen_st_i64_x86_64 +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_x86_64 +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_x86_64 #define tcg_gen_sub_i32 tcg_gen_sub_i32_x86_64 #define tcg_gen_sub_i64 tcg_gen_sub_i64_x86_64 +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_x86_64 +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_x86_64 #define tcg_gen_subi_i32 tcg_gen_subi_i32_x86_64 +#define tcg_gen_subi_i64 tcg_gen_subi_i64_x86_64 #define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_x86_64 #define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_x86_64 #define tcg_gen_xor_i32 tcg_gen_xor_i32_x86_64 #define tcg_gen_xor_i64 tcg_gen_xor_i64_x86_64 #define tcg_gen_xori_i32 tcg_gen_xori_i32_x86_64 +#define tcg_gen_xori_i64 tcg_gen_xori_i64_x86_64 #define tcg_get_arg_str_i32 tcg_get_arg_str_i32_x86_64 #define tcg_get_arg_str_i64 tcg_get_arg_str_i64_x86_64 #define tcg_get_arg_str_idx tcg_get_arg_str_idx_x86_64