diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 693a8810..ddf270a8 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -3564,6 +3564,12 @@ #define helper_sve_fcmuo_d helper_sve_fcmuo_d_aarch64 #define helper_sve_fcmuo_h helper_sve_fcmuo_h_aarch64 #define helper_sve_fcmuo_s helper_sve_fcmuo_s_aarch64 +#define helper_sve_fcvt_dh helper_sve_fcvt_dh_aarch64 +#define helper_sve_fcvt_ds helper_sve_fcvt_ds_aarch64 +#define helper_sve_fcvt_hd helper_sve_fcvt_hd_aarch64 +#define helper_sve_fcvt_hs helper_sve_fcvt_hs_aarch64 +#define helper_sve_fcvt_sd helper_sve_fcvt_sd_aarch64 +#define helper_sve_fcvt_sh helper_sve_fcvt_sh_aarch64 #define helper_sve_fdiv_d helper_sve_fdiv_d_aarch64 #define helper_sve_fdiv_h helper_sve_fdiv_h_aarch64 #define helper_sve_fdiv_s helper_sve_fdiv_s_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 4c78fa99..3d55e545 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -3564,6 +3564,12 @@ #define helper_sve_fcmuo_d helper_sve_fcmuo_d_aarch64eb #define helper_sve_fcmuo_h helper_sve_fcmuo_h_aarch64eb #define helper_sve_fcmuo_s helper_sve_fcmuo_s_aarch64eb +#define helper_sve_fcvt_dh helper_sve_fcvt_dh_aarch64eb +#define helper_sve_fcvt_ds helper_sve_fcvt_ds_aarch64eb +#define helper_sve_fcvt_hd helper_sve_fcvt_hd_aarch64eb +#define helper_sve_fcvt_hs helper_sve_fcvt_hs_aarch64eb +#define helper_sve_fcvt_sd helper_sve_fcvt_sd_aarch64eb +#define helper_sve_fcvt_sh helper_sve_fcvt_sh_aarch64eb #define helper_sve_fdiv_d helper_sve_fdiv_d_aarch64eb #define helper_sve_fdiv_h helper_sve_fdiv_h_aarch64eb #define helper_sve_fdiv_s helper_sve_fdiv_s_aarch64eb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 618265dc..bbfa60e6 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3585,6 +3585,12 @@ aarch64_symbols = ( 'helper_sve_fcmuo_d', 'helper_sve_fcmuo_h', 'helper_sve_fcmuo_s', + 'helper_sve_fcvt_dh', + 'helper_sve_fcvt_ds', + 'helper_sve_fcvt_hd', + 'helper_sve_fcvt_hs', + 'helper_sve_fcvt_sd', + 'helper_sve_fcvt_sh', 'helper_sve_fdiv_d', 'helper_sve_fdiv_h', 'helper_sve_fdiv_s', diff --git a/qemu/target/arm/helper-sve.h b/qemu/target/arm/helper-sve.h index aca137fc..4c379dbb 100644 --- a/qemu/target/arm/helper-sve.h +++ b/qemu/target/arm/helper-sve.h @@ -942,6 +942,19 @@ DEF_HELPER_FLAGS_6(sve_fmins_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmins_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64, ptr, i32) +DEF_HELPER_FLAGS_5(sve_fcvt_sh, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_fcvt_dh, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_fcvt_hs, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_fcvt_ds, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_fcvt_hd, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_fcvt_sd, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_scvt_hh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve_scvt_sh, TCG_CALL_NO_RWG, diff --git a/qemu/target/arm/sve.decode b/qemu/target/arm/sve.decode index b124f875..4b05af54 100644 --- a/qemu/target/arm/sve.decode +++ b/qemu/target/arm/sve.decode @@ -821,6 +821,14 @@ FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra ### SVE FP Unary Operations Predicated Group +# SVE floating-point convert precision +FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 +FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 +FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0 +FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0 +FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 +FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 + # SVE integer convert to floating-point SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0 SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 diff --git a/qemu/target/arm/sve_helper.c b/qemu/target/arm/sve_helper.c index 3eb442be..970c5b40 100644 --- a/qemu/target/arm/sve_helper.c +++ b/qemu/target/arm/sve_helper.c @@ -4000,6 +4000,61 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \ } while (i != 0); \ } +/* SVE fp16 conversions always use IEEE mode. Like AdvSIMD, they ignore + * FZ16. When converting from fp16, this affects flushing input denormals; + * when converting to fp16, this affects flushing output denormals. + */ +static inline float32 sve_f16_to_f32(float16 f, float_status *fpst) +{ + flag save = get_flush_inputs_to_zero(fpst); + float32 ret; + + set_flush_inputs_to_zero(false, fpst); + ret = float16_to_float32(f, true, fpst); + set_flush_inputs_to_zero(save, fpst); + return ret; +} + +static inline float64 sve_f16_to_f64(float16 f, float_status *fpst) +{ + flag save = get_flush_inputs_to_zero(fpst); + float64 ret; + + set_flush_inputs_to_zero(false, fpst); + ret = float16_to_float64(f, true, fpst); + set_flush_inputs_to_zero(save, fpst); + return ret; +} + +static inline float16 sve_f32_to_f16(float32 f, float_status *fpst) +{ + flag save = get_flush_to_zero(fpst); + float16 ret; + + set_flush_to_zero(false, fpst); + ret = float32_to_float16(f, true, fpst); + set_flush_to_zero(save, fpst); + return ret; +} + +static inline float16 sve_f64_to_f16(float64 f, float_status *fpst) +{ + flag save = get_flush_to_zero(fpst); + float16 ret; + + set_flush_to_zero(false, fpst); + ret = float64_to_float16(f, true, fpst); + set_flush_to_zero(save, fpst); + return ret; +} + +DO_ZPZ_FP(sve_fcvt_sh, uint32_t, H1_4, sve_f32_to_f16) +DO_ZPZ_FP(sve_fcvt_hs, uint32_t, H1_4, sve_f16_to_f32) +DO_ZPZ_FP(sve_fcvt_dh, uint64_t, , sve_f64_to_f16) +DO_ZPZ_FP(sve_fcvt_hd, uint64_t, , sve_f16_to_f64) +DO_ZPZ_FP(sve_fcvt_ds, uint64_t, , float64_to_float32) +DO_ZPZ_FP(sve_fcvt_sd, uint64_t, , float32_to_float64) + DO_ZPZ_FP(sve_scvt_hh, uint16_t, H1_2, int16_to_float16) DO_ZPZ_FP(sve_scvt_sh, uint32_t, H1_4, int32_to_float16) DO_ZPZ_FP(sve_scvt_ss, uint32_t, H1_4, int32_to_float32) diff --git a/qemu/target/arm/translate-sve.c b/qemu/target/arm/translate-sve.c index 393f9688..3facfca3 100644 --- a/qemu/target/arm/translate-sve.c +++ b/qemu/target/arm/translate-sve.c @@ -4097,6 +4097,36 @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg, return true; } +static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_sh); +} + +static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hs); +} + +static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_dh); +} + +static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hd); +} + +static bool trans_FCVT_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_ds); +} + +static bool trans_FCVT_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sd); +} + static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_hh);