From 52f2d5cbee36c9321191470a2bb3d1f42d5a0288 Mon Sep 17 00:00:00 2001
From: Richard Henderson <richard.henderson@linaro.org>
Date: Mon, 8 Mar 2021 12:24:18 -0500
Subject: [PATCH] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s

Do not depend on the RVD extension, take input and output via
TCGv_i64 instead of fpu regno. Move the function to translate.c
so that it can be used in multiple trans_*.inc.c files.

Backports d36a86d01e67792c51dd2a82360cda012bde9442
---
 qemu/target/riscv/insn_trans/trans_rvf.inc.c | 18 +-----------------
 qemu/target/riscv/translate.c                | 12 ++++++++++++
 2 files changed, 13 insertions(+), 17 deletions(-)

diff --git a/qemu/target/riscv/insn_trans/trans_rvf.inc.c b/qemu/target/riscv/insn_trans/trans_rvf.inc.c
index 0bc8dee5..d8da046e 100644
--- a/qemu/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/qemu/target/riscv/insn_trans/trans_rvf.inc.c
@@ -23,22 +23,6 @@
         return false;                       \
 } while (0)
 
-/*
- * RISC-V requires NaN-boxing of narrower width floating
- * point values.  This applies when a 32-bit value is
- * assigned to a 64-bit FP register.  Thus this does not
- * apply when the RVD extension is not present.
- */
-static void gen_nanbox_fpr(DisasContext *ctx, int regno)
-{
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
-
-    if (has_ext(ctx, RVD)) {
-        tcg_gen_ori_i64(tcg_ctx, tcg_ctx->cpu_fpr_risc[regno], tcg_ctx->cpu_fpr_risc[regno],
-                        MAKE_64BIT_MASK(32, 32));
-    }
-}
-
 static bool trans_flw(DisasContext *ctx, arg_flw *a)
 {
     TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
@@ -49,7 +33,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
     tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
 
     tcg_gen_qemu_ld_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rd], t0, ctx->mem_idx, MO_TEUL);
-    gen_nanbox_fpr(ctx, a->rd);
+    gen_nanbox_s(ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_fpr_risc[a->rd]);
 
     tcg_temp_free(tcg_ctx, t0);
     mark_fs_dirty(ctx);
diff --git a/qemu/target/riscv/translate.c b/qemu/target/riscv/translate.c
index 0593b801..c15d43cd 100644
--- a/qemu/target/riscv/translate.c
+++ b/qemu/target/riscv/translate.c
@@ -93,6 +93,18 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
     return ctx->misa & ext;
 }
 
+/*
+ * RISC-V requires NaN-boxing of narrower width floating point values.
+ * This applies when a 32-bit value is assigned to a 64-bit FP register.
+ * For consistency and simplicity, we nanbox results even when the RVD
+ * extension is not present.
+ */
+static void gen_nanbox_s(DisasContext *s, TCGv_i64 out, TCGv_i64 in)
+{
+    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    tcg_gen_ori_i64(tcg_ctx, out, in, MAKE_64BIT_MASK(32, 32));
+}
+
 static void generate_exception(DisasContext *ctx, int excp)
 {
     TCGContext *tcg_ctx = ctx->uc->tcg_ctx;