From 54a33d1db3288646d5f9fa6616acee2a5bc41252 Mon Sep 17 00:00:00 2001 From: Mateja Marjanovic Date: Tue, 28 May 2019 19:35:52 -0400 Subject: [PATCH] target/mips: Refactor and fix COPY_S. instructions The old version of the helper for the COPY_S. MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Backports commit 631c467461496dcf6d6a3e4c3d27a1433e96868e from qemu --- qemu/header_gen.py | 5 ++- qemu/mips.h | 5 ++- qemu/mips64.h | 5 ++- qemu/mips64el.h | 5 ++- qemu/mipsel.h | 5 ++- qemu/target/mips/helper.h | 7 +++- qemu/target/mips/msa_helper.c | 66 ++++++++++++++++++++++++----------- qemu/target/mips/translate.c | 19 +++++++++- 8 files changed, 89 insertions(+), 28 deletions(-) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 1bb7bc00..b08fbcc5 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -4972,7 +4972,10 @@ mips_symbols = ( 'helper_msa_clt_u_df', 'helper_msa_clti_s_df', 'helper_msa_clti_u_df', - 'helper_msa_copy_s_df', + 'helper_msa_copy_s_b', + 'helper_msa_copy_s_d', + 'helper_msa_copy_s_h', + 'helper_msa_copy_s_w', 'helper_msa_copy_u_df', 'helper_msa_ctcmsa', 'helper_msa_div_s_df', diff --git a/qemu/mips.h b/qemu/mips.h index 81315fc4..25143a40 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -3860,7 +3860,10 @@ #define helper_msa_clt_u_df helper_msa_clt_u_df_mips #define helper_msa_clti_s_df helper_msa_clti_s_df_mips #define helper_msa_clti_u_df helper_msa_clti_u_df_mips -#define helper_msa_copy_s_df helper_msa_copy_s_df_mips +#define helper_msa_copy_s_b helper_msa_copy_s_b_mips +#define helper_msa_copy_s_d helper_msa_copy_s_d_mips +#define helper_msa_copy_s_h helper_msa_copy_s_h_mips +#define helper_msa_copy_s_w helper_msa_copy_s_w_mips #define helper_msa_copy_u_df helper_msa_copy_u_df_mips #define helper_msa_ctcmsa helper_msa_ctcmsa_mips #define helper_msa_div_s_df helper_msa_div_s_df_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index df955412..0cbf852e 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -3860,7 +3860,10 @@ #define helper_msa_clt_u_df helper_msa_clt_u_df_mips64 #define helper_msa_clti_s_df helper_msa_clti_s_df_mips64 #define helper_msa_clti_u_df helper_msa_clti_u_df_mips64 -#define helper_msa_copy_s_df helper_msa_copy_s_df_mips64 +#define helper_msa_copy_s_b helper_msa_copy_s_b_mips64 +#define helper_msa_copy_s_d helper_msa_copy_s_d_mips64 +#define helper_msa_copy_s_h helper_msa_copy_s_h_mips64 +#define helper_msa_copy_s_w helper_msa_copy_s_w_mips64 #define helper_msa_copy_u_df helper_msa_copy_u_df_mips64 #define helper_msa_ctcmsa helper_msa_ctcmsa_mips64 #define helper_msa_div_s_df helper_msa_div_s_df_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index 268d142b..77f9be29 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -3860,7 +3860,10 @@ #define helper_msa_clt_u_df helper_msa_clt_u_df_mips64el #define helper_msa_clti_s_df helper_msa_clti_s_df_mips64el #define helper_msa_clti_u_df helper_msa_clti_u_df_mips64el -#define helper_msa_copy_s_df helper_msa_copy_s_df_mips64el +#define helper_msa_copy_s_b helper_msa_copy_s_b_mips64el +#define helper_msa_copy_s_d helper_msa_copy_s_d_mips64el +#define helper_msa_copy_s_h helper_msa_copy_s_h_mips64el +#define helper_msa_copy_s_w helper_msa_copy_s_w_mips64el #define helper_msa_copy_u_df helper_msa_copy_u_df_mips64el #define helper_msa_ctcmsa helper_msa_ctcmsa_mips64el #define helper_msa_div_s_df helper_msa_div_s_df_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index c0a1f54d..18713b00 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -3860,7 +3860,10 @@ #define helper_msa_clt_u_df helper_msa_clt_u_df_mipsel #define helper_msa_clti_s_df helper_msa_clti_s_df_mipsel #define helper_msa_clti_u_df helper_msa_clti_u_df_mipsel -#define helper_msa_copy_s_df helper_msa_copy_s_df_mipsel +#define helper_msa_copy_s_b helper_msa_copy_s_b_mipsel +#define helper_msa_copy_s_d helper_msa_copy_s_d_mipsel +#define helper_msa_copy_s_h helper_msa_copy_s_h_mipsel +#define helper_msa_copy_s_w helper_msa_copy_s_w_mipsel #define helper_msa_copy_u_df helper_msa_copy_u_df_mipsel #define helper_msa_ctcmsa helper_msa_ctcmsa_mipsel #define helper_msa_div_s_df helper_msa_div_s_df_mipsel diff --git a/qemu/target/mips/helper.h b/qemu/target/mips/helper.h index 0da6f9a0..7208ef94 100644 --- a/qemu/target/mips/helper.h +++ b/qemu/target/mips/helper.h @@ -876,7 +876,7 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_copy_s_df, void, env, i32, i32, i32, i32) + DEF_HELPER_5(msa_copy_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) @@ -938,6 +938,11 @@ DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_nloc_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_nlzc_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) + DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32) diff --git a/qemu/target/mips/msa_helper.c b/qemu/target/mips/msa_helper.c index a9f0d368..0fa59892 100644 --- a/qemu/target/mips/msa_helper.c +++ b/qemu/target/mips/msa_helper.c @@ -1249,29 +1249,53 @@ void helper_msa_splati_df(CPUMIPSState *env, uint32_t df, uint32_t wd, msa_splat_df(df, pwd, pws, n); } -void helper_msa_copy_s_df(CPUMIPSState *env, uint32_t df, uint32_t rd, - uint32_t ws, uint32_t n) +void helper_msa_copy_s_b(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) { - n %= DF_ELEMENTS(df); - - switch (df) { - case DF_BYTE: - env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n]; - break; - case DF_HALF: - env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n]; - break; - case DF_WORD: - env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n]; - break; -#ifdef TARGET_MIPS64 - case DF_DOUBLE: - env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n]; - break; -#endif - default: - assert(0); + n %= 16; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 8) { + n = 8 - n - 1; + } else { + n = 24 - n - 1; } +#endif + env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n]; +} + +void helper_msa_copy_s_h(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %= 8; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 4) { + n = 4 - n - 1; + } else { + n = 12 - n - 1; + } +#endif + env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n]; +} + +void helper_msa_copy_s_w(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %= 4; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 2) { + n = 2 - n - 1; + } else { + n = 6 - n - 1; + } +#endif + env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n]; +} + +void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %= 2; + env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n]; } void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd, diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index 241e95d6..ca725f19 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -28462,7 +28462,24 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df, switch (MASK_MSA_ELM(ctx->opcode)) { case OPC_COPY_S_df: if (likely(wd != 0)) { - gen_helper_msa_copy_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn); + switch (df) { + case DF_BYTE: + gen_helper_msa_copy_s_b(tcg_ctx, tcg_ctx->cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_copy_s_h(tcg_ctx, tcg_ctx->cpu_env, twd, tws, tn); + break; + case DF_WORD: + gen_helper_msa_copy_s_w(tcg_ctx, tcg_ctx->cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_DOUBLE: + gen_helper_msa_copy_s_d(tcg_ctx, tcg_ctx->cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } } break; case OPC_COPY_U_df: