From 565626ca63fa50fdd16a027f1f327a1142a97ac9 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 2 Mar 2018 20:00:56 -0500 Subject: [PATCH] armv7m: Raise correct kind of UsageFault for attempts to execute ARM code M profile doesn't implement ARM, and the architecturally required behaviour for attempts to execute with the Thumb bit clear is to generate a UsageFault with the CFSR INVSTATE bit set. We were incorrectly implementing this as generating an UNDEFINSTR UsageFault; fix this. Backports commit e13886e3a790b52f0b2e93cb5e84fdc2ada5471a from qemu --- qemu/target/arm/helper.c | 4 ++++ qemu/target/arm/translate.c | 8 ++++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index ee42b070..3e5052f5 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -5598,6 +5598,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) //armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK; break; + case EXCP_INVSTATE: + //armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); + env->v7m.cfsr |= R_V7M_CFSR_INVSTATE_MASK; + break; case EXCP_SWI: /* The PC already points to the next instruction. */ //armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c index 75e38f4e..1cb7f368 100644 --- a/qemu/target/arm/translate.c +++ b/qemu/target/arm/translate.c @@ -8218,9 +8218,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq TCGv_i32 addr; TCGv_i64 tmp64; - /* M variants do not implement ARM mode. */ + /* M variants do not implement ARM mode; this must raise the INVSTATE + * UsageFault exception. + */ if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; + gen_exception_insn(s, 4, EXCP_INVSTATE, syn_uncategorized(), + default_exception_el(s)); + return; } // Unicorn: trace this instruction on request