diff --git a/qemu/header_gen.py b/qemu/header_gen.py index c44b56e5..de51120c 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -6362,6 +6362,30 @@ riscv_symbols = ( 'helper_vmsbc_vxm_h', 'helper_vmsbc_vxm_w', 'helper_vmsbc_vxm_d', + 'helper_vand_vv_b', + 'helper_vand_vv_h', + 'helper_vand_vv_w', + 'helper_vand_vv_d', + 'helper_vor_vv_b', + 'helper_vor_vv_h', + 'helper_vor_vv_w', + 'helper_vor_vv_d', + 'helper_vxor_vv_b', + 'helper_vxor_vv_h', + 'helper_vxor_vv_w', + 'helper_vxor_vv_d', + 'helper_vand_vx_b', + 'helper_vand_vx_h', + 'helper_vand_vx_w', + 'helper_vand_vx_d', + 'helper_vor_vx_b', + 'helper_vor_vx_h', + 'helper_vor_vx_w', + 'helper_vor_vx_d', + 'helper_vxor_vx_b', + 'helper_vxor_vx_h', + 'helper_vxor_vx_w', + 'helper_vxor_vx_d', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index c0c09571..7f5201de 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -3816,6 +3816,30 @@ #define helper_vmsbc_vxm_h helper_vmsbc_vxm_h_riscv32 #define helper_vmsbc_vxm_w helper_vmsbc_vxm_w_riscv32 #define helper_vmsbc_vxm_d helper_vmsbc_vxm_d_riscv32 +#define helper_vand_vv_b helper_vand_vv_b_riscv32 +#define helper_vand_vv_h helper_vand_vv_h_riscv32 +#define helper_vand_vv_w helper_vand_vv_w_riscv32 +#define helper_vand_vv_d helper_vand_vv_d_riscv32 +#define helper_vor_vv_b helper_vor_vv_b_riscv32 +#define helper_vor_vv_h helper_vor_vv_h_riscv32 +#define helper_vor_vv_w helper_vor_vv_w_riscv32 +#define helper_vor_vv_d helper_vor_vv_d_riscv32 +#define helper_vxor_vv_b helper_vxor_vv_b_riscv32 +#define helper_vxor_vv_h helper_vxor_vv_h_riscv32 +#define helper_vxor_vv_w helper_vxor_vv_w_riscv32 +#define helper_vxor_vv_d helper_vxor_vv_d_riscv32 +#define helper_vand_vx_b helper_vand_vx_b_riscv32 +#define helper_vand_vx_h helper_vand_vx_h_riscv32 +#define helper_vand_vx_w helper_vand_vx_w_riscv32 +#define helper_vand_vx_d helper_vand_vx_d_riscv32 +#define helper_vor_vx_b helper_vor_vx_b_riscv32 +#define helper_vor_vx_h helper_vor_vx_h_riscv32 +#define helper_vor_vx_w helper_vor_vx_w_riscv32 +#define helper_vor_vx_d helper_vor_vx_d_riscv32 +#define helper_vxor_vx_b helper_vxor_vx_b_riscv32 +#define helper_vxor_vx_h helper_vxor_vx_h_riscv32 +#define helper_vxor_vx_w helper_vxor_vx_w_riscv32 +#define helper_vxor_vx_d helper_vxor_vx_d_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 226efea7..e48f9e05 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -3816,6 +3816,30 @@ #define helper_vmsbc_vxm_h helper_vmsbc_vxm_h_riscv64 #define helper_vmsbc_vxm_w helper_vmsbc_vxm_w_riscv64 #define helper_vmsbc_vxm_d helper_vmsbc_vxm_d_riscv64 +#define helper_vand_vv_b helper_vand_vv_b_riscv64 +#define helper_vand_vv_h helper_vand_vv_h_riscv64 +#define helper_vand_vv_w helper_vand_vv_w_riscv64 +#define helper_vand_vv_d helper_vand_vv_d_riscv64 +#define helper_vor_vv_b helper_vor_vv_b_riscv64 +#define helper_vor_vv_h helper_vor_vv_h_riscv64 +#define helper_vor_vv_w helper_vor_vv_w_riscv64 +#define helper_vor_vv_d helper_vor_vv_d_riscv64 +#define helper_vxor_vv_b helper_vxor_vv_b_riscv64 +#define helper_vxor_vv_h helper_vxor_vv_h_riscv64 +#define helper_vxor_vv_w helper_vxor_vv_w_riscv64 +#define helper_vxor_vv_d helper_vxor_vv_d_riscv64 +#define helper_vand_vx_b helper_vand_vx_b_riscv64 +#define helper_vand_vx_h helper_vand_vx_h_riscv64 +#define helper_vand_vx_w helper_vand_vx_w_riscv64 +#define helper_vand_vx_d helper_vand_vx_d_riscv64 +#define helper_vor_vx_b helper_vor_vx_b_riscv64 +#define helper_vor_vx_h helper_vor_vx_h_riscv64 +#define helper_vor_vx_w helper_vor_vx_w_riscv64 +#define helper_vor_vx_d helper_vor_vx_d_riscv64 +#define helper_vxor_vx_b helper_vxor_vx_b_riscv64 +#define helper_vxor_vx_h helper_vxor_vx_h_riscv64 +#define helper_vxor_vx_w helper_vxor_vx_w_riscv64 +#define helper_vxor_vx_d helper_vxor_vx_d_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index e8e4ab4b..1e2a0957 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -385,3 +385,28 @@ DEF_HELPER_6(vmsbc_vxm_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmsbc_vxm_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmsbc_vxm_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmsbc_vxm_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vand_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vand_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vand_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vand_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vor_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vor_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vor_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vor_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vxor_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vxor_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vxor_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vxor_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vand_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vand_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vand_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vand_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vor_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vor_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vor_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vor_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vxor_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vxor_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vxor_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vxor_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index be63e900..34d05a59 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -313,6 +313,15 @@ vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1 vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1 vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1 vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1 +vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm +vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm +vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm +vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm +vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm +vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm +vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm +vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm +vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index 57c262a9..2e6f57a1 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -1382,3 +1382,14 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ GEN_OPIVI_TRANS(vadc_vim, 0, vadc_vxm, opivx_vadc_check) GEN_OPIVI_TRANS(vmadc_vim, 0, vmadc_vxm, opivx_vmadc_check) + +/* Vector Bitwise Logical Instructions */ +GEN_OPIVV_GVEC_TRANS(vand_vv, and) +GEN_OPIVV_GVEC_TRANS(vor_vv, or) +GEN_OPIVV_GVEC_TRANS(vxor_vv, xor) +GEN_OPIVX_GVEC_TRANS(vand_vx, ands) +GEN_OPIVX_GVEC_TRANS(vor_vx, ors) +GEN_OPIVX_GVEC_TRANS(vxor_vx, xors) +GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi) +GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori) +GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori) diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index 828d4505..41841d85 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -1266,3 +1266,54 @@ GEN_VEXT_VMADC_VXM(vmsbc_vxm_b, uint8_t, H1, DO_MSBC) GEN_VEXT_VMADC_VXM(vmsbc_vxm_h, uint16_t, H2, DO_MSBC) GEN_VEXT_VMADC_VXM(vmsbc_vxm_w, uint32_t, H4, DO_MSBC) GEN_VEXT_VMADC_VXM(vmsbc_vxm_d, uint64_t, H8, DO_MSBC) + +/* Vector Bitwise Logical Instructions */ +RVVCALL(OPIVV2, vand_vv_b, OP_SSS_B, H1, H1, H1, DO_AND) +RVVCALL(OPIVV2, vand_vv_h, OP_SSS_H, H2, H2, H2, DO_AND) +RVVCALL(OPIVV2, vand_vv_w, OP_SSS_W, H4, H4, H4, DO_AND) +RVVCALL(OPIVV2, vand_vv_d, OP_SSS_D, H8, H8, H8, DO_AND) +RVVCALL(OPIVV2, vor_vv_b, OP_SSS_B, H1, H1, H1, DO_OR) +RVVCALL(OPIVV2, vor_vv_h, OP_SSS_H, H2, H2, H2, DO_OR) +RVVCALL(OPIVV2, vor_vv_w, OP_SSS_W, H4, H4, H4, DO_OR) +RVVCALL(OPIVV2, vor_vv_d, OP_SSS_D, H8, H8, H8, DO_OR) +RVVCALL(OPIVV2, vxor_vv_b, OP_SSS_B, H1, H1, H1, DO_XOR) +RVVCALL(OPIVV2, vxor_vv_h, OP_SSS_H, H2, H2, H2, DO_XOR) +RVVCALL(OPIVV2, vxor_vv_w, OP_SSS_W, H4, H4, H4, DO_XOR) +RVVCALL(OPIVV2, vxor_vv_d, OP_SSS_D, H8, H8, H8, DO_XOR) +GEN_VEXT_VV(vand_vv_b, 1, 1, clearb) +GEN_VEXT_VV(vand_vv_h, 2, 2, clearh) +GEN_VEXT_VV(vand_vv_w, 4, 4, clearl) +GEN_VEXT_VV(vand_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vor_vv_b, 1, 1, clearb) +GEN_VEXT_VV(vor_vv_h, 2, 2, clearh) +GEN_VEXT_VV(vor_vv_w, 4, 4, clearl) +GEN_VEXT_VV(vor_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vxor_vv_b, 1, 1, clearb) +GEN_VEXT_VV(vxor_vv_h, 2, 2, clearh) +GEN_VEXT_VV(vxor_vv_w, 4, 4, clearl) +GEN_VEXT_VV(vxor_vv_d, 8, 8, clearq) + +RVVCALL(OPIVX2, vand_vx_b, OP_SSS_B, H1, H1, DO_AND) +RVVCALL(OPIVX2, vand_vx_h, OP_SSS_H, H2, H2, DO_AND) +RVVCALL(OPIVX2, vand_vx_w, OP_SSS_W, H4, H4, DO_AND) +RVVCALL(OPIVX2, vand_vx_d, OP_SSS_D, H8, H8, DO_AND) +RVVCALL(OPIVX2, vor_vx_b, OP_SSS_B, H1, H1, DO_OR) +RVVCALL(OPIVX2, vor_vx_h, OP_SSS_H, H2, H2, DO_OR) +RVVCALL(OPIVX2, vor_vx_w, OP_SSS_W, H4, H4, DO_OR) +RVVCALL(OPIVX2, vor_vx_d, OP_SSS_D, H8, H8, DO_OR) +RVVCALL(OPIVX2, vxor_vx_b, OP_SSS_B, H1, H1, DO_XOR) +RVVCALL(OPIVX2, vxor_vx_h, OP_SSS_H, H2, H2, DO_XOR) +RVVCALL(OPIVX2, vxor_vx_w, OP_SSS_W, H4, H4, DO_XOR) +RVVCALL(OPIVX2, vxor_vx_d, OP_SSS_D, H8, H8, DO_XOR) +GEN_VEXT_VX(vand_vx_b, 1, 1, clearb) +GEN_VEXT_VX(vand_vx_h, 2, 2, clearh) +GEN_VEXT_VX(vand_vx_w, 4, 4, clearl) +GEN_VEXT_VX(vand_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vor_vx_b, 1, 1, clearb) +GEN_VEXT_VX(vor_vx_h, 2, 2, clearh) +GEN_VEXT_VX(vor_vx_w, 4, 4, clearl) +GEN_VEXT_VX(vor_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vxor_vx_b, 1, 1, clearb) +GEN_VEXT_VX(vxor_vx_h, 2, 2, clearh) +GEN_VEXT_VX(vxor_vx_w, 4, 4, clearl) +GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq)