diff --git a/qemu/target-arm/translate.c b/qemu/target-arm/translate.c
index 8fbe8c98..ff79fc4f 100644
--- a/qemu/target-arm/translate.c
+++ b/qemu/target-arm/translate.c
@@ -11691,48 +11691,45 @@ tb_end:
        instruction was a conditional branch or trap, and the PC has
        already been written.  */
     if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
-        /* Make sure the pc is updated, and raise a debug exception.  */
+        /* Unconditional and "condition passed" instruction codepath. */
+        gen_set_condexec(dc);
+        switch (dc->is_jmp) {
+        case DISAS_SWI:
+            gen_ss_advance(dc);
+            gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
+                          default_exception_el(dc));
+            break;
+        case DISAS_HVC:
+            gen_ss_advance(dc);
+            gen_exception(dc, EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
+            break;
+        case DISAS_SMC:
+            gen_ss_advance(dc);
+            gen_exception(dc, EXCP_SMC, syn_aa32_smc(), 3);
+            break;
+        case DISAS_NEXT:
+        case DISAS_UPDATE:
+            gen_set_pc_im(dc, dc->pc);
+            /* fall through */
+        default:
+            if (dc->ss_active) {
+                gen_step_complete_exception(dc);
+            } else {
+                /* FIXME: Single stepping a WFI insn will not halt
+                   the CPU.  */
+                gen_exception_internal(dc, EXCP_DEBUG);
+            }
+        }
         if (dc->condjmp) {
+            /* "Condition failed" instruction codepath. */
+            gen_set_label(tcg_ctx, dc->condlabel);
             gen_set_condexec(dc);
-            if (dc->is_jmp == DISAS_SWI) {
-                gen_ss_advance(dc);
-                gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
-                              default_exception_el(dc));
-            } else if (dc->is_jmp == DISAS_HVC) {
-                gen_ss_advance(dc);
-                gen_exception(dc, EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
-            } else if (dc->is_jmp == DISAS_SMC) {
-                gen_ss_advance(dc);
-                gen_exception(dc, EXCP_SMC, syn_aa32_smc(), 3);
-            } else if (dc->ss_active) {
+            gen_set_pc_im(dc, dc->pc);
+            if (dc->ss_active) {
                 gen_step_complete_exception(dc);
             } else {
                 gen_exception_internal(dc, EXCP_DEBUG);
             }
-            gen_set_label(tcg_ctx, dc->condlabel);
-        }
-        if (dc->condjmp || dc->is_jmp == DISAS_NEXT ||
-            dc->is_jmp == DISAS_UPDATE) {
-            gen_set_pc_im(dc, dc->pc);
-            dc->condjmp = 0;
-        }
-        gen_set_condexec(dc);
-        if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
-            gen_ss_advance(dc);
-            gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
-                          default_exception_el(dc));
-        } else if (dc->is_jmp == DISAS_HVC && !dc->condjmp) {
-            gen_ss_advance(dc);
-            gen_exception(dc, EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
-        } else if (dc->is_jmp == DISAS_SMC && !dc->condjmp) {
-            gen_ss_advance(dc);
-            gen_exception(dc, EXCP_SMC, syn_aa32_smc(), 3);
-        } else if (dc->ss_active) {
-            gen_step_complete_exception(dc);
-        } else {
-            /* FIXME: Single stepping a WFI insn will not halt
-               the CPU.  */
-            gen_exception_internal(dc, EXCP_DEBUG);
         }
     } else {
         /* While branches must always occur at the end of an IT block,