From 58891e213dd09cc5243040d6474ea127a3ed01cc Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Fri, 5 Mar 2021 09:11:17 -0500 Subject: [PATCH] target/riscv: vector single-width integer multiply-add instructions Backports 54df813a331d3badfb83604c36bef7cb1de4315a --- qemu/header_gen.py | 32 +++++++ qemu/riscv32.h | 32 +++++++ qemu/riscv64.h | 32 +++++++ qemu/target/riscv/helper.h | 33 ++++++++ qemu/target/riscv/insn32.decode | 8 ++ qemu/target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ qemu/target/riscv/vector_helper.c | 88 ++++++++++++++++++++ 7 files changed, 235 insertions(+) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 87f470d9..6791e0bb 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -6773,6 +6773,38 @@ riscv_symbols = ( 'helpet_vwmulsu_vx_b', 'helpet_vwmulsu_vx_h', 'helpet_vwmulsu_vx_w', + 'helper_vmacc_vv_b', + 'helper_vmacc_vv_h', + 'helper_vmacc_vv_w', + 'helper_vmacc_vv_d', + 'helper_vnmsac_vv_b', + 'helper_vnmsac_vv_h', + 'helper_vnmsac_vv_w', + 'helper_vnmsac_vv_d', + 'helper_vmadd_vv_b', + 'helper_vmadd_vv_h', + 'helper_vmadd_vv_w', + 'helper_vmadd_vv_d', + 'helper_vnmsub_vv_b', + 'helper_vnmsub_vv_h', + 'helper_vnmsub_vv_w', + 'helper_vnmsub_vv_d', + 'helper_vmacc_vx_b', + 'helper_vmacc_vx_h', + 'helper_vmacc_vx_w', + 'helper_vmacc_vx_d', + 'helper_vnmsac_vx_b', + 'helper_vnmsac_vx_h', + 'helper_vnmsac_vx_w', + 'helper_vnmsac_vx_d', + 'helper_vmadd_vx_b', + 'helper_vmadd_vx_h', + 'helper_vmadd_vx_w', + 'helper_vmadd_vx_d', + 'helper_vnmsub_vx_b', + 'helper_vnmsub_vx_h', + 'helper_vnmsub_vx_w', + 'helper_vnmsub_vx_d', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 4c3d8539..0947fe09 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -4209,6 +4209,38 @@ #define helpet_vwmulsu_vx_b helpet_vwmulsu_vx_b_riscv32 #define helpet_vwmulsu_vx_h helpet_vwmulsu_vx_h_riscv32 #define helpet_vwmulsu_vx_w helpet_vwmulsu_vx_w_riscv32 +#define helper_vmacc_vv_b helper_vmacc_vv_b_riscv32 +#define helper_vmacc_vv_h helper_vmacc_vv_h_riscv32 +#define helper_vmacc_vv_w helper_vmacc_vv_w_riscv32 +#define helper_vmacc_vv_d helper_vmacc_vv_d_riscv32 +#define helper_vnmsac_vv_b helper_vnmsac_vv_b_riscv32 +#define helper_vnmsac_vv_h helper_vnmsac_vv_h_riscv32 +#define helper_vnmsac_vv_w helper_vnmsac_vv_w_riscv32 +#define helper_vnmsac_vv_d helper_vnmsac_vv_d_riscv32 +#define helper_vmadd_vv_b helper_vmadd_vv_b_riscv32 +#define helper_vmadd_vv_h helper_vmadd_vv_h_riscv32 +#define helper_vmadd_vv_w helper_vmadd_vv_w_riscv32 +#define helper_vmadd_vv_d helper_vmadd_vv_d_riscv32 +#define helper_vnmsub_vv_b helper_vnmsub_vv_b_riscv32 +#define helper_vnmsub_vv_h helper_vnmsub_vv_h_riscv32 +#define helper_vnmsub_vv_w helper_vnmsub_vv_w_riscv32 +#define helper_vnmsub_vv_d helper_vnmsub_vv_d_riscv32 +#define helper_vmacc_vx_b helper_vmacc_vx_b_riscv32 +#define helper_vmacc_vx_h helper_vmacc_vx_h_riscv32 +#define helper_vmacc_vx_w helper_vmacc_vx_w_riscv32 +#define helper_vmacc_vx_d helper_vmacc_vx_d_riscv32 +#define helper_vnmsac_vx_b helper_vnmsac_vx_b_riscv32 +#define helper_vnmsac_vx_h helper_vnmsac_vx_h_riscv32 +#define helper_vnmsac_vx_w helper_vnmsac_vx_w_riscv32 +#define helper_vnmsac_vx_d helper_vnmsac_vx_d_riscv32 +#define helper_vmadd_vx_b helper_vmadd_vx_b_riscv32 +#define helper_vmadd_vx_h helper_vmadd_vx_h_riscv32 +#define helper_vmadd_vx_w helper_vmadd_vx_w_riscv32 +#define helper_vmadd_vx_d helper_vmadd_vx_d_riscv32 +#define helper_vnmsub_vx_b helper_vnmsub_vx_b_riscv32 +#define helper_vnmsub_vx_h helper_vnmsub_vx_h_riscv32 +#define helper_vnmsub_vx_w helper_vnmsub_vx_w_riscv32 +#define helper_vnmsub_vx_d helper_vnmsub_vx_d_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 2dae0034..c1b5a67a 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -4209,6 +4209,38 @@ #define helpet_vwmulsu_vx_b helpet_vwmulsu_vx_b_riscv64 #define helpet_vwmulsu_vx_h helpet_vwmulsu_vx_h_riscv64 #define helpet_vwmulsu_vx_w helpet_vwmulsu_vx_w_riscv64 +#define helper_vmacc_vv_b helper_vmacc_vv_b_riscv64 +#define helper_vmacc_vv_h helper_vmacc_vv_h_riscv64 +#define helper_vmacc_vv_w helper_vmacc_vv_w_riscv64 +#define helper_vmacc_vv_d helper_vmacc_vv_d_riscv64 +#define helper_vnmsac_vv_b helper_vnmsac_vv_b_riscv64 +#define helper_vnmsac_vv_h helper_vnmsac_vv_h_riscv64 +#define helper_vnmsac_vv_w helper_vnmsac_vv_w_riscv64 +#define helper_vnmsac_vv_d helper_vnmsac_vv_d_riscv64 +#define helper_vmadd_vv_b helper_vmadd_vv_b_riscv64 +#define helper_vmadd_vv_h helper_vmadd_vv_h_riscv64 +#define helper_vmadd_vv_w helper_vmadd_vv_w_riscv64 +#define helper_vmadd_vv_d helper_vmadd_vv_d_riscv64 +#define helper_vnmsub_vv_b helper_vnmsub_vv_b_riscv64 +#define helper_vnmsub_vv_h helper_vnmsub_vv_h_riscv64 +#define helper_vnmsub_vv_w helper_vnmsub_vv_w_riscv64 +#define helper_vnmsub_vv_d helper_vnmsub_vv_d_riscv64 +#define helper_vmacc_vx_b helper_vmacc_vx_b_riscv64 +#define helper_vmacc_vx_h helper_vmacc_vx_h_riscv64 +#define helper_vmacc_vx_w helper_vmacc_vx_w_riscv64 +#define helper_vmacc_vx_d helper_vmacc_vx_d_riscv64 +#define helper_vnmsac_vx_b helper_vnmsac_vx_b_riscv64 +#define helper_vnmsac_vx_h helper_vnmsac_vx_h_riscv64 +#define helper_vnmsac_vx_w helper_vnmsac_vx_w_riscv64 +#define helper_vnmsac_vx_d helper_vnmsac_vx_d_riscv64 +#define helper_vmadd_vx_b helper_vmadd_vx_b_riscv64 +#define helper_vmadd_vx_h helper_vmadd_vx_h_riscv64 +#define helper_vmadd_vx_w helper_vmadd_vx_w_riscv64 +#define helper_vmadd_vx_d helper_vmadd_vx_d_riscv64 +#define helper_vnmsub_vx_b helper_vnmsub_vx_b_riscv64 +#define helper_vnmsub_vx_h helper_vnmsub_vx_h_riscv64 +#define helper_vnmsub_vx_w helper_vnmsub_vx_w_riscv64 +#define helper_vnmsub_vx_d helper_vnmsub_vx_d_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index b0257a81..bef58b69 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -610,3 +610,36 @@ DEF_HELPER_6(vwmulu_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwmulsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwmulsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwmulsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsac_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsub_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmacc_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsac_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsac_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsac_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsac_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadd_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadd_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadd_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadd_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsub_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsub_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsub_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsub_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index d6254faa..3332c467 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -381,6 +381,14 @@ vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm +vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm +vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm +vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm +vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm +vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm +vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm +vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm +vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index 78aa65a8..81231a91 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -1530,3 +1530,13 @@ GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check) GEN_OPIVX_WIDEN_TRANS(vwmul_vx) GEN_OPIVX_WIDEN_TRANS(vwmulu_vx) GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx) + +/* Vector Single-Width Integer Multiply-Add Instructions */ +GEN_OPIVV_TRANS(vmacc_vv, opivv_check) +GEN_OPIVV_TRANS(vnmsac_vv, opivv_check) +GEN_OPIVV_TRANS(vmadd_vv, opivv_check) +GEN_OPIVV_TRANS(vnmsub_vv, opivv_check) +GEN_OPIVX_TRANS(vmacc_vx, opivx_check) +GEN_OPIVX_TRANS(vnmsac_vx, opivx_check) +GEN_OPIVX_TRANS(vmadd_vx, opivx_check) +GEN_OPIVX_TRANS(vnmsub_vx, opivx_check) diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index 12de329a..9322824a 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -1878,3 +1878,91 @@ GEN_VEXT_VX(vwmulu_vx_w, 4, 8, clearq) GEN_VEXT_VX(vwmulsu_vx_b, 1, 2, clearh) GEN_VEXT_VX(vwmulsu_vx_h, 2, 4, clearl) GEN_VEXT_VX(vwmulsu_vx_w, 4, 8, clearq) + +/* Vector Single-Width Integer Multiply-Add Instructions */ +#define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ +static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ +{ \ + TX1 s1 = *((T1 *)vs1 + HS1(i)); \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + TD d = *((TD *)vd + HD(i)); \ + *((TD *)vd + HD(i)) = OP(s2, s1, d); \ +} + +#define DO_MACC(N, M, D) (M * N + D) +#define DO_NMSAC(N, M, D) (-(M * N) + D) +#define DO_MADD(N, M, D) (M * D + N) +#define DO_NMSUB(N, M, D) (-(M * D) + N) +RVVCALL(OPIVV3, vmacc_vv_b, OP_SSS_B, H1, H1, H1, DO_MACC) +RVVCALL(OPIVV3, vmacc_vv_h, OP_SSS_H, H2, H2, H2, DO_MACC) +RVVCALL(OPIVV3, vmacc_vv_w, OP_SSS_W, H4, H4, H4, DO_MACC) +RVVCALL(OPIVV3, vmacc_vv_d, OP_SSS_D, H8, H8, H8, DO_MACC) +RVVCALL(OPIVV3, vnmsac_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSAC) +RVVCALL(OPIVV3, vnmsac_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSAC) +RVVCALL(OPIVV3, vnmsac_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSAC) +RVVCALL(OPIVV3, vnmsac_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSAC) +RVVCALL(OPIVV3, vmadd_vv_b, OP_SSS_B, H1, H1, H1, DO_MADD) +RVVCALL(OPIVV3, vmadd_vv_h, OP_SSS_H, H2, H2, H2, DO_MADD) +RVVCALL(OPIVV3, vmadd_vv_w, OP_SSS_W, H4, H4, H4, DO_MADD) +RVVCALL(OPIVV3, vmadd_vv_d, OP_SSS_D, H8, H8, H8, DO_MADD) +RVVCALL(OPIVV3, vnmsub_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSUB) +RVVCALL(OPIVV3, vnmsub_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSUB) +RVVCALL(OPIVV3, vnmsub_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSUB) +RVVCALL(OPIVV3, vnmsub_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSUB) +GEN_VEXT_VV(vmacc_vv_b, 1, 1, clearb) +GEN_VEXT_VV(vmacc_vv_h, 2, 2, clearh) +GEN_VEXT_VV(vmacc_vv_w, 4, 4, clearl) +GEN_VEXT_VV(vmacc_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vnmsac_vv_b, 1, 1, clearb) +GEN_VEXT_VV(vnmsac_vv_h, 2, 2, clearh) +GEN_VEXT_VV(vnmsac_vv_w, 4, 4, clearl) +GEN_VEXT_VV(vnmsac_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vmadd_vv_b, 1, 1, clearb) +GEN_VEXT_VV(vmadd_vv_h, 2, 2, clearh) +GEN_VEXT_VV(vmadd_vv_w, 4, 4, clearl) +GEN_VEXT_VV(vmadd_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vnmsub_vv_b, 1, 1, clearb) +GEN_VEXT_VV(vnmsub_vv_h, 2, 2, clearh) +GEN_VEXT_VV(vnmsub_vv_w, 4, 4, clearl) +GEN_VEXT_VV(vnmsub_vv_d, 8, 8, clearq) + +#define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ +{ \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + TD d = *((TD *)vd + HD(i)); \ + *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, d); \ +} + +RVVCALL(OPIVX3, vmacc_vx_b, OP_SSS_B, H1, H1, DO_MACC) +RVVCALL(OPIVX3, vmacc_vx_h, OP_SSS_H, H2, H2, DO_MACC) +RVVCALL(OPIVX3, vmacc_vx_w, OP_SSS_W, H4, H4, DO_MACC) +RVVCALL(OPIVX3, vmacc_vx_d, OP_SSS_D, H8, H8, DO_MACC) +RVVCALL(OPIVX3, vnmsac_vx_b, OP_SSS_B, H1, H1, DO_NMSAC) +RVVCALL(OPIVX3, vnmsac_vx_h, OP_SSS_H, H2, H2, DO_NMSAC) +RVVCALL(OPIVX3, vnmsac_vx_w, OP_SSS_W, H4, H4, DO_NMSAC) +RVVCALL(OPIVX3, vnmsac_vx_d, OP_SSS_D, H8, H8, DO_NMSAC) +RVVCALL(OPIVX3, vmadd_vx_b, OP_SSS_B, H1, H1, DO_MADD) +RVVCALL(OPIVX3, vmadd_vx_h, OP_SSS_H, H2, H2, DO_MADD) +RVVCALL(OPIVX3, vmadd_vx_w, OP_SSS_W, H4, H4, DO_MADD) +RVVCALL(OPIVX3, vmadd_vx_d, OP_SSS_D, H8, H8, DO_MADD) +RVVCALL(OPIVX3, vnmsub_vx_b, OP_SSS_B, H1, H1, DO_NMSUB) +RVVCALL(OPIVX3, vnmsub_vx_h, OP_SSS_H, H2, H2, DO_NMSUB) +RVVCALL(OPIVX3, vnmsub_vx_w, OP_SSS_W, H4, H4, DO_NMSUB) +RVVCALL(OPIVX3, vnmsub_vx_d, OP_SSS_D, H8, H8, DO_NMSUB) +GEN_VEXT_VX(vmacc_vx_b, 1, 1, clearb) +GEN_VEXT_VX(vmacc_vx_h, 2, 2, clearh) +GEN_VEXT_VX(vmacc_vx_w, 4, 4, clearl) +GEN_VEXT_VX(vmacc_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vnmsac_vx_b, 1, 1, clearb) +GEN_VEXT_VX(vnmsac_vx_h, 2, 2, clearh) +GEN_VEXT_VX(vnmsac_vx_w, 4, 4, clearl) +GEN_VEXT_VX(vnmsac_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vmadd_vx_b, 1, 1, clearb) +GEN_VEXT_VX(vmadd_vx_h, 2, 2, clearh) +GEN_VEXT_VX(vmadd_vx_w, 4, 4, clearl) +GEN_VEXT_VX(vmadd_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vnmsub_vx_b, 1, 1, clearb) +GEN_VEXT_VX(vnmsub_vx_h, 2, 2, clearh) +GEN_VEXT_VX(vnmsub_vx_w, 4, 4, clearl) +GEN_VEXT_VX(vnmsub_vx_d, 8, 8, clearq)