diff --git a/qemu/target/mips/cpu.h b/qemu/target/mips/cpu.h
index c3fb1251..0ce644d7 100644
--- a/qemu/target/mips/cpu.h
+++ b/qemu/target/mips/cpu.h
@@ -171,6 +171,16 @@ struct TCState {
         MSACSR_FS_MASK)
 
     float_status msa_fp_status;
+
+#define NUMBER_OF_MXU_REGISTERS 16
+    target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
+    target_ulong mxu_cr;
+#define MXU_CR_LC       31
+#define MXU_CR_RC       30
+#define MXU_CR_BIAS     2
+#define MXU_CR_RD_EN    1
+#define MXU_CR_MXU_EN   0
+
 };
 
 typedef struct CPUMIPSState CPUMIPSState;
diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c
index 8efe4d5b..6ffb20cc 100644
--- a/qemu/target/mips/translate.c
+++ b/qemu/target/mips/translate.c
@@ -2440,6 +2440,7 @@ typedef struct DisasContext {
     bool mrp;
     bool nan2008;
     bool abs2008;
+
     // Unicorn engine
     struct uc_struct *uc;
 } DisasContext;
@@ -2488,6 +2489,11 @@ static const char * const msaregnames[] = {
     "w30.d0", "w30.d1", "w31.d0", "w31.d1",
 };
 
+static const char * const mxuregnames[] = {
+    "XR1",  "XR2",  "XR3",  "XR4",  "XR5",  "XR6",  "XR7",  "XR8",
+    "XR9",  "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR",
+};
+
 #define LOG_DISAS(...)                                                        \
     do {                                                                      \
         if (MIPS_DEBUG_DISAS) {                                               \
@@ -27409,6 +27415,18 @@ void mips_tcg_init(struct uc_struct *uc)
     tcg_ctx->fpu_fcr31 = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env,
                                        offsetof(CPUMIPSState, active_fpu.fcr31),
                                        "fcr31");
+
+    for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
+        tcg_ctx->mxu_gpr[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+                                                 offsetof(CPUMIPSState,
+                                                          active_tc.mxu_gpr[i]),
+                                                 mxuregnames[i]);
+    }
+
+    tcg_ctx->mxu_CR = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+                                         offsetof(CPUMIPSState, active_tc.mxu_cr),
+                                         mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
+
     uc->init_tcg = true;
 }
 
diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h
index aece444b..0c410e19 100644
--- a/qemu/tcg/tcg.h
+++ b/qemu/tcg/tcg.h
@@ -891,6 +891,8 @@ struct TCGContext {
     TCGv_i32 fpu_fcr31;
     TCGv_i64 fpu_f64[32];
     TCGv_i64 msa_wr_d[64];
+    TCGv mxu_gpr[16 - 1]; // NUMBER_OF_MXU_REGISTERS - 1
+    TCGv mxu_CR;
 
     /* qemu/target-sparc/translate.c */
     /* global register indexes */