diff --git a/qemu/aarch64.h b/qemu/aarch64.h
index 6d6c2ff5..f69327a5 100644
--- a/qemu/aarch64.h
+++ b/qemu/aarch64.h
@@ -3575,6 +3575,7 @@
 #define helper_gvec_usra_d helper_gvec_usra_d_aarch64
 #define helper_gvec_usra_h helper_gvec_usra_h_aarch64
 #define helper_gvec_usra_s helper_gvec_usra_s_aarch64
+#define helper_irg helper_irg_aarch64
 #define helper_msr_i_daifclear helper_msr_i_daifclear_aarch64
 #define helper_msr_i_daifset helper_msr_i_daifset_aarch64
 #define helper_msr_i_spsel helper_msr_i_spsel_aarch64
diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h
index b04e69c0..8e1984e7 100644
--- a/qemu/aarch64eb.h
+++ b/qemu/aarch64eb.h
@@ -3575,6 +3575,7 @@
 #define helper_gvec_usra_d helper_gvec_usra_d_aarch64eb
 #define helper_gvec_usra_h helper_gvec_usra_h_aarch64eb
 #define helper_gvec_usra_s helper_gvec_usra_s_aarch64eb
+#define helper_irg helper_irg_aarch64eb
 #define helper_msr_i_daifclear helper_msr_i_daifclear_aarch64eb
 #define helper_msr_i_daifset helper_msr_i_daifset_aarch64eb
 #define helper_msr_i_spsel helper_msr_i_spsel_aarch64eb
diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index f86bd564..43068a03 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -3709,6 +3709,7 @@ aarch64_symbols = (
     'helper_gvec_usra_d',
     'helper_gvec_usra_h',
     'helper_gvec_usra_s',
+    'helper_irg',
     'helper_msr_i_daifclear',
     'helper_msr_i_daifset',
     'helper_msr_i_spsel',
diff --git a/qemu/target/arm/Makefile.objs b/qemu/target/arm/Makefile.objs
index 7cbd3622..711026dc 100644
--- a/qemu/target/arm/Makefile.objs
+++ b/qemu/target/arm/Makefile.objs
@@ -79,3 +79,4 @@ obj-$(CONFIG_SOFTMMU) += psci.o
 obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
 obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o
 obj-$(TARGET_AARCH64) += pauth_helper.o
+obj-$(TARGET_AARCH64) += mte_helper.o
diff --git a/qemu/target/arm/helper-a64.h b/qemu/target/arm/helper-a64.h
index 62ef2eca..086e4415 100644
--- a/qemu/target/arm/helper-a64.h
+++ b/qemu/target/arm/helper-a64.h
@@ -102,4 +102,6 @@ DEF_HELPER_FLAGS_3(autib, TCG_CALL_NO_WG, i64, env, i64, i64)
 DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64)
 DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64)
 DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64)
-DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64)
\ No newline at end of file
+DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64)
+
+DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64)
\ No newline at end of file
diff --git a/qemu/target/arm/internals.h b/qemu/target/arm/internals.h
index 01c66970..e5320b4e 100644
--- a/qemu/target/arm/internals.h
+++ b/qemu/target/arm/internals.h
@@ -1265,4 +1265,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
  */
 #define GMID_EL1_BS  6
 
+static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag)
+{
+    return deposit64(ptr, 56, 4, rtag);
+}
+
 #endif
diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c
index 7f6d17a2..077ddf3a 100644
--- a/qemu/target/arm/translate-a64.c
+++ b/qemu/target/arm/translate-a64.c
@@ -363,6 +363,12 @@ static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)
     return clean;
 }
 
+/* Insert a zero tag into src, with the result at dst. */
+static void gen_address_with_allocation_tag0(TCGContext *s, TCGv_i64 dst, TCGv_i64 src)
+{
+    tcg_gen_andi_i64(s, dst, src, ~MAKE_64BIT_MASK(56, 4));
+}
+
 typedef struct DisasCompare64 {
     TCGCond cond;
     TCGv_i64 value;
@@ -5506,6 +5512,18 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
     case 3: /* SDIV */
         handle_div(s, true, sf, rm, rn, rd);
         break;
+    case 4: /* IRG */
+        if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
+            goto do_unallocated;
+        }
+        if (s->ata) {
+            gen_helper_irg(tcg_ctx, cpu_reg_sp(s, rd), tcg_ctx->cpu_env,
+                           cpu_reg_sp(s, rn), cpu_reg(s, rm));
+        } else {
+            gen_address_with_allocation_tag0(tcg_ctx, cpu_reg_sp(s, rd),
+                                             cpu_reg_sp(s, rn));
+        }
+        break;
     case 8: /* LSLV */
         handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
         break;