From 5a7ad783e9bbd5f1694c20bd2c0be695aa03adf9 Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng@gmail.com>
Date: Tue, 26 Mar 2019 20:39:25 -0400
Subject: [PATCH] target/riscv: Fix wrong expanding for c.fswsp

base register is no rs1 not rs2 for fsw.

Backports commit 620455350a8da7cc62ae82cb69dd5c556f744136 from qemu
---
 qemu/target/riscv/insn_trans/trans_rvc.inc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/qemu/target/riscv/insn_trans/trans_rvc.inc.c b/qemu/target/riscv/insn_trans/trans_rvc.inc.c
index 5819f53f..ebcd977b 100644
--- a/qemu/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/qemu/target/riscv/insn_trans/trans_rvc.inc.c
@@ -337,7 +337,7 @@ static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
 {
 #ifdef TARGET_RISCV32
     /* C.FSWSP */
-    arg_fsw a_fsw = { .rs1 = a->rs2, .rs2 = 2, .imm = a->uimm_fswsp };
+    arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp };
     return trans_fsw(ctx, &a_fsw);
 #else
     /* C.SDSP */