From 5ad3a0ea82b61efa7b7defb9c557b251df045fa0 Mon Sep 17 00:00:00 2001 From: cfrantz Date: Thu, 28 Feb 2019 16:40:48 -0500 Subject: [PATCH] Add support for the ARM IPSR register. (#1067) 1. Create an enum name for the IPSR register. 2. Implement read and write of the IPSR via the xpsr helper functions. Fixes #1065 Backports commit 6c319941a5462ee3a4af4593c371f5674394d6ce from unicorn. --- include/unicorn/arm.h | 1 + qemu/target/arm/unicorn_arm.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/include/unicorn/arm.h b/include/unicorn/arm.h index f9130057..2726d147 100644 --- a/include/unicorn/arm.h +++ b/include/unicorn/arm.h @@ -133,6 +133,7 @@ typedef enum uc_arm_reg { UC_ARM_REG_C13_C0_2, UC_ARM_REG_C13_C0_3, + UC_ARM_REG_IPSR, UC_ARM_REG_ENDING, // <-- mark the end of the list or registers //> alias registers diff --git a/qemu/target/arm/unicorn_arm.c b/qemu/target/arm/unicorn_arm.c index 64f39c20..e4c354a2 100644 --- a/qemu/target/arm/unicorn_arm.c +++ b/qemu/target/arm/unicorn_arm.c @@ -93,6 +93,9 @@ int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun case UC_ARM_REG_FPEXC: *(int32_t *)value = state->vfp.xregs[ARM_VFP_FPEXC]; break; + case UC_ARM_REG_IPSR: + *(uint32_t *)value = xpsr_read(state) & 0x1ff; + break; case UC_ARM_REG_FPSCR: *(int32_t *)value = vfp_get_fpscr(state); break; @@ -157,6 +160,9 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i case UC_ARM_REG_FPSCR: vfp_set_fpscr(state, *(uint32_t *)value); break; + case UC_ARM_REG_IPSR: + xpsr_write(state, *(uint32_t *)value, 0x1ff); + break; } } }