From 5b8ad0e2fc9715467a7dcb2fb7157df4bb71944a Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 20 Feb 2018 11:38:25 -0500 Subject: [PATCH] target-arm: Fix IL bit reported for Thumb coprocessor traps All Thumb coprocessor instructions are 32 bits, so the IL bit in the syndrome register should be set. Pass false to the syn_* function's is_16bit argument rather than s->thumb so we report the correct IL bit. Backports commit 4df322593037d2700f72dfdfb967300b7ad2e696 from qemu --- qemu/target-arm/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qemu/target-arm/translate.c b/qemu/target-arm/translate.c index df9b0454..da76befb 100644 --- a/qemu/target-arm/translate.c +++ b/qemu/target-arm/translate.c @@ -7314,19 +7314,19 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) case 14: if (is64) { syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, - isread, s->thumb); + isread, false); } else { syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, - rt, isread, s->thumb); + rt, isread, false); } break; case 15: if (is64) { syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, - isread, s->thumb); + isread, false); } else { syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, - rt, isread, s->thumb); + rt, isread, false); } break; default: