From 5ca33a4aaac81e8a56d4c77369c2f02c03678092 Mon Sep 17 00:00:00 2001
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: Thu, 30 Apr 2020 07:14:00 -0400
Subject: [PATCH] target/mips: Fix loongson multimedia condition instructions

Loongson multimedia condition instructions were previously implemented as
write 0 to rd due to lack of documentation. So I just confirmed with Loongson
about their encoding and implemented them correctly.

Backports commit 84878f4c00a7beca1d1460e2f77a6c833b8d0393 from qemu
---
 qemu/target/mips/translate.c | 34 ++++++++++++++++++++++++++++++----
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c
index 0c7add55..17b83e32 100644
--- a/qemu/target/mips/translate.c
+++ b/qemu/target/mips/translate.c
@@ -5588,6 +5588,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
     TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
     uint32_t opc, shift_max;
     TCGv_i64 t0, t1;
+    TCGCond cond;
 
     opc = MASK_LMI(ctx->opcode);
     switch (opc) {
@@ -5818,14 +5819,39 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
 
     case OPC_SEQU_CP2:
     case OPC_SEQ_CP2:
+        cond = TCG_COND_EQ;
+        goto do_cc_cond;
+        break;
     case OPC_SLTU_CP2:
+        cond = TCG_COND_LTU;
+        goto do_cc_cond;
+        break;
     case OPC_SLT_CP2:
+        cond = TCG_COND_LT;
+        goto do_cc_cond;
+        break;
     case OPC_SLEU_CP2:
+        cond = TCG_COND_LEU;
+        goto do_cc_cond;
+        break;
     case OPC_SLE_CP2:
-        /*
-         * ??? Document is unclear: Set FCC[CC].  Does that mean the
-         * FD field is the CC field?
-         */
+        cond = TCG_COND_LE;
+    do_cc_cond:
+        {
+            int cc = (ctx->opcode >> 8) & 0x7;
+            TCGv_i64 t64 = tcg_temp_new_i64(tcg_ctx);
+            TCGv_i32 t32 = tcg_temp_new_i32(tcg_ctx);
+
+            tcg_gen_setcond_i64(tcg_ctx, cond, t64, t0, t1);
+            tcg_gen_extrl_i64_i32(tcg_ctx, t32, t64);
+            tcg_gen_deposit_i32(tcg_ctx, tcg_ctx->fpu_fcr31, tcg_ctx->fpu_fcr31, t32,
+                                get_fp_bit(cc), 1);
+
+            tcg_temp_free_i32(tcg_ctx, t32);
+            tcg_temp_free_i64(tcg_ctx, t64);
+        }
+        goto no_rd;
+        break;
     default:
         MIPS_INVAL("loongson_cp2");
         generate_exception_end(ctx, EXCP_RI);