From 5de5b69344976bbcc2c2d58052272003b26e2eca Mon Sep 17 00:00:00 2001 From: Lioncash Date: Tue, 16 Apr 2019 06:29:01 -0400 Subject: [PATCH] target/i386: Fix compilation of the x86 target Thanks to @rk700 for reporting it. --- Makefile | 3 --- qemu/target/i386/translate.c | 26 +++++++++++++------------- uc.c | 4 ++-- 3 files changed, 15 insertions(+), 18 deletions(-) diff --git a/Makefile b/Makefile index 01799946..ab8574d7 100644 --- a/Makefile +++ b/Makefile @@ -26,11 +26,8 @@ ifneq (,$(findstring x86,$(UNICORN_ARCHS))) endif ifneq (,$(findstring arm,$(UNICORN_ARCHS))) UC_TARGET_OBJ += $(call GENOBJ,arm-softmmu) - UC_TARGET_OBJ += $(call GENOBJ,armeb-softmmu) UNICORN_CFLAGS += -DUNICORN_HAS_ARM - UNICORN_CFLAGS += -DUNICORN_HAS_ARMEB UNICORN_TARGETS += arm-softmmu, - UNICORN_TARGETS += armeb-softmmu, endif ifneq (,$(findstring m68k,$(UNICORN_ARCHS))) UC_TARGET_OBJ += $(call GENOBJ,m68k-softmmu) diff --git a/qemu/target/i386/translate.c b/qemu/target/i386/translate.c index 34bd826c..209bd31c 100644 --- a/qemu/target/i386/translate.c +++ b/qemu/target/i386/translate.c @@ -1557,34 +1557,34 @@ static void gen_op(DisasContext *s, int op, TCGMemOp ot, int d) } /* if d == OR_TMP0, it means memory operand (address in A0) */ -static void gen_inc(DisasContext *s, TCGMemOp ot, int d, int c) +static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c) { - TCGContext *tcg_ctx = s->uc->tcg_ctx; + TCGContext *tcg_ctx = s1->uc->tcg_ctx; TCGv cpu_cc_dst = tcg_ctx->cpu_cc_dst; TCGv cpu_cc_src = tcg_ctx->cpu_cc_src; - if (s->prefix & PREFIX_LOCK) { + if (s1->prefix & PREFIX_LOCK) { if (d != OR_TMP0) { /* Lock prefix when destination is not memory */ gen_illegal_opcode(s1); return; } - tcg_gen_movi_tl(tcg_ctx, s->T0, c > 0 ? 1 : -1); - tcg_gen_atomic_add_fetch_tl(tcg_ctx, s->T0, s->A0, s->T0, - s->mem_index, ot | MO_LE); + tcg_gen_movi_tl(tcg_ctx, s1->T0, c > 0 ? 1 : -1); + tcg_gen_atomic_add_fetch_tl(tcg_ctx, s1->T0, s1->A0, s1->T0, + s1->mem_index, ot | MO_LE); } else { if (d != OR_TMP0) { - gen_op_mov_v_reg(s, ot, s->T0, d); + gen_op_mov_v_reg(s1, ot, s1->T0, d); } else { - gen_op_ld_v(s, ot, s->T0, s->A0); + gen_op_ld_v(s1, ot, s1->T0, s1->A0); } - tcg_gen_addi_tl(tcg_ctx, s->T0, s->T0, (c > 0 ? 1 : -1)); - gen_op_st_rm_T0_A0(s, ot, d); + tcg_gen_addi_tl(tcg_ctx, s1->T0, s1->T0, (c > 0 ? 1 : -1)); + gen_op_st_rm_T0_A0(s1, ot, d); } - gen_compute_eflags_c(s, cpu_cc_src); - tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, s->T0); - set_cc_op(s, (c > 0 ? CC_OP_INCB : CC_OP_DECB) + ot); + gen_compute_eflags_c(s1, cpu_cc_src); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, s1->T0); + set_cc_op(s1, (c > 0 ? CC_OP_INCB : CC_OP_DECB) + ot); } static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result, diff --git a/uc.c b/uc.c index d20b7e52..d8670a78 100644 --- a/uc.c +++ b/uc.c @@ -199,7 +199,7 @@ uc_err uc_open(uc_arch arch, uc_mode mode, uc_engine **result) return UC_ERR_MODE; } if (mode & UC_MODE_BIG_ENDIAN) { - uc->init_arch = armeb_uc_init; + //uc->init_arch = armeb_uc_init; } else { uc->init_arch = arm_uc_init; } @@ -1244,7 +1244,7 @@ static size_t cpu_context_size(uc_arch arch, uc_mode mode) case UC_ARCH_X86: return X86_REGS_STORAGE_SIZE; #endif #ifdef UNICORN_HAS_ARM - case UC_ARCH_ARM: return mode & UC_MODE_BIG_ENDIAN ? ARM_REGS_STORAGE_SIZE_armeb : ARM_REGS_STORAGE_SIZE_arm; + case UC_ARCH_ARM: return ARM_REGS_STORAGE_SIZE_arm; #endif #ifdef UNICORN_HAS_ARM64 case UC_ARCH_ARM64: return mode & UC_MODE_BIG_ENDIAN ? ARM64_REGS_STORAGE_SIZE_aarch64eb : ARM64_REGS_STORAGE_SIZE_aarch64;