From 5e3349a8186afb6a7ce42549f2525538cdc1f41b Mon Sep 17 00:00:00 2001 From: Wei Huang Date: Fri, 2 Mar 2018 07:57:36 -0500 Subject: [PATCH] target-arm: Add support for PMU register PMINTENSET_EL1 This patch adds access support for PMINTENSET_EL1. Backports commit e6ec54571e424bb1d6e50e32fe317c616cde3e05 from qemu --- qemu/target/arm/cpu.h | 2 +- qemu/target/arm/helper.c | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h index cab0927e..b41a89e9 100644 --- a/qemu/target/arm/cpu.h +++ b/qemu/target/arm/cpu.h @@ -313,7 +313,7 @@ typedef struct CPUARMState { uint32_t c9_pmovsr; /* perf monitor overflow status */ uint32_t c9_pmuserenr; /* perf monitor user enable */ uint64_t c9_pmselr; /* perf monitor counter selection register */ - uint32_t c9_pminten; /* perf monitor interrupt enables */ + uint64_t c9_pminten; /* perf monitor interrupt enables */ union { /* Memory attribute redirection */ struct { #ifdef HOST_WORDS_BIGENDIAN diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 1c4e3acf..4e8d6322 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -1128,8 +1128,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { "PMUSERENR_EL0", 0,9,14,3,3,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS, PL0_R | PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmuserenr), {0, 0}, access_tpm, NULL, pmuserenr_write, NULL, raw_write }, - { "PMINTENSET", 15,9,14, 0,0,1, 0, - 0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0}, + { "PMINTENSET", 15,9,14, 0,0,1, 0, ARM_CP_ALIAS, + PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.c9_pminten), {0, 0}, + access_tpm, NULL, pmintenset_write, NULL, raw_write }, + { "PMINTENSET_EL1", 0,9,14, 3,0,1, ARM_CP_STATE_AA64, ARM_CP_IO, + PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0}, access_tpm, NULL, pmintenset_write, NULL, raw_write }, { "PMINTENCLR", 15,9,14, 0,0,2, 0, ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},