diff --git a/qemu/include/fpu/softfloat-macros.h b/qemu/include/fpu/softfloat-macros.h
index 46fdd4b1..50d3dd16 100644
--- a/qemu/include/fpu/softfloat-macros.h
+++ b/qemu/include/fpu/softfloat-macros.h
@@ -79,6 +79,9 @@ this code that are retained.
  * version 2 or later. See the COPYING file in the top-level directory.
  */
 
+#ifndef FPU_SOFTFLOAT_MACROS_H
+#define FPU_SOFTFLOAT_MACROS_H
+
 /*----------------------------------------------------------------------------
 | Shifts `a' right by the number of bits given in `count'.  If any nonzero
 | bits are shifted off, they are ``jammed'' into the least significant bit of
@@ -796,3 +799,5 @@ static inline flag ne128( uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1 )
     return ( a0 != b0 ) || ( a1 != b1 );
 
 }
+
+#endif
diff --git a/qemu/target/riscv/cpu_bits.h b/qemu/target/riscv/cpu_bits.h
index ca1d3c61..9cd2e3f4 100644
--- a/qemu/target/riscv/cpu_bits.h
+++ b/qemu/target/riscv/cpu_bits.h
@@ -1,5 +1,8 @@
 /* RISC-V ISA constants */
 
+#ifndef TARGET_RISCV_CPU_BITS_H
+#define TARGET_RISCV_CPU_BITS_H
+
 #define get_field(reg, mask) (((reg) & \
                  (target_ulong)(mask)) / ((mask) & ~((mask) << 1)))
 #define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \
@@ -527,3 +530,5 @@
 #define SIP_SSIP                           MIP_SSIP
 #define SIP_STIP                           MIP_STIP
 #define SIP_SEIP                           MIP_SEIP
+
+#endif
diff --git a/qemu/target/riscv/cpu_user.h b/qemu/target/riscv/cpu_user.h
index 52d380aa..02afad60 100644
--- a/qemu/target/riscv/cpu_user.h
+++ b/qemu/target/riscv/cpu_user.h
@@ -1,3 +1,6 @@
+#ifndef TARGET_RISCV_CPU_USER_H
+#define TARGET_RISCV_CPU_USER_H
+
 #define xRA 1   /* return address (aka link register) */
 #define xSP 2   /* stack pointer */
 #define xGP 3   /* global pointer */
@@ -12,3 +15,5 @@
 #define xA6 16
 #define xA7 17  /* syscall number for RVI ABI */
 #define xT0 5   /* syscall number for RVE ABI */
+
+#endif
diff --git a/qemu/target/riscv/instmap.h b/qemu/target/riscv/instmap.h
index 58baa1ba..f8ad7d60 100644
--- a/qemu/target/riscv/instmap.h
+++ b/qemu/target/riscv/instmap.h
@@ -16,6 +16,9 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#ifndef TARGET_RISCV_INSTMAP_H
+#define TARGET_RISCV_INSTMAP_H
+
 #define MASK_OP_MAJOR(op)  (op & 0x7F)
 enum {
     /* rv32i, rv64i, rv32m */
@@ -362,3 +365,5 @@ enum {
 #define GET_C_RS2(inst)             extract32(inst, 2, 5)
 #define GET_C_RS1S(inst)            (8 + extract32(inst, 7, 3))
 #define GET_C_RS2S(inst)            (8 + extract32(inst, 2, 3))
+
+#endif
diff --git a/qemu/tcg/tcg-gvec-desc.h b/qemu/tcg/tcg-gvec-desc.h
index 2dda7d6b..0224ac3e 100644
--- a/qemu/tcg/tcg-gvec-desc.h
+++ b/qemu/tcg/tcg-gvec-desc.h
@@ -17,6 +17,9 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#ifndef TCG_TCG_GVEC_DESC_H
+#define TCG_TCG_GVEC_DESC_H
+
 /* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */
 #define SIMD_OPRSZ_SHIFT   0
 #define SIMD_OPRSZ_BITS    5
@@ -47,3 +50,5 @@ static inline int32_t simd_data(uint32_t desc)
 {
     return sextract32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS);
 }
+
+#endif
diff --git a/qemu/tcg/tcg-op-gvec.h b/qemu/tcg/tcg-op-gvec.h
index 1cac83f9..8c9dbdc1 100644
--- a/qemu/tcg/tcg-op-gvec.h
+++ b/qemu/tcg/tcg-op-gvec.h
@@ -28,6 +28,9 @@
  * Operands may completely, but not partially, overlap.
  */
 
+#ifndef TCG_TCG_OP_GVEC_H
+#define TCG_TCG_OP_GVEC_H
+
 /* Expand a call to a gvec-style helper, with pointers to two vector
    operands, and a descriptor (see tcg-gvec-desc.h).  */
 typedef void gen_helper_gvec_2(TCGContext *, TCGv_ptr, TCGv_ptr, TCGv_i32);
@@ -373,3 +376,5 @@ void tcg_gen_vec_shr8i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t);
 void tcg_gen_vec_shr16i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t);
 void tcg_gen_vec_sar8i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t);
 void tcg_gen_vec_sar16i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t);
+
+#endif