From 5e5b3e9ea9fd327ed2c0a60ca6f9c02c2c3e498d Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Mon, 18 Mar 2019 15:41:19 -0400 Subject: [PATCH] target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu --- qemu/header_gen.py | 1 + qemu/riscv32.h | 1 + qemu/riscv64.h | 1 + qemu/target/riscv/Makefile.objs | 10 ++++++ qemu/target/riscv/insn32.decode | 30 ++++++++++++++++ qemu/target/riscv/insn_trans/trans_rvi.inc.c | 37 ++++++++++++++++++++ qemu/target/riscv/translate.c | 31 ++++++++-------- 7 files changed, 97 insertions(+), 14 deletions(-) create mode 100644 qemu/target/riscv/insn32.decode create mode 100644 qemu/target/riscv/insn_trans/trans_rvi.inc.c diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 96c35824..6985b0af 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -5411,6 +5411,7 @@ riscv_symbols = ( 'cpu_riscv_set_fflags', 'csr_read_helper', 'csr_write_helper', + 'decode_insn32', 'do_raise_exception_err', 'gen_helper_tlb_flush', 'helper_csrrc', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 9a789293..60438aef 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -3332,6 +3332,7 @@ #define cpu_riscv_set_fflags cpu_riscv_set_fflags_riscv32 #define csr_read_helper csr_read_helper_riscv32 #define csr_write_helper csr_write_helper_riscv32 +#define decode_insn32 decode_insn32_riscv32 #define do_raise_exception_err do_raise_exception_err_riscv32 #define gen_helper_tlb_flush gen_helper_tlb_flush_riscv32 #define helper_csrrc helper_csrrc_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index e88cbc1a..8f4f74de 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -3332,6 +3332,7 @@ #define cpu_riscv_set_fflags cpu_riscv_set_fflags_riscv64 #define csr_read_helper csr_read_helper_riscv64 #define csr_write_helper csr_write_helper_riscv64 +#define decode_insn32 decode_insn32_riscv64 #define do_raise_exception_err do_raise_exception_err_riscv64 #define gen_helper_tlb_flush gen_helper_tlb_flush_riscv64 #define helper_csrrc helper_csrrc_riscv64 diff --git a/qemu/target/riscv/Makefile.objs b/qemu/target/riscv/Makefile.objs index 7e07ff06..47447e82 100644 --- a/qemu/target/riscv/Makefile.objs +++ b/qemu/target/riscv/Makefile.objs @@ -1,2 +1,12 @@ obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o pmp.o obj-y += unicorn.o + +DECODETREE = $(SRC_PATH)/scripts/decodetree.py + +target/riscv/decode_insn32.inc.c: \ + $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE) + $(call quiet-command, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \ + "GEN", $(TARGET_DIR)$@) + +target/riscv/translate.o: target/riscv/decode_insn32.inc.c diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode new file mode 100644 index 00000000..97c47d2f --- /dev/null +++ b/qemu/target/riscv/insn32.decode @@ -0,0 +1,30 @@ +# +# RISC-V translation routines for the RVXI Base Integer Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . + +# Fields: +%rd 7:5 + +# immediates: +%imm_u 12:s20 !function=ex_shift_12 + +# Formats 32: +@u .................... ..... ....... imm=%imm_u %rd + +# *** RV32I Base Instruction Set *** +lui .................... ..... 0110111 @u +auipc .................... ..... 0010111 @u \ No newline at end of file diff --git a/qemu/target/riscv/insn_trans/trans_rvi.inc.c b/qemu/target/riscv/insn_trans/trans_rvi.inc.c new file mode 100644 index 00000000..baa22954 --- /dev/null +++ b/qemu/target/riscv/insn_trans/trans_rvi.inc.c @@ -0,0 +1,37 @@ +/* + * RISC-V translation routines for the RVXI Base Integer Instruction Set. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +static bool trans_lui(DisasContext *ctx, arg_lui *a) +{ + if (a->rd != 0) { + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[a->rd], a->imm); + } + return true; +} + +static bool trans_auipc(DisasContext *ctx, arg_auipc *a) +{ + if (a->rd != 0) { + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[a->rd], a->imm + ctx->base.pc_next); + } + return true; +} diff --git a/qemu/target/riscv/translate.c b/qemu/target/riscv/translate.c index 5a1a442e..17b49aed 100644 --- a/qemu/target/riscv/translate.c +++ b/qemu/target/riscv/translate.c @@ -1946,6 +1946,19 @@ static void decode_RV32_64C(DisasContext *ctx) } } +#define EX_SH(amount) \ + static int ex_shift_##amount(int imm) \ + { \ + return imm << amount; \ + } +EX_SH(12) + +bool decode_insn32(DisasContext *ctx, uint32_t insn); +/* Include the auto-generated decoder for 32 bit insn */ +#include "decode_insn32.inc.c" +/* Include insn module translation function */ +#include "insn_trans/trans_rvi.inc.c" + static void decode_RV32_64G(DisasContext *ctx) { TCGContext *tcg_ctx = ctx->uc->tcg_ctx; @@ -1967,19 +1980,6 @@ static void decode_RV32_64G(DisasContext *ctx) imm = GET_IMM(ctx->opcode); switch (op) { - case OPC_RISC_LUI: - if (rd == 0) { - break; /* NOP */ - } - tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr_risc[rd], sextract64(ctx->opcode, 12, 20) << 12); - break; - case OPC_RISC_AUIPC: - if (rd == 0) { - break; /* NOP */ - } - tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr_risc[rd], (sextract64(ctx->opcode, 12, 20) << 12) + - ctx->base.pc_next); - break; case OPC_RISC_JAL: imm = GET_JAL_IMM(ctx->opcode); gen_jal(ctx, rd, imm); @@ -2084,7 +2084,10 @@ static void decode_opc(DisasContext *ctx) } } else { ctx->pc_succ_insn = ctx->base.pc_next + 4; - decode_RV32_64G(ctx); + if (!decode_insn32(ctx, ctx->opcode)) { + /* fallback to old decoder */ + decode_RV32_64G(ctx); + } } }