From 611933d18d9c15908453a52d9e6053694256cc65 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Sun, 11 Feb 2018 16:17:19 -0500 Subject: [PATCH] target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP Fix microMIPS MOVE16 and MOVEP instructions on 64-bit processors by using register addition operations. This copies the approach taken with MIPS16 MOVE instructions (I8_MOV32R and I8_MOVR32 opcodes) and follows the observation that OPC_ADDU expands to tcg_gen_mov_tl whenever `rt' is 0 and `rs' is not, therefore copying `rs' to `rd' verbatim. This is not the case with OPC_ADDIU where a sign-extension from bit #31 is made, unless in the uninteresting case of `rs' being 0, losing the upper 32 bits of the value copied for any proper 64-bit values. This also serves as an optimization as one op is produced in generated code rather than two (again, unless `rs' is 0, where it doesn't change anything). Backports commit 7215d7e7aea85699bf516c3e8d84f6a22584da35 from qemu --- qemu/target-mips/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qemu/target-mips/translate.c b/qemu/target-mips/translate.c index 59710758..6996b142 100644 --- a/qemu/target-mips/translate.c +++ b/qemu/target-mips/translate.c @@ -14058,8 +14058,8 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, bool *ins rs = rs_rt_enc[enc_rs]; rt = rs_rt_enc[enc_rt]; - gen_arith_imm(ctx, OPC_ADDIU, rd, rs, 0); - gen_arith_imm(ctx, OPC_ADDIU, re, rt, 0); + gen_arith(ctx, OPC_ADDU, rd, rs, 0); + gen_arith(ctx, OPC_ADDU, re, rt, 0); } break; case LBU16: @@ -14140,7 +14140,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, bool *ins int rd = uMIPS_RD5(ctx->opcode); int rs = uMIPS_RS5(ctx->opcode); - gen_arith_imm(ctx, OPC_ADDIU, rd, rs, 0); + gen_arith(ctx, OPC_ADDU, rd, rs, 0); } break; case ANDI16: