diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c
index 4de20d6e..72247650 100644
--- a/qemu/target/arm/cpu.c
+++ b/qemu/target/arm/cpu.c
@@ -1025,6 +1025,7 @@ static void cortex_m3_initfn(struct uc_struct *uc, Object *obj, void *opaque)
     cpu->id_isar3 = 0x01111110;
     cpu->id_isar4 = 0x01310102;
     cpu->id_isar5 = 0x00000000;
+    cpu->id_isar6 = 0x00000000;
 }
 
 static void cortex_m4_initfn(struct uc_struct *uc, Object *obj, void *opaque)
@@ -1051,6 +1052,7 @@ static void cortex_m4_initfn(struct uc_struct *uc, Object *obj, void *opaque)
     cpu->id_isar3 = 0x01111110;
     cpu->id_isar4 = 0x01310102;
     cpu->id_isar5 = 0x00000000;
+    cpu->id_isar6 = 0x00000000;
 }
 
 static void cortex_m33_initfn(struct uc_struct *uc, Object *obj, void *opaque)
@@ -1079,6 +1081,7 @@ static void cortex_m33_initfn(struct uc_struct *uc, Object *obj, void *opaque)
     cpu->id_isar3 = 0x01111131;
     cpu->id_isar4 = 0x01310132;
     cpu->id_isar5 = 0x00000000;
+    cpu->id_isar6 = 0x00000000;
     cpu->clidr = 0x00000000;
     cpu->ctr = 0x8000c000;
 }
@@ -1126,6 +1129,7 @@ static void cortex_r5_initfn(struct uc_struct *uc, Object *obj, void *opaque)
     cpu->id_isar3 = 0x01112131;
     cpu->id_isar4 = 0x0010142;
     cpu->id_isar5 = 0x0;
+    cpu->id_isar6 = 0x0;
     cpu->mp_is_up = true;
     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 }
diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h
index 7d4f7b87..87dc5bcb 100644
--- a/qemu/target/arm/cpu.h
+++ b/qemu/target/arm/cpu.h
@@ -791,6 +791,7 @@ typedef struct ARMCPU {
     uint32_t id_isar3;
     uint32_t id_isar4;
     uint32_t id_isar5;
+    uint32_t id_isar6;
     uint64_t id_aa64pfr0;
     uint64_t id_aa64pfr1;
     uint64_t id_aa64dfr0;
diff --git a/qemu/target/arm/cpu64.c b/qemu/target/arm/cpu64.c
index 5c6efe38..9d8a3c74 100644
--- a/qemu/target/arm/cpu64.c
+++ b/qemu/target/arm/cpu64.c
@@ -120,6 +120,7 @@ static void aarch64_a57_initfn(struct uc_struct *uc, Object *obj, void *opaque)
     cpu->id_isar3 = 0x01112131;
     cpu->id_isar4 = 0x00011142;
     cpu->id_isar5 = 0x00011121;
+    cpu->id_isar6 = 0;
     cpu->id_aa64pfr0 = 0x00002222;
     cpu->id_aa64dfr0 = 0x10305106;
     cpu->pmceid0 = 0x00000000;
@@ -177,6 +178,7 @@ static void aarch64_a53_initfn(struct uc_struct *uc, Object *obj, void *opaque)
     cpu->id_isar3 = 0x01112131;
     cpu->id_isar4 = 0x00011142;
     cpu->id_isar5 = 0x00011121;
+    cpu->id_isar6 = 0;
     cpu->id_aa64pfr0 = 0x00002222;
     cpu->id_aa64dfr0 = 0x10305106;
     cpu->id_aa64isar0 = 0x00011120;
diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c
index 5e353088..3607867c 100644
--- a/qemu/target/arm/helper.c
+++ b/qemu/target/arm/helper.c
@@ -4264,11 +4264,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
               ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar4 },
             { "ID_ISAR5", 0,0,2, 3,0,5, ARM_CP_STATE_BOTH,
               ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar5 },
-            /* 6..7 are as yet unallocated and must RAZ */
-            { "ID_ISAR6", 15,0,2, 0,0,6, 0,
-              ARM_CP_CONST, PL1_R, 0, NULL, 0 },
-            { "ID_ISAR7", 15,0,2, 0,0,7, 0,
-              ARM_CP_CONST, PL1_R, 0, NULL, 0 },
+            { "ID_MMFR4", 0,0,2, 3,0,6, ARM_CP_STATE_BOTH, ARM_CP_CONST,
+              PL1_R, 0, NULL, cpu->id_mmfr4 },
+            { "ID_ISAR6", 0,0,2, 3,0,7, 0,
+              ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar6 },
             REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, v6_idregs);