From 614ecb2bf254e699f3ab0b3bafc06c85708e5769 Mon Sep 17 00:00:00 2001 From: Sergey Fedorov Date: Tue, 13 Feb 2018 14:27:51 -0500 Subject: [PATCH] target-arm: add AArch32 MIDR aliases in ARMv8 According to ARMv8 ARM, there are additional aliases to MIDR system register in AArch32 state. So add them to the list. Backports commit ac00c79ff6635ae9fd732ff357ada0d05e795500 from qemu --- qemu/target-arm/helper.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index e15bdcc4..d0af7a25 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -2937,11 +2937,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) REGINFO_SENTINEL }; ARMCPRegInfo id_v8_midr_cp_reginfo[] = { - /* v8 MIDR -- the wildcard isn't necessary, and nor is the - * variable-MIDR TI925 behaviour. - */ { "MIDR_EL1", 0,0,0, 3,0,0, ARM_CP_STATE_BOTH, ARM_CP_CONST, PL1_R, 0, NULL, cpu->midr }, + /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ + { "MIDR", 15,0,0, 0,0,4, 0, ARM_CP_ALIAS | ARM_CP_CONST, + PL1_R, 0, NULL, cpu->midr }, + { "MIDR", 15,0,0, 0,0,7, 0, ARM_CP_ALIAS | ARM_CP_CONST, + PL1_R, 0, NULL, cpu->midr }, { "REVIDR_EL1", 0,0,0, 3,0,6, ARM_CP_STATE_BOTH, ARM_CP_CONST, PL1_R, 0, NULL, cpu->revidr }, REGINFO_SENTINEL