From 6234d074890dd9430d25c979042e6c3b14c49c25 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 10 Feb 2018 19:01:17 -0500 Subject: [PATCH] tcg: Merge memop and mmu_idx parameters to qemu_ld/st At the tcg opcode level, not at the tcg-op.h generator level. This requires minor changes through all of the tcg backends, but none of the cpu translators. Backports commit 59227d5d45bb3c31dc2118011691c35b3c00879c from qemu --- qemu/tcg/aarch64/tcg-target.c | 12 +++++++---- qemu/tcg/arm/tcg-target.c | 12 +++++++---- qemu/tcg/i386/tcg-target.c | 12 +++++++---- qemu/tcg/mips/tcg-target.c | 12 +++++++---- qemu/tcg/optimize.c | 3 ++- qemu/tcg/ppc/tcg-target.c | 12 +++++++---- qemu/tcg/s390/tcg-target.c | 12 +++++++---- qemu/tcg/sparc/tcg-target.c | 14 ++++++++----- qemu/tcg/tcg-op.c | 22 +++++++++----------- qemu/tcg/tcg-opc.h | 8 ++++---- qemu/tcg/tcg.c | 16 ++++++++++----- qemu/tcg/tcg.h | 38 +++++++++++++++++++++++++++++++++++ 12 files changed, 122 insertions(+), 51 deletions(-) diff --git a/qemu/tcg/aarch64/tcg-target.c b/qemu/tcg/aarch64/tcg-target.c index bf2573ce..8d247e22 100644 --- a/qemu/tcg/aarch64/tcg-target.c +++ b/qemu/tcg/aarch64/tcg-target.c @@ -1197,9 +1197,11 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop, } static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, - TCGMemOp memop, TCGType ext, int mem_index) + TCGMemOpIdx oi, TCGType ext) { + TCGMemOp memop = get_memop(oi); #ifdef CONFIG_SOFTMMU + unsigned mem_index = get_mmuidx(oi); TCGMemOp s_bits = memop & MO_SIZE; tcg_insn_unit *label_ptr; @@ -1214,9 +1216,11 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, } static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, - TCGMemOp memop, int mem_index) + TCGMemOpIdx oi) { + TCGMemOp memop = get_memop(oi); #ifdef CONFIG_SOFTMMU + unsigned mem_index = get_mmuidx(oi); TCGMemOp s_bits = memop & MO_SIZE; tcg_insn_unit *label_ptr; @@ -1515,11 +1519,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, a0, a1, a2, ext, args[3]); + tcg_out_qemu_ld(s, a0, a1, a2, ext); break; case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, REG0(0), a1, a2, args[3]); + tcg_out_qemu_st(s, REG0(0), a1, a2); break; case INDEX_op_bswap64_i64: diff --git a/qemu/tcg/arm/tcg-target.c b/qemu/tcg/arm/tcg-target.c index 366b6f43..d9aa4b53 100644 --- a/qemu/tcg/arm/tcg-target.c +++ b/qemu/tcg/arm/tcg-target.c @@ -1463,6 +1463,7 @@ static inline void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) { TCGReg addrlo, datalo, datahi, addrhi QEMU_UNUSED_VAR; + TCGMemOpIdx oi; TCGMemOp opc; #ifdef CONFIG_SOFTMMU int mem_index; @@ -1474,10 +1475,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) datahi = (is64 ? *args++ : 0); addrlo = *args++; addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0); - opc = *args++; + oi = *args++; + opc = get_memop(oi); #ifdef CONFIG_SOFTMMU - mem_index = *args; + mem_index = get_mmuidx(oi); addend = tcg_out_tlb_read(s, addrlo, addrhi, opc & MO_SIZE, mem_index, 1); /* This a conditional BL only to load a pointer within this opcode into LR @@ -1592,6 +1594,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) { TCGReg addrlo, datalo, datahi, addrhi QEMU_UNUSED_VAR; + TCGMemOpIdx oi; TCGMemOp opc; #ifdef CONFIG_SOFTMMU int mem_index; @@ -1603,10 +1606,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) datahi = (is64 ? *args++ : 0); addrlo = *args++; addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0); - opc = *args++; + oi = *args++; + opc = get_memop(oi); #ifdef CONFIG_SOFTMMU - mem_index = *args; + mem_index = get_mmuidx(oi); addend = tcg_out_tlb_read(s, addrlo, addrhi, opc & MO_SIZE, mem_index, 0); tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend); diff --git a/qemu/tcg/i386/tcg-target.c b/qemu/tcg/i386/tcg-target.c index 7e49ff96..ababfdcf 100644 --- a/qemu/tcg/i386/tcg-target.c +++ b/qemu/tcg/i386/tcg-target.c @@ -1634,6 +1634,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) { TCGReg datalo, datahi, addrlo; TCGReg addrhi QEMU_UNUSED_VAR; + TCGMemOpIdx oi; TCGMemOp opc; #if defined(CONFIG_SOFTMMU) int mem_index; @@ -1645,10 +1646,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); addrlo = *args++; addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); - opc = *args++; + oi = *args++; + opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - mem_index = *args++; + mem_index = get_mmuidx(oi); s_bits = opc & MO_SIZE; tcg_out_tlb_load(s, addrlo, addrhi, mem_index, s_bits, @@ -1765,6 +1767,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) { TCGReg datalo, datahi, addrlo; TCGReg addrhi QEMU_UNUSED_VAR; + TCGMemOpIdx oi; TCGMemOp opc; #if defined(CONFIG_SOFTMMU) int mem_index; @@ -1776,10 +1779,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); addrlo = *args++; addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); - opc = *args++; + oi = *args++; + opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - mem_index = *args++; + mem_index = get_mmuidx(oi); s_bits = opc & MO_SIZE; tcg_out_tlb_load(s, addrlo, addrhi, mem_index, s_bits, diff --git a/qemu/tcg/mips/tcg-target.c b/qemu/tcg/mips/tcg-target.c index 3ebfa049..bcc3ddcf 100644 --- a/qemu/tcg/mips/tcg-target.c +++ b/qemu/tcg/mips/tcg-target.c @@ -1150,6 +1150,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) { TCGReg addr_regl, addr_regh QEMU_UNUSED_VAR; TCGReg data_regl, data_regh; + TCGMemOpIdx oi; TCGMemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; @@ -1164,10 +1165,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) data_regh = (is_64 ? *args++ : 0); addr_regl = *args++; addr_regh = (TARGET_LONG_BITS == 64 ? *args++ : 0); - opc = *args++; + oi = *args++; + opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - mem_index = *args; + mem_index = get_mmuidx(oi); s_bits = opc & MO_SIZE; tcg_out_tlb_load(s, base, addr_regl, addr_regh, mem_index, @@ -1279,6 +1281,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) { TCGReg addr_regl, addr_regh QEMU_UNUSED_VAR; TCGReg data_regl, data_regh, base; + TCGMemOpIdx oi; TCGMemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; @@ -1290,10 +1293,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) data_regh = (is_64 ? *args++ : 0); addr_regl = *args++; addr_regh = (TARGET_LONG_BITS == 64 ? *args++ : 0); - opc = *args++; + oi = *args++; + opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - mem_index = *args; + mem_index = get_mmuidx(oi); s_bits = opc & 3; /* Note that we eliminated the helper's address argument, diff --git a/qemu/tcg/optimize.c b/qemu/tcg/optimize.c index 2222f641..5054b76c 100644 --- a/qemu/tcg/optimize.c +++ b/qemu/tcg/optimize.c @@ -920,7 +920,8 @@ static void tcg_constant_folding(TCGContext *s) CASE_OP_32_64(qemu_ld): { - TCGMemOp mop = args[nb_oargs + nb_iargs]; + TCGMemOpIdx oi = args[nb_oargs + nb_iargs]; + TCGMemOp mop = get_memop(oi); if (!(mop & MO_SIGN)) { mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1; } diff --git a/qemu/tcg/ppc/tcg-target.c b/qemu/tcg/ppc/tcg-target.c index b2b79ba1..8a55ea0f 100644 --- a/qemu/tcg/ppc/tcg-target.c +++ b/qemu/tcg/ppc/tcg-target.c @@ -1575,6 +1575,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) { TCGReg datalo, datahi, addrlo, rbase; TCGReg addrhi QEMU_UNUSED_VAR; + TCGMemOpIdx oi; TCGMemOp opc, s_bits; #ifdef CONFIG_SOFTMMU int mem_index; @@ -1585,11 +1586,12 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); addrlo = *args++; addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - opc = *args++; + oi = *args++; + opc = get_memop(oi); s_bits = opc & MO_SIZE; #ifdef CONFIG_SOFTMMU - mem_index = *args; + mem_index = get_mmuidx(oi); addrlo = tcg_out_tlb_read(s, s_bits, addrlo, addrhi, mem_index, true); /* Load a pointer into the current opcode w/conditional branch-link. */ @@ -1648,6 +1650,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) { TCGReg datalo, datahi, addrlo, rbase; TCGReg addrhi QEMU_UNUSED_VAR; + TCGMemOpIdx oi; TCGMemOp opc, s_bits; #ifdef CONFIG_SOFTMMU int mem_index; @@ -1658,11 +1661,12 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); addrlo = *args++; addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - opc = *args++; + oi = *args++; + opc = get_memop(oi); s_bits = opc & MO_SIZE; #ifdef CONFIG_SOFTMMU - mem_index = *args; + mem_index = get_mmuidx(oi); addrlo = tcg_out_tlb_read(s, s_bits, addrlo, addrhi, mem_index, false); /* Load a pointer into the current opcode w/conditional branch-link. */ diff --git a/qemu/tcg/s390/tcg-target.c b/qemu/tcg/s390/tcg-target.c index 9e0ab2a6..68761f40 100644 --- a/qemu/tcg/s390/tcg-target.c +++ b/qemu/tcg/s390/tcg-target.c @@ -1632,9 +1632,11 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg, #endif /* CONFIG_SOFTMMU */ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, - TCGMemOp opc, int mem_index) + TCGMemOpIdx oi) { + TCGMemOp opc = get_memop(oi); #ifdef CONFIG_SOFTMMU + unsigned mem_index = get_mmuidx(oi); tcg_insn_unit *label_ptr; TCGReg base_reg; @@ -1657,9 +1659,11 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, } static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, - TCGMemOp opc, int mem_index) + TCGMemOpIdx oi) { + TCGMemOp opc = get_memop(oi); #ifdef CONFIG_SOFTMMU + unsigned mem_index = get_mmuidx(oi); tcg_insn_unit *label_ptr; TCGReg base_reg; @@ -1920,11 +1924,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_qemu_ld_i32: /* ??? Technically we can use a non-extending instruction. */ case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3]); + tcg_out_qemu_ld(s, args[0], args[1], args[2]); break; case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args[0], args[1], args[2], args[3]); + tcg_out_qemu_st(s, args[0], args[1], args[2]); break; case INDEX_op_ld16s_i64: diff --git a/qemu/tcg/sparc/tcg-target.c b/qemu/tcg/sparc/tcg-target.c index 27f819c1..d8329c94 100644 --- a/qemu/tcg/sparc/tcg-target.c +++ b/qemu/tcg/sparc/tcg-target.c @@ -1070,9 +1070,11 @@ static const int qemu_st_opc[16] = { }; static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, - TCGMemOp memop, int memi, bool is_64) + TCGMemOpIdx oi, bool is_64) { + TCGMemOp memop = get_memop(oi); #ifdef CONFIG_SOFTMMU + unsigned memi = get_mmuidx(oi); TCGMemOp s_bits = memop & MO_SIZE; TCGReg addrz, param; tcg_insn_unit *func; @@ -1150,9 +1152,11 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, } static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, - TCGMemOp memop, int memi) + TCGMemOpIdx oi) { + TCGMemOp memop = get_memop(oi); #ifdef CONFIG_SOFTMMU + unsigned memi = get_mmuidx(oi); TCGMemOp s_bits = memop & MO_SIZE; TCGReg addrz, param; tcg_insn_unit *func; @@ -1363,14 +1367,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, a0, a1, a2, args[3], false); + tcg_out_qemu_ld(s, a0, a1, a2, false); break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, a0, a1, a2, args[3], true); + tcg_out_qemu_ld(s, a0, a1, a2, true); break; case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, a0, a1, a2, args[3]); + tcg_out_qemu_st(s, a0, a1, a2); break; case INDEX_op_ld32s_i64: diff --git a/qemu/tcg/tcg-op.c b/qemu/tcg/tcg-op.c index 8d458422..05beeb18 100644 --- a/qemu/tcg/tcg-op.c +++ b/qemu/tcg/tcg-op.c @@ -1874,15 +1874,14 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st) static void gen_ldst_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 val, TCGv addr, TCGMemOp memop, TCGArg idx) { + TCGMemOpIdx oi = make_memop_idx(memop, idx); #if TARGET_LONG_BITS == 32 - tcg_gen_op4ii_i32(s, opc, val, addr, memop, idx); + tcg_gen_op3i_i32(s, opc, val, addr, oi); #else if (TCG_TARGET_REG_BITS == 32) { - tcg_gen_op5ii_i32(s, opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), - memop, idx); + tcg_gen_op4i_i32(s, opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi); } else { - tcg_gen_op4(s, opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), - memop, idx); + tcg_gen_op3(s, opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), oi); } #endif } @@ -1890,20 +1889,19 @@ static void gen_ldst_i32(TCGContext *s, TCGOpcode opc, TCGv_i32 val, TCGv addr, static void gen_ldst_i64(TCGContext *s, TCGOpcode opc, TCGv_i64 val, TCGv addr, TCGMemOp memop, TCGArg idx) { + TCGMemOpIdx oi = make_memop_idx(memop, idx); #if TARGET_LONG_BITS == 32 if (TCG_TARGET_REG_BITS == 32) { - tcg_gen_op5ii_i32(s, opc, TCGV_LOW(val), TCGV_HIGH(val), - addr, memop, idx); + tcg_gen_op4i_i32(s, opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi); } else { - tcg_gen_op4(s, opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), - memop, idx); + tcg_gen_op3(s, opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), oi); } #else if (TCG_TARGET_REG_BITS == 32) { - tcg_gen_op6ii_i32(s, opc, TCGV_LOW(val), TCGV_HIGH(val), - TCGV_LOW(addr), TCGV_HIGH(addr), memop, idx); + tcg_gen_op5i_i32(s, opc, TCGV_LOW(val), TCGV_HIGH(val), + TCGV_LOW(addr), TCGV_HIGH(addr), oi); } else { - tcg_gen_op4ii_i64(s, opc, val, addr, memop, idx); + tcg_gen_op3i_i64(s, opc, val, addr, oi); } #endif } diff --git a/qemu/tcg/tcg-opc.h b/qemu/tcg/tcg-opc.h index cfc8dd22..66bc0fc5 100644 --- a/qemu/tcg/tcg-opc.h +++ b/qemu/tcg/tcg-opc.h @@ -184,13 +184,13 @@ DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END) #define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2) #define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2) -DEF(qemu_ld_i32, 1, TLADDR_ARGS, 2, +DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) -DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 2, +DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) -DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 2, +DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) -DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 2, +DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) #undef TLADDR_ARGS diff --git a/qemu/tcg/tcg.c b/qemu/tcg/tcg.c index c3e8b353..d2fc8a99 100644 --- a/qemu/tcg/tcg.c +++ b/qemu/tcg/tcg.c @@ -1109,12 +1109,18 @@ void tcg_dump_ops(TCGContext *s) case INDEX_op_qemu_st_i32: case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: - if (args[k] < ARRAY_SIZE(ldst_name) && ldst_name[args[k]]) { - printf(",%s", ldst_name[args[k++]]); - } else { - printf(",$0x%" TCG_PRIlx, args[k++]); + { + TCGMemOpIdx oi = args[k++]; + TCGMemOp op = get_memop(oi); + unsigned ix = get_mmuidx(oi); + + if (op < ARRAY_SIZE(ldst_name) && ldst_name[op]) { + printf(",%s,%u", ldst_name[op], ix); + } else { + printf(",$0x%x,%u", op, ix); + } + i = 1; } - i = 1; break; default: i = 0; diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h index 0f3af973..54c32829 100644 --- a/qemu/tcg/tcg.h +++ b/qemu/tcg/tcg.h @@ -961,6 +961,44 @@ static inline size_t tcg_current_code_size(TCGContext *s) return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); } +/* Combine the TCGMemOp and mmu_idx parameters into a single value. */ +typedef uint32_t TCGMemOpIdx; + +/** + * make_memop_idx + * @op: memory operation + * @idx: mmu index + * + * Encode these values into a single parameter. + */ +static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx) +{ + tcg_debug_assert(idx <= 15); + return (op << 4) | idx; +} + +/** + * get_memop + * @oi: combined op/idx parameter + * + * Extract the memory operation from the combined value. + */ +static inline TCGMemOp get_memop(TCGMemOpIdx oi) +{ + return oi >> 4; +} + +/** + * get_mmuidx + * @oi: combined op/idx parameter + * + * Extract the mmu index from the combined value. + */ +static inline unsigned get_mmuidx(TCGMemOpIdx oi) +{ + return oi & 15; +} + /** * tcg_qemu_tb_exec: * @env: CPUArchState * for the CPU