From 63dad98564097da811d08ef7c6f92f2824d6e8fd Mon Sep 17 00:00:00 2001 From: Miodrag Dinic Date: Mon, 19 Feb 2018 00:42:02 -0500 Subject: [PATCH] target-mips: Fix ALIGN instruction when bp=0 If executing ALIGN with shift count bp=0 within mips64 emulation, the result of the operation should be sign extended. Taken from the official documentation (pseudo code) : ALIGN: tmp_rt_hi = unsigned_word(GPR[rt]) << (8*bp) tmp_rs_lo = unsigned_word(GPR[rs]) >> (8*(4-bp)) tmp = tmp_rt_hi || tmp_rt_lo GPR[rd] = sign_extend.32(tmp) Backports commit 51243852af322f0a1103a90c936c43db84def82f from qemu --- qemu/target-mips/translate.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/qemu/target-mips/translate.c b/qemu/target-mips/translate.c index 17e57955..d8253e94 100644 --- a/qemu/target-mips/translate.c +++ b/qemu/target-mips/translate.c @@ -4696,7 +4696,16 @@ static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt, t0 = tcg_temp_new(tcg_ctx); gen_load_gpr(ctx, t0, rt); if (bp == 0) { - tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], t0); + switch (opc) { + case OPC_ALIGN: + tcg_gen_ext32s_tl(tcg_ctx, *cpu_gpr[rd], t0); + break; +#if defined(TARGET_MIPS64) + case OPC_DALIGN: + tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], t0); + break; +#endif + } } else { TCGv t1 = tcg_temp_new(tcg_ctx); gen_load_gpr(ctx, t1, rs);