From 6482182ba576c814fbc78b9371854508458072bf Mon Sep 17 00:00:00 2001 From: Andrew Jones Date: Tue, 26 Mar 2019 20:33:50 -0400 Subject: [PATCH] target/arm: cortex-a7 and cortex-a15 have pmus cortex-a7 and cortex-a15 have pmus (PMUv2) and they advertise them in ID_DFR0. Let's allow them to function. This also enables the pmu cpu property to work with these cpu types, i.e. we can now do '-cpu cortex-a15,pmu=off' to remove the pmu. Backports commit a46118fc16537a593119e5b316052a98514046bb from qemu --- qemu/target/arm/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index 357897c2..2d2bd008 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -801,6 +801,7 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); } else { cpu->id_aa64dfr0 &= ~0xf00; + cpu->id_dfr0 &= ~(0xf << 24); cpu->pmceid0 = 0; cpu->pmceid1 = 0; } @@ -1433,6 +1434,7 @@ static void cortex_a7_initfn(struct uc_struct *uc, Object *obj, void *opaque) set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; cpu->midr = 0x410fc075; cpu->reset_fpsid = 0x41023075; @@ -1478,6 +1480,7 @@ static void cortex_a15_initfn(struct uc_struct *uc, Object *obj, void *opaque) set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1; cpu->reset_fpsid = 0x410430f0;