From 65a78ebb26ca09281d66a8e021d04fa374d211c2 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 20 Feb 2018 10:51:01 -0500 Subject: [PATCH] target-i386: Deconstruct the cpu_T array All references to cpu_T are done with a constant index. It aids readability to decompose the array into two scalar variables. Backports commit 1d1cc4d0f481b2939c7e9f6606e571b2fc81971a from qemu --- qemu/target-i386/translate.c | 1318 +++++++++++++++++----------------- qemu/target-i386/unicorn.c | 4 +- qemu/tcg/tcg.h | 3 +- 3 files changed, 669 insertions(+), 656 deletions(-) diff --git a/qemu/target-i386/translate.c b/qemu/target-i386/translate.c index 8a07d88d..36c40122 100644 --- a/qemu/target-i386/translate.c +++ b/qemu/target-i386/translate.c @@ -469,10 +469,10 @@ static inline void gen_op_add_reg_im(TCGContext *s, TCGMemOp size, int reg, int3 static inline void gen_op_add_reg_T0(TCGContext *s, TCGMemOp size, int reg) { TCGv cpu_tmp0 = *(TCGv *)s->cpu_tmp0; - TCGv **cpu_T = (TCGv **)s->cpu_T; + TCGv cpu_T0 = *(TCGv *)s->cpu_T0; TCGv **cpu_regs = (TCGv **)s->cpu_regs; - tcg_gen_add_tl(s, cpu_tmp0, *cpu_regs[reg], *cpu_T[0]); + tcg_gen_add_tl(s, cpu_tmp0, *cpu_regs[reg], cpu_T0); gen_op_mov_reg_v(s, size, reg, cpu_tmp0); } @@ -494,12 +494,12 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d) { TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; if (d == OR_TMP0) { - gen_op_st_v(s, idx, *cpu_T[0], cpu_A0); + gen_op_st_v(s, idx, cpu_T0, cpu_A0); } else { - gen_op_mov_reg_v(tcg_ctx, idx, d, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, idx, d, cpu_T0); } } @@ -591,10 +591,10 @@ static inline void gen_string_movl_A0_EDI(DisasContext *s) static inline void gen_op_movl_T0_Dshift(TCGContext *s, TCGMemOp ot) { - TCGv **cpu_T = (TCGv **)s->cpu_T; + TCGv cpu_T0 = *(TCGv *)s->cpu_T0; - tcg_gen_ld32s_tl(s, *cpu_T[0], s->cpu_env, offsetof(CPUX86State, df)); - tcg_gen_shli_tl(s, *cpu_T[0], *cpu_T[0], ot); + tcg_gen_ld32s_tl(s, cpu_T0, s->cpu_env, offsetof(CPUX86State, df)); + tcg_gen_shli_tl(s, cpu_T0, cpu_T0, ot); }; static TCGv gen_ext_tl(TCGContext *s, TCGv dst, TCGv src, TCGMemOp size, bool sign) @@ -698,13 +698,13 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip, target_ulong next_eip; TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 cpu_tmp2_i32 = tcg_ctx->cpu_tmp2_i32; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; // Unicorn: allow all I/O instructions return; if (s->pe && (s->cpl > s->iopl || s->vm86)) { - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); switch (ot) { case MO_8: gen_helper_check_iob(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp2_i32); @@ -724,7 +724,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip, gen_jmp_im(s, cur_eip); svm_flags |= (1 << (4 + ot)); next_eip = s->pc - s->cs_base; - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); gen_helper_svm_check_io(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp2_i32, tcg_const_i32(tcg_ctx, svm_flags), tcg_const_i32(tcg_ctx, next_eip - cur_eip)); @@ -735,12 +735,12 @@ static inline void gen_movs(DisasContext *s, TCGMemOp ot) { TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; gen_string_movl_A0_ESI(s); - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); gen_string_movl_A0_EDI(s); - gen_op_st_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_st_v(s, ot, cpu_T0, cpu_A0); gen_op_movl_T0_Dshift(tcg_ctx, ot); gen_op_add_reg_T0(tcg_ctx, s->aflag, R_ESI); gen_op_add_reg_T0(tcg_ctx, s->aflag, R_EDI); @@ -749,19 +749,20 @@ static inline void gen_movs(DisasContext *s, TCGMemOp ot) static void gen_op_update1_cc(TCGContext *s) { TCGv cpu_cc_dst = *(TCGv *)s->cpu_cc_dst; - TCGv **cpu_T = (TCGv **)s->cpu_T; + TCGv cpu_T0 = *(TCGv *)s->cpu_T0; - tcg_gen_mov_tl(s, cpu_cc_dst, *cpu_T[0]); + tcg_gen_mov_tl(s, cpu_cc_dst, cpu_T0); } static void gen_op_update2_cc(TCGContext *s) { TCGv cpu_cc_dst = *(TCGv *)s->cpu_cc_dst; TCGv cpu_cc_src = *(TCGv *)s->cpu_cc_src; - TCGv **cpu_T = (TCGv **)s->cpu_T; + TCGv cpu_T0 = *(TCGv *)s->cpu_T0; + TCGv cpu_T1 = *(TCGv *)s->cpu_T1; - tcg_gen_mov_tl(s, cpu_cc_src, *cpu_T[1]); - tcg_gen_mov_tl(s, cpu_cc_dst, *cpu_T[0]); + tcg_gen_mov_tl(s, cpu_cc_src, cpu_T1); + tcg_gen_mov_tl(s, cpu_cc_dst, cpu_T0); } static void gen_op_update3_cc(TCGContext *s, TCGv reg) @@ -769,19 +770,21 @@ static void gen_op_update3_cc(TCGContext *s, TCGv reg) TCGv cpu_cc_dst = *(TCGv *)s->cpu_cc_dst; TCGv cpu_cc_src = *(TCGv *)s->cpu_cc_src; TCGv cpu_cc_src2 = *(TCGv *)s->cpu_cc_src2; - TCGv **cpu_T = (TCGv **)s->cpu_T; + TCGv cpu_T0 = *(TCGv *)s->cpu_T0; + TCGv cpu_T1 = *(TCGv *)s->cpu_T1; tcg_gen_mov_tl(s, cpu_cc_src2, reg); - tcg_gen_mov_tl(s, cpu_cc_src, *cpu_T[1]); - tcg_gen_mov_tl(s, cpu_cc_dst, *cpu_T[0]); + tcg_gen_mov_tl(s, cpu_cc_src, cpu_T1); + tcg_gen_mov_tl(s, cpu_cc_dst, cpu_T0); } static inline void gen_op_testl_T0_T1_cc(TCGContext *s) { TCGv cpu_cc_dst = *(TCGv *)s->cpu_cc_dst; - TCGv **cpu_T = (TCGv **)s->cpu_T; + TCGv cpu_T0 = *(TCGv *)s->cpu_T0; + TCGv cpu_T1 = *(TCGv *)s->cpu_T1; - tcg_gen_and_tl(s, cpu_cc_dst, *cpu_T[0], *cpu_T[1]); + tcg_gen_and_tl(s, cpu_cc_dst, cpu_T0, cpu_T1); } static void gen_op_update_neg_cc(TCGContext *s) @@ -789,10 +792,10 @@ static void gen_op_update_neg_cc(TCGContext *s) TCGv cpu_cc_dst = *(TCGv *)s->cpu_cc_dst; TCGv cpu_cc_src = *(TCGv *)s->cpu_cc_src; TCGv cpu_cc_srcT = *(TCGv *)s->cpu_cc_srcT; - TCGv **cpu_T = (TCGv **)s->cpu_T; + TCGv cpu_T0 = *(TCGv *)s->cpu_T0; - tcg_gen_mov_tl(s, cpu_cc_dst, *cpu_T[0]); - tcg_gen_neg_tl(s, cpu_cc_src, *cpu_T[0]); + tcg_gen_mov_tl(s, cpu_cc_dst, cpu_T0); + tcg_gen_neg_tl(s, cpu_cc_src, cpu_T0); tcg_gen_movi_tl(s, cpu_cc_srcT, 0); } @@ -1160,12 +1163,12 @@ static inline void gen_compute_eflags_c(DisasContext *s, TCGv reg) static inline void gen_jcc1_noeob(DisasContext *s, int b, TCGLabel *l1) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; - CCPrepare cc = gen_prepare_cc(s, b, *cpu_T[0]); + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; + CCPrepare cc = gen_prepare_cc(s, b, cpu_T0); if (cc.mask != -1) { - tcg_gen_andi_tl(tcg_ctx, *cpu_T[0], cc.reg, cc.mask); - cc.reg = *cpu_T[0]; + tcg_gen_andi_tl(tcg_ctx, cpu_T0, cc.reg, cc.mask); + cc.reg = cpu_T0; } if (cc.use_reg2) { tcg_gen_brcond_tl(tcg_ctx, cc.cond, cc.reg, cc.reg2, l1); @@ -1180,13 +1183,13 @@ static inline void gen_jcc1_noeob(DisasContext *s, int b, TCGLabel *l1) static inline void gen_jcc1(DisasContext *s, int b, TCGLabel *l1) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; - CCPrepare cc = gen_prepare_cc(s, b, *cpu_T[0]); + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; + CCPrepare cc = gen_prepare_cc(s, b, cpu_T0); gen_update_cc_op(s); if (cc.mask != -1) { - tcg_gen_andi_tl(tcg_ctx, *cpu_T[0], cc.reg, cc.mask); - cc.reg = *cpu_T[0]; + tcg_gen_andi_tl(tcg_ctx, cpu_T0, cc.reg, cc.mask); + cc.reg = cpu_T0; } set_cc_op(s, CC_OP_DYNAMIC); if (cc.use_reg2) { @@ -1215,11 +1218,11 @@ static inline void gen_stos(DisasContext *s, TCGMemOp ot) { TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; - gen_op_mov_v_reg(tcg_ctx, MO_32, *cpu_T[0], R_EAX); + gen_op_mov_v_reg(tcg_ctx, MO_32, cpu_T0, R_EAX); gen_string_movl_A0_EDI(s); - gen_op_st_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_st_v(s, ot, cpu_T0, cpu_A0); gen_op_movl_T0_Dshift(tcg_ctx, ot); gen_op_add_reg_T0(tcg_ctx, s->aflag, R_EDI); } @@ -1228,11 +1231,11 @@ static inline void gen_lods(DisasContext *s, TCGMemOp ot) { TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; gen_string_movl_A0_ESI(s); - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); - gen_op_mov_reg_v(tcg_ctx, ot, R_EAX, *cpu_T[0]); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); + gen_op_mov_reg_v(tcg_ctx, ot, R_EAX, cpu_T0); gen_op_movl_T0_Dshift(tcg_ctx, ot); gen_op_add_reg_T0(tcg_ctx, s->aflag, R_ESI); } @@ -1241,10 +1244,10 @@ static inline void gen_scas(DisasContext *s, TCGMemOp ot) { TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T1 = *(TCGv *)tcg_ctx->cpu_T1; gen_string_movl_A0_EDI(s); - gen_op_ld_v(s, ot, *cpu_T[1], cpu_A0); + gen_op_ld_v(s, ot, cpu_T1, cpu_A0); gen_op(s, OP_CMPL, ot, R_EAX); gen_op_movl_T0_Dshift(tcg_ctx, ot); gen_op_add_reg_T0(tcg_ctx, s->aflag, R_EDI); @@ -1254,10 +1257,10 @@ static inline void gen_cmps(DisasContext *s, TCGMemOp ot) { TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T1 = *(TCGv *)tcg_ctx->cpu_T1; gen_string_movl_A0_EDI(s); - gen_op_ld_v(s, ot, *cpu_T[1], cpu_A0); + gen_op_ld_v(s, ot, cpu_T1, cpu_A0); gen_string_movl_A0_ESI(s); gen_op(s, OP_CMPL, ot, OR_TMP0); gen_op_movl_T0_Dshift(tcg_ctx, ot); @@ -1284,18 +1287,18 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot) TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 cpu_tmp2_i32 = tcg_ctx->cpu_tmp2_i32; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; TCGv **cpu_regs = (TCGv **)tcg_ctx->cpu_regs; gen_string_movl_A0_EDI(s); /* Note: we must do this dummy write first to be restartable in case of page fault. */ - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], 0); - gen_op_st_v(s, ot, *cpu_T[0], cpu_A0); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, 0); + gen_op_st_v(s, ot, cpu_T0, cpu_A0); tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_regs[R_EDX]); tcg_gen_andi_i32(tcg_ctx, cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); - gen_helper_in_func(tcg_ctx, ot, *cpu_T[0], cpu_tmp2_i32); - gen_op_st_v(s, ot, *cpu_T[0], cpu_A0); + gen_helper_in_func(tcg_ctx, ot, cpu_T0, cpu_tmp2_i32); + gen_op_st_v(s, ot, cpu_T0, cpu_A0); gen_op_movl_T0_Dshift(tcg_ctx, ot); gen_op_add_reg_T0(tcg_ctx, s->aflag, R_EDI); gen_bpt_io(s, cpu_tmp2_i32, ot); @@ -1307,15 +1310,15 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot) TCGv_i32 cpu_tmp2_i32 = tcg_ctx->cpu_tmp2_i32; TCGv_i32 cpu_tmp3_i32 = tcg_ctx->cpu_tmp3_i32; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; TCGv **cpu_regs = (TCGv **)tcg_ctx->cpu_regs; gen_string_movl_A0_ESI(s); - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_regs[R_EDX]); tcg_gen_andi_i32(tcg_ctx, cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp3_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp3_i32, cpu_T0); gen_helper_out_func(tcg_ctx, ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_op_movl_T0_Dshift(tcg_ctx, ot); @@ -1432,66 +1435,67 @@ static void gen_op(DisasContext *s, int op, TCGMemOp ot, int d) TCGv cpu_cc_src = *(TCGv *)tcg_ctx->cpu_cc_src; TCGv cpu_cc_srcT = *(TCGv *)tcg_ctx->cpu_cc_srcT; TCGv cpu_tmp4 = *(TCGv *)tcg_ctx->cpu_tmp4; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; + TCGv cpu_T1 = *(TCGv *)tcg_ctx->cpu_T1; if (d != OR_TMP0) { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], d); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, d); } else { - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); } switch(op) { case OP_ADCL: gen_compute_eflags_c(s, cpu_tmp4); - tcg_gen_add_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); - tcg_gen_add_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], cpu_tmp4); + tcg_gen_add_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); + tcg_gen_add_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp4); gen_op_st_rm_T0_A0(s, ot, d); gen_op_update3_cc(tcg_ctx, cpu_tmp4); set_cc_op(s, CC_OP_ADCB + ot); break; case OP_SBBL: gen_compute_eflags_c(s, cpu_tmp4); - tcg_gen_sub_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); - tcg_gen_sub_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], cpu_tmp4); + tcg_gen_sub_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); + tcg_gen_sub_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp4); gen_op_st_rm_T0_A0(s, ot, d); gen_op_update3_cc(tcg_ctx, cpu_tmp4); set_cc_op(s, CC_OP_SBBB + ot); break; case OP_ADDL: - tcg_gen_add_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + tcg_gen_add_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); gen_op_st_rm_T0_A0(s, ot, d); gen_op_update2_cc(tcg_ctx); set_cc_op(s, CC_OP_ADDB + ot); break; case OP_SUBL: - tcg_gen_mov_tl(tcg_ctx, cpu_cc_srcT, *cpu_T[0]); - tcg_gen_sub_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_srcT, cpu_T0); + tcg_gen_sub_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); gen_op_st_rm_T0_A0(s, ot, d); gen_op_update2_cc(tcg_ctx); set_cc_op(s, CC_OP_SUBB + ot); break; default: case OP_ANDL: - tcg_gen_and_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + tcg_gen_and_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); gen_op_st_rm_T0_A0(s, ot, d); gen_op_update1_cc(tcg_ctx); set_cc_op(s, CC_OP_LOGICB + ot); break; case OP_ORL: - tcg_gen_or_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + tcg_gen_or_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); gen_op_st_rm_T0_A0(s, ot, d); gen_op_update1_cc(tcg_ctx); set_cc_op(s, CC_OP_LOGICB + ot); break; case OP_XORL: - tcg_gen_xor_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + tcg_gen_xor_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); gen_op_st_rm_T0_A0(s, ot, d); gen_op_update1_cc(tcg_ctx); set_cc_op(s, CC_OP_LOGICB + ot); break; case OP_CMPL: - tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, *cpu_T[1]); - tcg_gen_mov_tl(tcg_ctx, cpu_cc_srcT, *cpu_T[0]); - tcg_gen_sub_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0], *cpu_T[1]); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, cpu_T1); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_srcT, cpu_T0); + tcg_gen_sub_tl(tcg_ctx, cpu_cc_dst, cpu_T0, cpu_T1); set_cc_op(s, CC_OP_SUBB + ot); break; } @@ -1504,23 +1508,23 @@ static void gen_inc(DisasContext *s, TCGMemOp ot, int d, int c) TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; TCGv cpu_cc_dst = *(TCGv *)tcg_ctx->cpu_cc_dst; TCGv cpu_cc_src = *(TCGv *)tcg_ctx->cpu_cc_src; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; if (d != OR_TMP0) { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], d); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, d); } else { - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); } gen_compute_eflags_c(s, cpu_cc_src); if (c > 0) { - tcg_gen_addi_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], 1); + tcg_gen_addi_tl(tcg_ctx, cpu_T0, cpu_T0, 1); set_cc_op(s, CC_OP_INCB + ot); } else { - tcg_gen_addi_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], -1); + tcg_gen_addi_tl(tcg_ctx, cpu_T0, cpu_T0, -1); set_cc_op(s, CC_OP_DECB + ot); } gen_op_st_rm_T0_A0(s, ot, d); - tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0]); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, cpu_T0); } static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result, @@ -1581,37 +1585,38 @@ static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1, TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; TCGv cpu_tmp0 = *(TCGv *)tcg_ctx->cpu_tmp0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; + TCGv cpu_T1 = *(TCGv *)tcg_ctx->cpu_T1; /* load */ if (op1 == OR_TMP0) { - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); } else { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], op1); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, op1); } - tcg_gen_andi_tl(tcg_ctx, *cpu_T[1], *cpu_T[1], mask); - tcg_gen_subi_tl(tcg_ctx, cpu_tmp0, *cpu_T[1], 1); + tcg_gen_andi_tl(tcg_ctx, cpu_T1, cpu_T1, mask); + tcg_gen_subi_tl(tcg_ctx, cpu_tmp0, cpu_T1, 1); if (is_right) { if (is_arith) { - gen_exts(tcg_ctx, ot, *cpu_T[0]); - tcg_gen_sar_tl(tcg_ctx, cpu_tmp0, *cpu_T[0], cpu_tmp0); - tcg_gen_sar_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + gen_exts(tcg_ctx, ot, cpu_T0); + tcg_gen_sar_tl(tcg_ctx, cpu_tmp0, cpu_T0, cpu_tmp0); + tcg_gen_sar_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); } else { - gen_extu(tcg_ctx, ot, *cpu_T[0]); - tcg_gen_shr_tl(tcg_ctx, cpu_tmp0, *cpu_T[0], cpu_tmp0); - tcg_gen_shr_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + gen_extu(tcg_ctx, ot, cpu_T0); + tcg_gen_shr_tl(tcg_ctx, cpu_tmp0, cpu_T0, cpu_tmp0); + tcg_gen_shr_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); } } else { - tcg_gen_shl_tl(tcg_ctx, cpu_tmp0, *cpu_T[0], cpu_tmp0); - tcg_gen_shl_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + tcg_gen_shl_tl(tcg_ctx, cpu_tmp0, cpu_T0, cpu_tmp0); + tcg_gen_shl_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); } /* store */ gen_op_st_rm_T0_A0(s, ot, op1); - gen_shift_flags(s, ot, *cpu_T[0], cpu_tmp0, *cpu_T[1], is_right); + gen_shift_flags(s, ot, cpu_T0, cpu_tmp0, cpu_T1, is_right); } static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2, @@ -1623,29 +1628,29 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2, TCGv cpu_cc_dst = *(TCGv *)tcg_ctx->cpu_cc_dst; TCGv cpu_cc_src = *(TCGv *)tcg_ctx->cpu_cc_src; TCGv cpu_tmp4 = *(TCGv *)tcg_ctx->cpu_tmp4; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; /* load */ if (op1 == OR_TMP0) - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); else - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], op1); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, op1); op2 &= mask; if (op2 != 0) { if (is_right) { if (is_arith) { - gen_exts(tcg_ctx, ot, *cpu_T[0]); - tcg_gen_sari_tl(tcg_ctx, cpu_tmp4, *cpu_T[0], op2 - 1); - tcg_gen_sari_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], op2); + gen_exts(tcg_ctx, ot, cpu_T0); + tcg_gen_sari_tl(tcg_ctx, cpu_tmp4, cpu_T0, op2 - 1); + tcg_gen_sari_tl(tcg_ctx, cpu_T0, cpu_T0, op2); } else { - gen_extu(tcg_ctx, ot, *cpu_T[0]); - tcg_gen_shri_tl(tcg_ctx, cpu_tmp4, *cpu_T[0], op2 - 1); - tcg_gen_shri_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], op2); + gen_extu(tcg_ctx, ot, cpu_T0); + tcg_gen_shri_tl(tcg_ctx, cpu_tmp4, cpu_T0, op2 - 1); + tcg_gen_shri_tl(tcg_ctx, cpu_T0, cpu_T0, op2); } } else { - tcg_gen_shli_tl(tcg_ctx, cpu_tmp4, *cpu_T[0], op2 - 1); - tcg_gen_shli_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], op2); + tcg_gen_shli_tl(tcg_ctx, cpu_tmp4, cpu_T0, op2 - 1); + tcg_gen_shli_tl(tcg_ctx, cpu_T0, cpu_T0, op2); } } @@ -1655,7 +1660,7 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2, /* update eflags if non zero shift */ if (op2 != 0) { tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, cpu_tmp4); - tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0]); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, cpu_T0); set_cc_op(s, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot); } } @@ -1671,45 +1676,46 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right) TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; TCGv cpu_cc_dst = *(TCGv *)tcg_ctx->cpu_cc_dst; TCGv cpu_cc_src2 = *(TCGv *)tcg_ctx->cpu_cc_src2; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; + TCGv cpu_T1 = *(TCGv *)tcg_ctx->cpu_T1; /* load */ if (op1 == OR_TMP0) { - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); } else { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], op1); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, op1); } - tcg_gen_andi_tl(tcg_ctx, *cpu_T[1], *cpu_T[1], mask); + tcg_gen_andi_tl(tcg_ctx, cpu_T1, cpu_T1, mask); switch (ot) { case MO_8: /* Replicate the 8-bit input so that a 32-bit rotate works. */ - tcg_gen_ext8u_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); - tcg_gen_muli_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], 0x01010101); + tcg_gen_ext8u_tl(tcg_ctx, cpu_T0, cpu_T0); + tcg_gen_muli_tl(tcg_ctx, cpu_T0, cpu_T0, 0x01010101); goto do_long; case MO_16: /* Replicate the 16-bit input so that a 32-bit rotate works. */ - tcg_gen_deposit_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[0], 16, 16); + tcg_gen_deposit_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T0, 16, 16); goto do_long; do_long: #ifdef TARGET_X86_64 case MO_32: - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp3_i32, *cpu_T[1]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp3_i32, cpu_T1); if (is_right) { tcg_gen_rotr_i32(tcg_ctx, cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32); } else { tcg_gen_rotl_i32(tcg_ctx, cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32); } - tcg_gen_extu_i32_tl(tcg_ctx, *cpu_T[0], cpu_tmp2_i32); + tcg_gen_extu_i32_tl(tcg_ctx, cpu_T0, cpu_tmp2_i32); break; #endif default: if (is_right) { - tcg_gen_rotr_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + tcg_gen_rotr_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); } else { - tcg_gen_rotl_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + tcg_gen_rotl_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); } break; } @@ -1725,12 +1731,12 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right) since we've computed the flags into CC_SRC, these variables are currently dead. */ if (is_right) { - tcg_gen_shri_tl(tcg_ctx, cpu_cc_src2, *cpu_T[0], mask - 1); - tcg_gen_shri_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0], mask); + tcg_gen_shri_tl(tcg_ctx, cpu_cc_src2, cpu_T0, mask - 1); + tcg_gen_shri_tl(tcg_ctx, cpu_cc_dst, cpu_T0, mask); tcg_gen_andi_tl(tcg_ctx, cpu_cc_dst, cpu_cc_dst, 1); } else { - tcg_gen_shri_tl(tcg_ctx, cpu_cc_src2, *cpu_T[0], mask); - tcg_gen_andi_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0], 1); + tcg_gen_shri_tl(tcg_ctx, cpu_cc_src2, cpu_T0, mask); + tcg_gen_andi_tl(tcg_ctx, cpu_cc_dst, cpu_T0, 1); } tcg_gen_andi_tl(tcg_ctx, cpu_cc_src2, cpu_cc_src2, 1); tcg_gen_xor_tl(tcg_ctx, cpu_cc_src2, cpu_cc_src2, cpu_cc_dst); @@ -1741,7 +1747,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right) exactly as we computed above. */ t0 = tcg_const_i32(tcg_ctx, 0); t1 = tcg_temp_new_i32(tcg_ctx); - tcg_gen_trunc_tl_i32(tcg_ctx, t1, *cpu_T[1]); + tcg_gen_trunc_tl_i32(tcg_ctx, t1, cpu_T1); tcg_gen_movi_i32(tcg_ctx, cpu_tmp2_i32, CC_OP_ADCOX); tcg_gen_movi_i32(tcg_ctx, cpu_tmp3_i32, CC_OP_EFLAGS); tcg_gen_movcond_i32(tcg_ctx, TCG_COND_NE, cpu_cc_op, t1, t0, @@ -1763,7 +1769,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2, TCGv cpu_cc_dst = *(TCGv *)tcg_ctx->cpu_cc_dst; TCGv cpu_cc_src2 = *(TCGv *)tcg_ctx->cpu_cc_src2; TCGv cpu_tmp0 = *(TCGv *)tcg_ctx->cpu_tmp0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; #ifdef TARGET_X86_64 TCGv_i32 cpu_tmp2_i32 = tcg_ctx->cpu_tmp2_i32; @@ -1771,9 +1777,9 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2, /* load */ if (op1 == OR_TMP0) { - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); } else { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], op1); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, op1); } op2 &= mask; @@ -1781,20 +1787,20 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2, switch (ot) { #ifdef TARGET_X86_64 case MO_32: - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); if (is_right) { tcg_gen_rotri_i32(tcg_ctx, cpu_tmp2_i32, cpu_tmp2_i32, op2); } else { tcg_gen_rotli_i32(tcg_ctx, cpu_tmp2_i32, cpu_tmp2_i32, op2); } - tcg_gen_extu_i32_tl(tcg_ctx, *cpu_T[0], cpu_tmp2_i32); + tcg_gen_extu_i32_tl(tcg_ctx, cpu_T0, cpu_tmp2_i32); break; #endif default: if (is_right) { - tcg_gen_rotri_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], op2); + tcg_gen_rotri_tl(tcg_ctx, cpu_T0, cpu_T0, op2); } else { - tcg_gen_rotli_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], op2); + tcg_gen_rotli_tl(tcg_ctx, cpu_T0, cpu_T0, op2); } break; case MO_8: @@ -1807,10 +1813,10 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2, if (is_right) { shift = mask + 1 - shift; } - gen_extu(tcg_ctx, ot, *cpu_T[0]); - tcg_gen_shli_tl(tcg_ctx, cpu_tmp0, *cpu_T[0], shift); - tcg_gen_shri_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], mask + 1 - shift); - tcg_gen_or_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], cpu_tmp0); + gen_extu(tcg_ctx, ot, cpu_T0); + tcg_gen_shli_tl(tcg_ctx, cpu_tmp0, cpu_T0, shift); + tcg_gen_shri_tl(tcg_ctx, cpu_T0, cpu_T0, mask + 1 - shift); + tcg_gen_or_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp0); break; } } @@ -1827,12 +1833,12 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2, since we've computed the flags into CC_SRC, these variables are currently dead. */ if (is_right) { - tcg_gen_shri_tl(tcg_ctx, cpu_cc_src2, *cpu_T[0], mask - 1); - tcg_gen_shri_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0], mask); + tcg_gen_shri_tl(tcg_ctx, cpu_cc_src2, cpu_T0, mask - 1); + tcg_gen_shri_tl(tcg_ctx, cpu_cc_dst, cpu_T0, mask); tcg_gen_andi_tl(tcg_ctx, cpu_cc_dst, cpu_cc_dst, 1); } else { - tcg_gen_shri_tl(tcg_ctx, cpu_cc_src2, *cpu_T[0], mask); - tcg_gen_andi_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0], 1); + tcg_gen_shri_tl(tcg_ctx, cpu_cc_src2, cpu_T0, mask); + tcg_gen_andi_tl(tcg_ctx, cpu_cc_dst, cpu_T0, 1); } tcg_gen_andi_tl(tcg_ctx, cpu_cc_src2, cpu_cc_src2, 1); tcg_gen_xor_tl(tcg_ctx, cpu_cc_src2, cpu_cc_src2, cpu_cc_dst); @@ -1846,31 +1852,32 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1, { TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; + TCGv cpu_T1 = *(TCGv *)tcg_ctx->cpu_T1; gen_compute_eflags(s); assert(s->cc_op == CC_OP_EFLAGS); /* load */ if (op1 == OR_TMP0) - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); else - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], op1); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, op1); if (is_right) { switch (ot) { case MO_8: - gen_helper_rcrb(tcg_ctx, *cpu_T[0], tcg_ctx->cpu_env, *cpu_T[0], *cpu_T[1]); + gen_helper_rcrb(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1); break; case MO_16: - gen_helper_rcrw(tcg_ctx, *cpu_T[0], tcg_ctx->cpu_env, *cpu_T[0], *cpu_T[1]); + gen_helper_rcrw(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1); break; case MO_32: - gen_helper_rcrl(tcg_ctx, *cpu_T[0], tcg_ctx->cpu_env, *cpu_T[0], *cpu_T[1]); + gen_helper_rcrl(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1); break; #ifdef TARGET_X86_64 case MO_64: - gen_helper_rcrq(tcg_ctx, *cpu_T[0], tcg_ctx->cpu_env, *cpu_T[0], *cpu_T[1]); + gen_helper_rcrq(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1); break; #endif default: @@ -1879,17 +1886,17 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1, } else { switch (ot) { case MO_8: - gen_helper_rclb(tcg_ctx, *cpu_T[0], tcg_ctx->cpu_env, *cpu_T[0], *cpu_T[1]); + gen_helper_rclb(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1); break; case MO_16: - gen_helper_rclw(tcg_ctx, *cpu_T[0], tcg_ctx->cpu_env, *cpu_T[0], *cpu_T[1]); + gen_helper_rclw(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1); break; case MO_32: - gen_helper_rcll(tcg_ctx, *cpu_T[0], tcg_ctx->cpu_env, *cpu_T[0], *cpu_T[1]); + gen_helper_rcll(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1); break; #ifdef TARGET_X86_64 case MO_64: - gen_helper_rclq(tcg_ctx, *cpu_T[0], tcg_ctx->cpu_env, *cpu_T[0], *cpu_T[1]); + gen_helper_rclq(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1); break; #endif default: @@ -1910,13 +1917,14 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1, TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; TCGv cpu_tmp0 = *(TCGv *)tcg_ctx->cpu_tmp0; TCGv cpu_tmp4 = *(TCGv *)tcg_ctx->cpu_tmp4; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; + TCGv cpu_T1 = *(TCGv *)tcg_ctx->cpu_T1; /* load */ if (op1 == OR_TMP0) { - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); } else { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], op1); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, op1); } count = tcg_temp_new(tcg_ctx); @@ -1928,11 +1936,11 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1, This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A portion by constructing it as a 32-bit value. */ if (is_right) { - tcg_gen_deposit_tl(tcg_ctx, cpu_tmp0, *cpu_T[0], *cpu_T[1], 16, 16); - tcg_gen_mov_tl(tcg_ctx, *cpu_T[1], *cpu_T[0]); - tcg_gen_mov_tl(tcg_ctx, *cpu_T[0], cpu_tmp0); + tcg_gen_deposit_tl(tcg_ctx, cpu_tmp0, cpu_T0, cpu_T1, 16, 16); + tcg_gen_mov_tl(tcg_ctx, cpu_T1, cpu_T0); + tcg_gen_mov_tl(tcg_ctx, cpu_T0, cpu_tmp0); } else { - tcg_gen_deposit_tl(tcg_ctx, *cpu_T[1], *cpu_T[0], *cpu_T[1], 16, 16); + tcg_gen_deposit_tl(tcg_ctx, cpu_T1, cpu_T0, cpu_T1, 16, 16); } /* FALLTHRU */ #ifdef TARGET_X86_64 @@ -1940,60 +1948,60 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1, /* Concatenate the two 32-bit values and use a 64-bit shift. */ tcg_gen_subi_tl(tcg_ctx, cpu_tmp0, count, 1); if (is_right) { - tcg_gen_concat_tl_i64(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); - tcg_gen_shr_i64(tcg_ctx, cpu_tmp0, *cpu_T[0], cpu_tmp0); - tcg_gen_shr_i64(tcg_ctx, *cpu_T[0], *cpu_T[0], count); + tcg_gen_concat_tl_i64(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); + tcg_gen_shr_i64(tcg_ctx, cpu_tmp0, cpu_T0, cpu_tmp0); + tcg_gen_shr_i64(tcg_ctx, cpu_T0, cpu_T0, count); } else { - tcg_gen_concat_tl_i64(tcg_ctx, *cpu_T[0], *cpu_T[1], *cpu_T[0]); - tcg_gen_shl_i64(tcg_ctx, cpu_tmp0, *cpu_T[0], cpu_tmp0); - tcg_gen_shl_i64(tcg_ctx, *cpu_T[0], *cpu_T[0], count); + tcg_gen_concat_tl_i64(tcg_ctx, cpu_T0, cpu_T1, cpu_T0); + tcg_gen_shl_i64(tcg_ctx, cpu_tmp0, cpu_T0, cpu_tmp0); + tcg_gen_shl_i64(tcg_ctx, cpu_T0, cpu_T0, count); tcg_gen_shri_i64(tcg_ctx, cpu_tmp0, cpu_tmp0, 32); - tcg_gen_shri_i64(tcg_ctx, *cpu_T[0], *cpu_T[0], 32); + tcg_gen_shri_i64(tcg_ctx, cpu_T0, cpu_T0, 32); } break; #endif default: tcg_gen_subi_tl(tcg_ctx, cpu_tmp0, count, 1); if (is_right) { - tcg_gen_shr_tl(tcg_ctx, cpu_tmp0, *cpu_T[0], cpu_tmp0); + tcg_gen_shr_tl(tcg_ctx, cpu_tmp0, cpu_T0, cpu_tmp0); tcg_gen_subfi_tl(tcg_ctx, cpu_tmp4, mask + 1, count); - tcg_gen_shr_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], count); - tcg_gen_shl_tl(tcg_ctx, *cpu_T[1], *cpu_T[1], cpu_tmp4); + tcg_gen_shr_tl(tcg_ctx, cpu_T0, cpu_T0, count); + tcg_gen_shl_tl(tcg_ctx, cpu_T1, cpu_T1, cpu_tmp4); } else { - tcg_gen_shl_tl(tcg_ctx, cpu_tmp0, *cpu_T[0], cpu_tmp0); + tcg_gen_shl_tl(tcg_ctx, cpu_tmp0, cpu_T0, cpu_tmp0); if (ot == MO_16) { /* Only needed if count > 16, for Intel behaviour. */ tcg_gen_subfi_tl(tcg_ctx, cpu_tmp4, 33, count); - tcg_gen_shr_tl(tcg_ctx, cpu_tmp4, *cpu_T[1], cpu_tmp4); + tcg_gen_shr_tl(tcg_ctx, cpu_tmp4, cpu_T1, cpu_tmp4); tcg_gen_or_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, cpu_tmp4); } tcg_gen_subfi_tl(tcg_ctx, cpu_tmp4, mask + 1, count); - tcg_gen_shl_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], count); - tcg_gen_shr_tl(tcg_ctx, *cpu_T[1], *cpu_T[1], cpu_tmp4); + tcg_gen_shl_tl(tcg_ctx, cpu_T0, cpu_T0, count); + tcg_gen_shr_tl(tcg_ctx, cpu_T1, cpu_T1, cpu_tmp4); } tcg_gen_movi_tl(tcg_ctx, cpu_tmp4, 0); - tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, *cpu_T[1], count, cpu_tmp4, - cpu_tmp4, *cpu_T[1]); - tcg_gen_or_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, cpu_T1, count, cpu_tmp4, + cpu_tmp4, cpu_T1); + tcg_gen_or_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); break; } /* store */ gen_op_st_rm_T0_A0(s, ot, op1); - gen_shift_flags(s, ot, *cpu_T[0], cpu_tmp0, count, is_right); + gen_shift_flags(s, ot, cpu_T0, cpu_tmp0, count, is_right); tcg_temp_free(tcg_ctx, count); } static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s) { TCGContext *tcg_ctx = s1->uc->tcg_ctx; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T1 = *(TCGv *)tcg_ctx->cpu_T1; if (s != OR_TMP1) - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[1], s); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T1, s); switch(op) { case OP_ROL: gen_rot_rm_T1(s1, ot, d, 0); @@ -2023,7 +2031,7 @@ static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s) static void gen_shifti(DisasContext *s, int op, TCGMemOp ot, int d, int c) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T1 = *(TCGv *)tcg_ctx->cpu_T1; switch(op) { case OP_ROL: @@ -2044,7 +2052,7 @@ static void gen_shifti(DisasContext *s, int op, TCGMemOp ot, int d, int c) break; default: /* currently not optimized */ - tcg_gen_movi_tl(tcg_ctx, *cpu_T[1], c); + tcg_gen_movi_tl(tcg_ctx, cpu_T1, c); gen_shift(s, op, ot, d, OR_TMP1); break; } @@ -2278,7 +2286,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, int mod, rm; TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; mod = (modrm >> 6) & 3; @@ -2286,23 +2294,23 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, if (mod == 3) { if (is_store) { if (reg != OR_TMP0) - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], reg); - gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, reg); + gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0); } else { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], rm); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, rm); if (reg != OR_TMP0) - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); } } else { gen_lea_modrm(env, s, modrm); if (is_store) { if (reg != OR_TMP0) - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], reg); - gen_op_st_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, reg); + gen_op_st_v(s, ot, cpu_T0, cpu_A0); } else { - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); if (reg != OR_TMP0) - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); } } } @@ -2399,12 +2407,13 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b, { CCPrepare cc; TCGContext *tcg_ctx = s->uc->tcg_ctx; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; + TCGv cpu_T1 = *(TCGv *)tcg_ctx->cpu_T1; TCGv **cpu_regs = (TCGv **)tcg_ctx->cpu_regs; gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); - cc = gen_prepare_cc(s, b, *cpu_T[1]); + cc = gen_prepare_cc(s, b, cpu_T1); if (cc.mask != -1) { TCGv t0 = tcg_temp_new(tcg_ctx); tcg_gen_andi_tl(tcg_ctx, t0, cc.reg, cc.mask); @@ -2414,9 +2423,9 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b, cc.reg2 = tcg_const_tl(tcg_ctx, cc.imm); } - tcg_gen_movcond_tl(tcg_ctx, cc.cond, *cpu_T[0], cc.reg, cc.reg2, - *cpu_T[0], *cpu_regs[reg]); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + tcg_gen_movcond_tl(tcg_ctx, cc.cond, cpu_T0, cc.reg, cc.reg2, + cpu_T0, *cpu_regs[reg]); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); if (cc.mask != -1) { tcg_temp_free(tcg_ctx, cc.reg); @@ -2428,21 +2437,21 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b, static inline void gen_op_movl_T0_seg(TCGContext *s, int seg_reg) { - TCGv **cpu_T = (TCGv **)s->cpu_T; + TCGv cpu_T0 = *(TCGv *)s->cpu_T0; - tcg_gen_ld32u_tl(s, *cpu_T[0], s->cpu_env, + tcg_gen_ld32u_tl(s, cpu_T0, s->cpu_env, offsetof(CPUX86State,segs[seg_reg].selector)); } static inline void gen_op_movl_seg_T0_vm(TCGContext *s, int seg_reg) { - TCGv **cpu_T = (TCGv **)s->cpu_T; + TCGv cpu_T0 = *(TCGv *)s->cpu_T0; TCGv **cpu_seg_base = (TCGv **)s->cpu_seg_base; - tcg_gen_ext16u_tl(s, *cpu_T[0], *cpu_T[0]); - tcg_gen_st32_tl(s, *cpu_T[0], s->cpu_env, + tcg_gen_ext16u_tl(s, cpu_T0, cpu_T0); + tcg_gen_st32_tl(s, cpu_T0, s->cpu_env, offsetof(CPUX86State,segs[seg_reg].selector)); - tcg_gen_shli_tl(s, *cpu_seg_base[seg_reg], *cpu_T[0], 4); + tcg_gen_shli_tl(s, *cpu_seg_base[seg_reg], cpu_T0, 4); } /* move T0 to seg_reg and compute if the CPU state may change. Never @@ -2451,10 +2460,10 @@ static void gen_movl_seg_T0(DisasContext *s, int seg_reg) { TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 cpu_tmp2_i32 = tcg_ctx->cpu_tmp2_i32; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; if (s->pe && !s->vm86) { - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); gen_helper_load_seg(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, seg_reg), cpu_tmp2_i32); /* abort translation because the addseg value may change or because ss32 may change. For R_SS, translation must always @@ -2534,11 +2543,11 @@ static TCGMemOp gen_pop_T0(DisasContext *s) TCGMemOp d_ot = mo_pushpop(s, s->dflag); TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; TCGv **cpu_regs = (TCGv **)tcg_ctx->cpu_regs; gen_lea_v_seg(s, mo_stacksize(s), *cpu_regs[R_ESP], R_SS, -1); - gen_op_ld_v(s, d_ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, d_ot, cpu_T0, cpu_A0); return d_ot; } @@ -2583,7 +2592,7 @@ static void gen_popa(DisasContext *s) int i; TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; TCGv **cpu_regs = (TCGv **)tcg_ctx->cpu_regs; for (i = 0; i < 8; i++) { @@ -2593,8 +2602,8 @@ static void gen_popa(DisasContext *s) } tcg_gen_addi_tl(tcg_ctx, cpu_A0, *cpu_regs[R_ESP], i * size); gen_lea_v_seg(s, s_ot, cpu_A0, R_SS, -1); - gen_op_ld_v(s, d_ot, *cpu_T[0], cpu_A0); - gen_op_mov_reg_v(tcg_ctx, d_ot, 7 - i, *cpu_T[0]); + gen_op_ld_v(s, d_ot, cpu_T0, cpu_A0); + gen_op_mov_reg_v(tcg_ctx, d_ot, 7 - i, cpu_T0); } gen_stack_update(s, 8 * size); @@ -2608,12 +2617,12 @@ static void gen_enter(DisasContext *s, int esp_addend, int level) TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; TCGv cpu_tmp0 = *(TCGv *)tcg_ctx->cpu_tmp0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T1 = *(TCGv *)tcg_ctx->cpu_T1; TCGv **cpu_regs = (TCGv **)tcg_ctx->cpu_regs; /* Push BP; compute FrameTemp into T1. */ - tcg_gen_subi_tl(tcg_ctx, *cpu_T[1], *cpu_regs[R_ESP], size); - gen_lea_v_seg(s, a_ot, *cpu_T[1], R_SS, -1); + tcg_gen_subi_tl(tcg_ctx, cpu_T1, *cpu_regs[R_ESP], size); + gen_lea_v_seg(s, a_ot, cpu_T1, R_SS, -1); gen_op_st_v(s, d_ot, *cpu_regs[R_EBP], cpu_A0); level &= 31; @@ -2626,23 +2635,23 @@ static void gen_enter(DisasContext *s, int esp_addend, int level) gen_lea_v_seg(s, a_ot, cpu_A0, R_SS, -1); gen_op_ld_v(s, d_ot, cpu_tmp0, cpu_A0); - tcg_gen_subi_tl(tcg_ctx, cpu_A0, *cpu_T[1], size * i); + tcg_gen_subi_tl(tcg_ctx, cpu_A0, cpu_T1, size * i); gen_lea_v_seg(s, a_ot, cpu_A0, R_SS, -1); gen_op_st_v(s, d_ot, cpu_tmp0, cpu_A0); } /* Push the current FrameTemp as the last level. */ - tcg_gen_subi_tl(tcg_ctx, cpu_A0, *cpu_T[1], size * level); + tcg_gen_subi_tl(tcg_ctx, cpu_A0, cpu_T1, size * level); gen_lea_v_seg(s, a_ot, cpu_A0, R_SS, -1); - gen_op_st_v(s, d_ot, *cpu_T[1], cpu_A0); + gen_op_st_v(s, d_ot, cpu_T1, cpu_A0); } /* Copy the FrameTemp value to EBP. */ - gen_op_mov_reg_v(tcg_ctx, a_ot, R_EBP, *cpu_T[1]); + gen_op_mov_reg_v(tcg_ctx, a_ot, R_EBP, cpu_T1); /* Compute the final value of ESP. */ - tcg_gen_subi_tl(tcg_ctx, *cpu_T[1], *cpu_T[1], esp_addend + size * level); - gen_op_mov_reg_v(tcg_ctx, a_ot, R_ESP, *cpu_T[1]); + tcg_gen_subi_tl(tcg_ctx, cpu_T1, cpu_T1, esp_addend + size * level); + gen_op_mov_reg_v(tcg_ctx, a_ot, R_ESP, cpu_T1); } static void gen_leave(DisasContext *s) @@ -2651,16 +2660,17 @@ static void gen_leave(DisasContext *s) TCGMemOp a_ot = mo_stacksize(s); TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; + TCGv cpu_T1 = *(TCGv *)tcg_ctx->cpu_T1; TCGv **cpu_regs = (TCGv **)tcg_ctx->cpu_regs; gen_lea_v_seg(s, a_ot, *cpu_regs[R_EBP], R_SS, -1); - gen_op_ld_v(s, d_ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, d_ot, cpu_T0, cpu_A0); - tcg_gen_addi_tl(tcg_ctx, *cpu_T[1], *cpu_regs[R_EBP], 1 << d_ot); + tcg_gen_addi_tl(tcg_ctx, cpu_T1, *cpu_regs[R_EBP], 1 << d_ot); - gen_op_mov_reg_v(tcg_ctx, d_ot, R_EBP, *cpu_T[0]); - gen_op_mov_reg_v(tcg_ctx, a_ot, R_ESP, *cpu_T[1]); + gen_op_mov_reg_v(tcg_ctx, d_ot, R_EBP, cpu_T0); + gen_op_mov_reg_v(tcg_ctx, a_ot, R_ESP, cpu_T1); } static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) @@ -3365,7 +3375,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, TCGv cpu_cc_src = *(TCGv *)tcg_ctx->cpu_cc_src; TCGv cpu_cc_src2 = *(TCGv *)tcg_ctx->cpu_cc_src2; TCGv cpu_tmp0 = *(TCGv *)tcg_ctx->cpu_tmp0; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; + TCGv cpu_T1 = *(TCGv *)tcg_ctx->cpu_T1; TCGv **cpu_regs = (TCGv **)tcg_ctx->cpu_regs; b &= 0xff; @@ -3459,23 +3470,23 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, gen_stq_env_A0(s, offsetof(CPUX86State, xmm_regs[reg].ZMM_Q(0))); } else { - tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State, + tcg_gen_ld32u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, xmm_regs[reg].ZMM_L(0))); - gen_op_st_v(s, MO_32, *cpu_T[0], cpu_A0); + gen_op_st_v(s, MO_32, cpu_T0, cpu_A0); } break; case 0x6e: /* movd mm, ea */ #ifdef TARGET_X86_64 if (s->dflag == MO_64) { gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0); - tcg_gen_st_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); + tcg_gen_st_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); } else #endif { gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0); tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); gen_helper_movl_mm_T0_mmx(tcg_ctx, cpu_ptr0, cpu_tmp2_i32); } break; @@ -3485,14 +3496,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0); tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[reg])); - gen_helper_movq_mm_T0_xmm(tcg_ctx, cpu_ptr0, *cpu_T[0]); + gen_helper_movq_mm_T0_xmm(tcg_ctx, cpu_ptr0, cpu_T0); } else #endif { gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0); tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[reg])); - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); gen_helper_movl_mm_T0_xmm(tcg_ctx, cpu_ptr0, cpu_tmp2_i32); } break; @@ -3526,12 +3537,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x210: /* movss xmm, ea */ if (mod != 3) { gen_lea_modrm(env, s, modrm); - gen_op_ld_v(s, MO_32, *cpu_T[0], cpu_A0); - tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0))); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], 0); - tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(1))); - tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(2))); - tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(3))); + gen_op_ld_v(s, MO_32, cpu_T0, cpu_A0); + tcg_gen_st32_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0))); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, 0); + tcg_gen_st32_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(1))); + tcg_gen_st32_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(2))); + tcg_gen_st32_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(3))); } else { rm = (modrm & 7) | REX_B(s); gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)), @@ -3543,9 +3554,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, gen_lea_modrm(env, s, modrm); gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_regs[reg].ZMM_Q(0))); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], 0); - tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(2))); - tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(3))); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, 0); + tcg_gen_st32_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(2))); + tcg_gen_st32_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(3))); } else { rm = (modrm & 7) | REX_B(s); gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)), @@ -3647,13 +3658,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x7e: /* movd ea, mm */ #ifdef TARGET_X86_64 if (s->dflag == MO_64) { - tcg_gen_ld_i64(tcg_ctx, *cpu_T[0], cpu_env, + tcg_gen_ld_i64(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1); } else #endif { - tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, + tcg_gen_ld32u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0))); gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1); } @@ -3661,13 +3672,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x17e: /* movd ea, xmm */ #ifdef TARGET_X86_64 if (s->dflag == MO_64) { - tcg_gen_ld_i64(tcg_ctx, *cpu_T[0], cpu_env, + tcg_gen_ld_i64(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0))); gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1); } else #endif { - tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, + tcg_gen_ld32u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0))); gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1); } @@ -3712,8 +3723,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x211: /* movss ea, xmm */ if (mod != 3) { gen_lea_modrm(env, s, modrm); - tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0))); - gen_op_st_v(s, MO_32, *cpu_T[0], cpu_A0); + tcg_gen_ld32u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0))); + gen_op_st_v(s, MO_32, cpu_T0, cpu_A0); } else { rm = (modrm & 7) | REX_B(s); gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[rm].ZMM_L(0)), @@ -3762,16 +3773,16 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } val = cpu_ldub_code(env, s->pc++); if (is_xmm) { - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], val); - tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.ZMM_L(0))); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], 0); - tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.ZMM_L(1))); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, val); + tcg_gen_st32_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_t0.ZMM_L(0))); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, 0); + tcg_gen_st32_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_t0.ZMM_L(1))); op1_offset = offsetof(CPUX86State,xmm_t0); } else { - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], val); - tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], 0); - tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, val); + tcg_gen_st32_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, 0); + tcg_gen_st32_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); op1_offset = offsetof(CPUX86State,mmx_t0); } sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 + @@ -3836,12 +3847,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, op1_offset); if (ot == MO_32) { SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1]; - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); sse_fn_epi(tcg_ctx, cpu_env, cpu_ptr0, cpu_tmp2_i32); } else { #ifdef TARGET_X86_64 SSEFunc_0_epl sse_fn_epl = sse_op_table3aq[(b >> 8) & 1]; - sse_fn_epl(tcg_ctx, cpu_env, cpu_ptr0, *cpu_T[0]); + sse_fn_epl(tcg_ctx, cpu_env, cpu_ptr0, cpu_T0); #else goto illegal_op; #endif @@ -3888,8 +3899,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if ((b >> 8) & 1) { gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.ZMM_Q(0))); } else { - gen_op_ld_v(s, MO_32, *cpu_T[0], cpu_A0); - tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.ZMM_L(0))); + gen_op_ld_v(s, MO_32, cpu_T0, cpu_A0); + tcg_gen_st32_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_t0.ZMM_L(0))); } op2_offset = offsetof(CPUX86State,xmm_t0); } else { @@ -3901,17 +3912,17 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, SSEFunc_i_ep sse_fn_i_ep = sse_op_table3bi[((b >> 7) & 2) | (b & 1)]; sse_fn_i_ep(tcg_ctx, cpu_tmp2_i32, cpu_env, cpu_ptr0); - tcg_gen_extu_i32_tl(tcg_ctx, *cpu_T[0], cpu_tmp2_i32); + tcg_gen_extu_i32_tl(tcg_ctx, cpu_T0, cpu_tmp2_i32); } else { #ifdef TARGET_X86_64 SSEFunc_l_ep sse_fn_l_ep = sse_op_table3bq[((b >> 7) & 2) | (b & 1)]; - sse_fn_l_ep(tcg_ctx, *cpu_T[0], cpu_env, cpu_ptr0); + sse_fn_l_ep(tcg_ctx, cpu_T0, cpu_env, cpu_ptr0); #else goto illegal_op; #endif } - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); break; case 0xc4: /* pinsrw */ case 0x1c4: @@ -3920,11 +3931,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, val = cpu_ldub_code(env, s->pc++); if (b1) { val &= 7; - tcg_gen_st16_tl(tcg_ctx, *cpu_T[0], cpu_env, + tcg_gen_st16_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_W(val))); } else { val &= 3; - tcg_gen_st16_tl(tcg_ctx, *cpu_T[0], cpu_env, + tcg_gen_st16_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val))); } break; @@ -3937,16 +3948,16 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (b1) { val &= 7; rm = (modrm & 7) | REX_B(s); - tcg_gen_ld16u_tl(tcg_ctx, *cpu_T[0], cpu_env, + tcg_gen_ld16u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_regs[rm].ZMM_W(val))); } else { val &= 3; rm = (modrm & 7); - tcg_gen_ld16u_tl(tcg_ctx, *cpu_T[0], cpu_env, + tcg_gen_ld16u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); } reg = ((modrm >> 3) & 7) | rex_r; - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); break; case 0x1d6: /* movq ea, xmm */ if (mod != 3) { @@ -4093,11 +4104,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_regs[reg]); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); - gen_helper_crc32(tcg_ctx, *cpu_T[0], cpu_tmp2_i32, - *cpu_T[0], tcg_const_i32(tcg_ctx, 8 << ot)); + gen_helper_crc32(tcg_ctx, cpu_T0, cpu_tmp2_i32, + cpu_T0, tcg_const_i32(tcg_ctx, 8 << ot)); ot = mo_64_32(s->dflag); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); break; case 0x1f0: /* crc32 or movbe */ @@ -4122,9 +4133,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, gen_lea_modrm(env, s, modrm); if ((b & 1) == 0) { - tcg_gen_qemu_ld_tl(s->uc, *cpu_T[0], cpu_A0, + tcg_gen_qemu_ld_tl(s->uc, cpu_T0, cpu_A0, s->mem_index, ot | MO_BE); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); } else { tcg_gen_qemu_st_tl(s->uc, *cpu_regs[reg], cpu_A0, s->mem_index, ot | MO_BE); @@ -4139,8 +4150,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } ot = mo_64_32(s->dflag); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); - tcg_gen_andc_tl(tcg_ctx, *cpu_T[0], *cpu_regs[s->vex_v], *cpu_T[0]); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + tcg_gen_andc_tl(tcg_ctx, cpu_T0, *cpu_regs[s->vex_v], cpu_T0); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); gen_op_update1_cc(tcg_ctx); set_cc_op(s, CC_OP_LOGICB + ot); break; @@ -4159,12 +4170,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, /* Extract START, and shift the operand. Shifts larger than operand size get zeros. */ tcg_gen_ext8u_tl(tcg_ctx, cpu_A0, *cpu_regs[s->vex_v]); - tcg_gen_shr_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], cpu_A0); + tcg_gen_shr_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_A0); bound = tcg_const_tl(tcg_ctx, ot == MO_64 ? 63 : 31); zero = tcg_const_tl(tcg_ctx, 0); - tcg_gen_movcond_tl(tcg_ctx, TCG_COND_LEU, *cpu_T[0], cpu_A0, bound, - *cpu_T[0], zero); + tcg_gen_movcond_tl(tcg_ctx, TCG_COND_LEU, cpu_T0, cpu_A0, bound, + cpu_T0, zero); tcg_temp_free(tcg_ctx, zero); /* Extract the LEN into a mask. Lengths larger than @@ -4174,12 +4185,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, tcg_gen_movcond_tl(tcg_ctx, TCG_COND_LEU, cpu_A0, cpu_A0, bound, cpu_A0, bound); tcg_temp_free(tcg_ctx, bound); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[1], 1); - tcg_gen_shl_tl(tcg_ctx, *cpu_T[1], *cpu_T[1], cpu_A0); - tcg_gen_subi_tl(tcg_ctx, *cpu_T[1], *cpu_T[1], 1); - tcg_gen_and_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + tcg_gen_movi_tl(tcg_ctx, cpu_T1, 1); + tcg_gen_shl_tl(tcg_ctx, cpu_T1, cpu_T1, cpu_A0); + tcg_gen_subi_tl(tcg_ctx, cpu_T1, cpu_T1, 1); + tcg_gen_and_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); gen_op_update1_cc(tcg_ctx); set_cc_op(s, CC_OP_LOGICB + ot); } @@ -4193,21 +4204,21 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } ot = mo_64_32(s->dflag); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); - tcg_gen_ext8u_tl(tcg_ctx, *cpu_T[1], *cpu_regs[s->vex_v]); + tcg_gen_ext8u_tl(tcg_ctx, cpu_T1, *cpu_regs[s->vex_v]); { TCGv bound = tcg_const_tl(tcg_ctx, ot == MO_64 ? 63 : 31); /* Note that since we're using BMILG (in order to get O cleared) we need to store the inverse into C. */ tcg_gen_setcond_tl(tcg_ctx, TCG_COND_LT, cpu_cc_src, - *cpu_T[1], bound); - tcg_gen_movcond_tl(tcg_ctx, TCG_COND_GT, *cpu_T[1], *cpu_T[1], - bound, bound, *cpu_T[1]); + cpu_T1, bound); + tcg_gen_movcond_tl(tcg_ctx, TCG_COND_GT, cpu_T1, cpu_T1, + bound, bound, cpu_T1); tcg_temp_free(tcg_ctx, bound); } tcg_gen_movi_tl(tcg_ctx, cpu_A0, -1); - tcg_gen_shl_tl(tcg_ctx, cpu_A0, cpu_A0, *cpu_T[1]); - tcg_gen_andc_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], cpu_A0); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + tcg_gen_shl_tl(tcg_ctx, cpu_A0, cpu_A0, cpu_T1); + tcg_gen_andc_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_A0); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); gen_op_update1_cc(tcg_ctx); set_cc_op(s, CC_OP_BMILGB + ot); break; @@ -4222,7 +4233,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); switch (ot) { default: - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp3_i32, *cpu_regs[R_EDX]); tcg_gen_mulu2_i32(tcg_ctx, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp2_i32, cpu_tmp3_i32); @@ -4231,10 +4242,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, break; #ifdef TARGET_X86_64 case MO_64: - tcg_gen_mulu2_i64(tcg_ctx, *cpu_T[0], *cpu_T[1], - *cpu_T[0], *cpu_regs[R_EDX]); - tcg_gen_mov_i64(tcg_ctx, *cpu_regs[s->vex_v], *cpu_T[0]); - tcg_gen_mov_i64(tcg_ctx, *cpu_regs[reg], *cpu_T[1]); + tcg_gen_mulu2_i64(tcg_ctx, cpu_T0, cpu_T1, + cpu_T0, *cpu_regs[R_EDX]); + tcg_gen_mov_i64(tcg_ctx, *cpu_regs[s->vex_v], cpu_T0); + tcg_gen_mov_i64(tcg_ctx, *cpu_regs[reg], cpu_T1); break; #endif } @@ -4251,11 +4262,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, /* Note that by zero-extending the mask operand, we automatically handle zero-extending the result. */ if (ot == MO_64) { - tcg_gen_mov_tl(tcg_ctx, *cpu_T[1], *cpu_regs[s->vex_v]); + tcg_gen_mov_tl(tcg_ctx, cpu_T1, *cpu_regs[s->vex_v]); } else { - tcg_gen_ext32u_tl(tcg_ctx, *cpu_T[1], *cpu_regs[s->vex_v]); + tcg_gen_ext32u_tl(tcg_ctx, cpu_T1, *cpu_regs[s->vex_v]); } - gen_helper_pdep(tcg_ctx, *cpu_regs[reg], *cpu_T[0], *cpu_T[1]); + gen_helper_pdep(tcg_ctx, *cpu_regs[reg], cpu_T0, cpu_T1); break; case 0x2f5: /* pext Gy, By, Ey */ @@ -4269,11 +4280,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, /* Note that by zero-extending the mask operand, we automatically handle zero-extending the result. */ if (ot == MO_64) { - tcg_gen_mov_tl(tcg_ctx, *cpu_T[1], *cpu_regs[s->vex_v]); + tcg_gen_mov_tl(tcg_ctx, cpu_T1, *cpu_regs[s->vex_v]); } else { - tcg_gen_ext32u_tl(tcg_ctx, *cpu_T[1], *cpu_regs[s->vex_v]); + tcg_gen_ext32u_tl(tcg_ctx, cpu_T1, *cpu_regs[s->vex_v]); } - gen_helper_pext(tcg_ctx, *cpu_regs[reg], *cpu_T[0], *cpu_T[1]); + gen_helper_pext(tcg_ctx, *cpu_regs[reg], cpu_T0, cpu_T1); break; case 0x1f6: /* adcx Gy, Ey */ @@ -4332,22 +4343,22 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, /* If we know TL is 64-bit, and we want a 32-bit result, just do everything in 64-bit arithmetic. */ tcg_gen_ext32u_i64(tcg_ctx, *cpu_regs[reg], *cpu_regs[reg]); - tcg_gen_ext32u_i64(tcg_ctx, *cpu_T[0], *cpu_T[0]); - tcg_gen_add_i64(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_regs[reg]); - tcg_gen_add_i64(tcg_ctx, *cpu_T[0], *cpu_T[0], carry_in); - tcg_gen_ext32u_i64(tcg_ctx, *cpu_regs[reg], *cpu_T[0]); - tcg_gen_shri_i64(tcg_ctx, carry_out, *cpu_T[0], 32); + tcg_gen_ext32u_i64(tcg_ctx, cpu_T0, cpu_T0); + tcg_gen_add_i64(tcg_ctx, cpu_T0, cpu_T0, *cpu_regs[reg]); + tcg_gen_add_i64(tcg_ctx, cpu_T0, cpu_T0, carry_in); + tcg_gen_ext32u_i64(tcg_ctx, *cpu_regs[reg], cpu_T0); + tcg_gen_shri_i64(tcg_ctx, carry_out, cpu_T0, 32); break; #endif default: /* Otherwise compute the carry-out in two steps. */ zero = tcg_const_tl(tcg_ctx, 0); - tcg_gen_add2_tl(tcg_ctx, *cpu_T[0], carry_out, - *cpu_T[0], zero, + tcg_gen_add2_tl(tcg_ctx, cpu_T0, carry_out, + cpu_T0, zero, carry_in, zero); tcg_gen_add2_tl(tcg_ctx, *cpu_regs[reg], carry_out, *cpu_regs[reg], carry_out, - *cpu_T[0], zero); + cpu_T0, zero); tcg_temp_free(tcg_ctx, zero); break; } @@ -4366,24 +4377,24 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ot = mo_64_32(s->dflag); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); if (ot == MO_64) { - tcg_gen_andi_tl(tcg_ctx, *cpu_T[1], *cpu_regs[s->vex_v], 63); + tcg_gen_andi_tl(tcg_ctx, cpu_T1, *cpu_regs[s->vex_v], 63); } else { - tcg_gen_andi_tl(tcg_ctx, *cpu_T[1], *cpu_regs[s->vex_v], 31); + tcg_gen_andi_tl(tcg_ctx, cpu_T1, *cpu_regs[s->vex_v], 31); } if (b == 0x1f7) { - tcg_gen_shl_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + tcg_gen_shl_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); } else if (b == 0x2f7) { if (ot != MO_64) { - tcg_gen_ext32s_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); + tcg_gen_ext32s_tl(tcg_ctx, cpu_T0, cpu_T0); } - tcg_gen_sar_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + tcg_gen_sar_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); } else { if (ot != MO_64) { - tcg_gen_ext32u_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); + tcg_gen_ext32u_tl(tcg_ctx, cpu_T0, cpu_T0); } - tcg_gen_shr_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); + tcg_gen_shr_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); } - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); break; case 0x0f3: @@ -4400,26 +4411,26 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, switch (reg & 7) { case 1: /* blsr By,Ey */ - tcg_gen_neg_tl(tcg_ctx, *cpu_T[1], *cpu_T[0]); - tcg_gen_and_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); - gen_op_mov_reg_v(tcg_ctx, ot, s->vex_v, *cpu_T[0]); + tcg_gen_neg_tl(tcg_ctx, cpu_T1, cpu_T0); + tcg_gen_and_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); + gen_op_mov_reg_v(tcg_ctx, ot, s->vex_v, cpu_T0); gen_op_update2_cc(tcg_ctx); set_cc_op(s, CC_OP_BMILGB + ot); break; case 2: /* blsmsk By,Ey */ - tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, *cpu_T[0]); - tcg_gen_subi_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], 1); - tcg_gen_xor_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], cpu_cc_src); - tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0]); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, cpu_T0); + tcg_gen_subi_tl(tcg_ctx, cpu_T0, cpu_T0, 1); + tcg_gen_xor_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_cc_src); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, cpu_T0); set_cc_op(s, CC_OP_BMILGB + ot); break; case 3: /* blsi By, Ey */ - tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, *cpu_T[0]); - tcg_gen_subi_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], 1); - tcg_gen_and_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], cpu_cc_src); - tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0]); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, cpu_T0); + tcg_gen_subi_tl(tcg_ctx, cpu_T0, cpu_T0, 1); + tcg_gen_and_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_cc_src); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, cpu_T0); set_cc_op(s, CC_OP_BMILGB + ot); break; @@ -4460,22 +4471,22 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, val = cpu_ldub_code(env, s->pc++); switch (b) { case 0x14: /* pextrb */ - tcg_gen_ld8u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State, + tcg_gen_ld8u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, xmm_regs[reg].ZMM_B(val & 15))); if (mod == 3) { - gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0); } else { - tcg_gen_qemu_st_tl(s->uc, *cpu_T[0], cpu_A0, + tcg_gen_qemu_st_tl(s->uc, cpu_T0, cpu_A0, s->mem_index, MO_UB); } break; case 0x15: /* pextrw */ - tcg_gen_ld16u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State, + tcg_gen_ld16u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, xmm_regs[reg].ZMM_W(val & 7))); if (mod == 3) { - gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0); } else { - tcg_gen_qemu_st_tl(s->uc, *cpu_T[0], cpu_A0, + tcg_gen_qemu_st_tl(s->uc, cpu_T0, cpu_A0, s->mem_index, MO_LEUW); } break; @@ -4507,23 +4518,23 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } break; case 0x17: /* extractps */ - tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State, + tcg_gen_ld32u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, xmm_regs[reg].ZMM_L(val & 3))); if (mod == 3) { - gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0); } else { - tcg_gen_qemu_st_tl(s->uc, *cpu_T[0], cpu_A0, + tcg_gen_qemu_st_tl(s->uc, cpu_T0, cpu_A0, s->mem_index, MO_LEUL); } break; case 0x20: /* pinsrb */ if (mod == 3) { - gen_op_mov_v_reg(tcg_ctx, MO_32, *cpu_T[0], rm); + gen_op_mov_v_reg(tcg_ctx, MO_32, cpu_T0, rm); } else { - tcg_gen_qemu_ld_tl(s->uc, *cpu_T[0], cpu_A0, + tcg_gen_qemu_ld_tl(s->uc, cpu_T0, cpu_A0, s->mem_index, MO_UB); } - tcg_gen_st8_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State, + tcg_gen_st8_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, xmm_regs[reg].ZMM_B(val & 15))); break; case 0x21: /* insertps */ @@ -4638,13 +4649,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); b = cpu_ldub_code(env, s->pc++); if (ot == MO_64) { - tcg_gen_rotri_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], b & 63); + tcg_gen_rotri_tl(tcg_ctx, cpu_T0, cpu_T0, b & 63); } else { - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); tcg_gen_rotri_i32(tcg_ctx, cpu_tmp2_i32, cpu_tmp2_i32, b & 31); - tcg_gen_extu_i32_tl(tcg_ctx, *cpu_T[0], cpu_tmp2_i32); + tcg_gen_extu_i32_tl(tcg_ctx, cpu_T0, cpu_tmp2_i32); } - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); break; default: @@ -4696,8 +4707,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, switch (sz) { case 2: /* 32 bit access */ - gen_op_ld_v(s, MO_32, *cpu_T[0], cpu_A0); - tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, + gen_op_ld_v(s, MO_32, cpu_T0, cpu_A0); + tcg_gen_st32_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,xmm_t0.ZMM_L(0))); break; case 3: @@ -4786,22 +4797,22 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, // Unicorn: sync EFLAGS on demand static void sync_eflags(DisasContext *s, TCGContext *tcg_ctx) { - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; TCGv_ptr cpu_env = tcg_ctx->cpu_env; gen_update_cc_op(s); - gen_helper_read_eflags(tcg_ctx, *cpu_T[0], cpu_env); - tcg_gen_st_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State, eflags)); + gen_helper_read_eflags(tcg_ctx, cpu_T0, cpu_env); + tcg_gen_st_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, eflags)); } /* static void restore_eflags(DisasContext *s, TCGContext *tcg_ctx) { - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; TCGv_ptr cpu_env = tcg_ctx->cpu_env; - tcg_gen_ld_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State, eflags)); - gen_helper_write_eflags(tcg_ctx, cpu_env, *cpu_T[0], + tcg_gen_ld_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, eflags)); + gen_helper_write_eflags(tcg_ctx, cpu_env, cpu_T0, tcg_const_i32(tcg_ctx, (TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff)); set_cc_op(s, CC_OP_EFLAGS); } @@ -4829,7 +4840,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, TCGv cpu_cc_srcT = *(TCGv *)tcg_ctx->cpu_cc_srcT; TCGv cpu_tmp0 = *(TCGv *)tcg_ctx->cpu_tmp0; TCGv cpu_tmp4 = *(TCGv *)tcg_ctx->cpu_tmp4; - TCGv **cpu_T = (TCGv **)tcg_ctx->cpu_T; + TCGv cpu_T0 = *(TCGv *)tcg_ctx->cpu_T0; + TCGv cpu_T1 = *(TCGv *)tcg_ctx->cpu_T1; TCGv **cpu_regs = (TCGv **)tcg_ctx->cpu_regs; TCGArg* save_opparam_ptr = tcg_ctx->gen_opparam_buf + tcg_ctx->gen_op_buf[tcg_ctx->gen_last_op_idx].args; bool cc_op_dirty = s->cc_op_dirty; @@ -5067,13 +5079,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, xor_zero: /* xor reg, reg optimisation */ set_cc_op(s, CC_OP_CLR); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], 0); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, 0); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); break; } else { opreg = rm; } - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[1], reg); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T1, reg); gen_op(s, op, ot, opreg); break; case 1: /* OP Gv, Ev */ @@ -5083,17 +5095,17 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, rm = (modrm & 7) | REX_B(s); if (mod != 3) { gen_lea_modrm(env, s, modrm); - gen_op_ld_v(s, ot, *cpu_T[1], cpu_A0); + gen_op_ld_v(s, ot, cpu_T1, cpu_A0); } else if (op == OP_XORL && rm == reg) { goto xor_zero; } else { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[1], rm); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T1, rm); } gen_op(s, op, ot, reg); break; case 2: /* OP A, Iv */ val = insn_get(env, s, ot); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[1], val); + tcg_gen_movi_tl(tcg_ctx, cpu_T1, val); gen_op(s, op, ot, OR_EAX); break; } @@ -5138,7 +5150,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, val = (int8_t)insn_get(env, s, MO_8); break; } - tcg_gen_movi_tl(tcg_ctx, *cpu_T[1], val); + tcg_gen_movi_tl(tcg_ctx, cpu_T1, val); gen_op(s, op, ot, opreg); } break; @@ -5167,32 +5179,32 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (op == 0) s->rip_offset = insn_const_size(ot); gen_lea_modrm(env, s, modrm); - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); } else { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], rm); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, rm); } switch(op) { case 0: /* test */ val = insn_get(env, s, ot); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[1], val); + tcg_gen_movi_tl(tcg_ctx, cpu_T1, val); gen_op_testl_T0_T1_cc(tcg_ctx); set_cc_op(s, CC_OP_LOGICB + ot); break; case 2: /* not */ - tcg_gen_not_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); + tcg_gen_not_tl(tcg_ctx, cpu_T0, cpu_T0); if (mod != 3) { - gen_op_st_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_st_v(s, ot, cpu_T0, cpu_A0); } else { - gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0); } break; case 3: /* neg */ - tcg_gen_neg_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); + tcg_gen_neg_tl(tcg_ctx, cpu_T0, cpu_T0); if (mod != 3) { - gen_op_st_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_st_v(s, ot, cpu_T0, cpu_A0); } else { - gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0); } gen_op_update_neg_cc(tcg_ctx); set_cc_op(s, CC_OP_SUBB + ot); @@ -5200,32 +5212,32 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 4: /* mul */ switch(ot) { case MO_8: - gen_op_mov_v_reg(tcg_ctx, MO_8, *cpu_T[1], R_EAX); - tcg_gen_ext8u_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); - tcg_gen_ext8u_tl(tcg_ctx, *cpu_T[1], *cpu_T[1]); + gen_op_mov_v_reg(tcg_ctx, MO_8, cpu_T1, R_EAX); + tcg_gen_ext8u_tl(tcg_ctx, cpu_T0, cpu_T0); + tcg_gen_ext8u_tl(tcg_ctx, cpu_T1, cpu_T1); /* XXX: use 32 bit mul which could be faster */ - tcg_gen_mul_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); - gen_op_mov_reg_v(tcg_ctx, MO_16, R_EAX, *cpu_T[0]); - tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0]); - tcg_gen_andi_tl(tcg_ctx, cpu_cc_src, *cpu_T[0], 0xff00); + tcg_gen_mul_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); + gen_op_mov_reg_v(tcg_ctx, MO_16, R_EAX, cpu_T0); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, cpu_T0); + tcg_gen_andi_tl(tcg_ctx, cpu_cc_src, cpu_T0, 0xff00); set_cc_op(s, CC_OP_MULB); break; case MO_16: - gen_op_mov_v_reg(tcg_ctx, MO_16, *cpu_T[1], R_EAX); - tcg_gen_ext16u_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); - tcg_gen_ext16u_tl(tcg_ctx, *cpu_T[1], *cpu_T[1]); + gen_op_mov_v_reg(tcg_ctx, MO_16, cpu_T1, R_EAX); + tcg_gen_ext16u_tl(tcg_ctx, cpu_T0, cpu_T0); + tcg_gen_ext16u_tl(tcg_ctx, cpu_T1, cpu_T1); /* XXX: use 32 bit mul which could be faster */ - tcg_gen_mul_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); - gen_op_mov_reg_v(tcg_ctx, MO_16, R_EAX, *cpu_T[0]); - tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0]); - tcg_gen_shri_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], 16); - gen_op_mov_reg_v(tcg_ctx, MO_16, R_EDX, *cpu_T[0]); - tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, *cpu_T[0]); + tcg_gen_mul_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); + gen_op_mov_reg_v(tcg_ctx, MO_16, R_EAX, cpu_T0); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, cpu_T0); + tcg_gen_shri_tl(tcg_ctx, cpu_T0, cpu_T0, 16); + gen_op_mov_reg_v(tcg_ctx, MO_16, R_EDX, cpu_T0); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, cpu_T0); set_cc_op(s, CC_OP_MULW); break; default: case MO_32: - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp3_i32, *cpu_regs[R_EAX]); tcg_gen_mulu2_i32(tcg_ctx, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp2_i32, cpu_tmp3_i32); @@ -5238,7 +5250,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, #ifdef TARGET_X86_64 case MO_64: tcg_gen_mulu2_i64(tcg_ctx, *cpu_regs[R_EAX], *cpu_regs[R_EDX], - *cpu_T[0], *cpu_regs[R_EAX]); + cpu_T0, *cpu_regs[R_EAX]); tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, *cpu_regs[R_EAX]); tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, *cpu_regs[R_EDX]); set_cc_op(s, CC_OP_MULQ); @@ -5249,34 +5261,34 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 5: /* imul */ switch(ot) { case MO_8: - gen_op_mov_v_reg(tcg_ctx, MO_8, *cpu_T[1], R_EAX); - tcg_gen_ext8s_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); - tcg_gen_ext8s_tl(tcg_ctx, *cpu_T[1], *cpu_T[1]); + gen_op_mov_v_reg(tcg_ctx, MO_8, cpu_T1, R_EAX); + tcg_gen_ext8s_tl(tcg_ctx, cpu_T0, cpu_T0); + tcg_gen_ext8s_tl(tcg_ctx, cpu_T1, cpu_T1); /* XXX: use 32 bit mul which could be faster */ - tcg_gen_mul_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); - gen_op_mov_reg_v(tcg_ctx, MO_16, R_EAX, *cpu_T[0]); - tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0]); - tcg_gen_ext8s_tl(tcg_ctx, cpu_tmp0, *cpu_T[0]); - tcg_gen_sub_tl(tcg_ctx, cpu_cc_src, *cpu_T[0], cpu_tmp0); + tcg_gen_mul_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); + gen_op_mov_reg_v(tcg_ctx, MO_16, R_EAX, cpu_T0); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, cpu_T0); + tcg_gen_ext8s_tl(tcg_ctx, cpu_tmp0, cpu_T0); + tcg_gen_sub_tl(tcg_ctx, cpu_cc_src, cpu_T0, cpu_tmp0); set_cc_op(s, CC_OP_MULB); break; case MO_16: - gen_op_mov_v_reg(tcg_ctx, MO_16, *cpu_T[1], R_EAX); - tcg_gen_ext16s_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); - tcg_gen_ext16s_tl(tcg_ctx, *cpu_T[1], *cpu_T[1]); + gen_op_mov_v_reg(tcg_ctx, MO_16, cpu_T1, R_EAX); + tcg_gen_ext16s_tl(tcg_ctx, cpu_T0, cpu_T0); + tcg_gen_ext16s_tl(tcg_ctx, cpu_T1, cpu_T1); /* XXX: use 32 bit mul which could be faster */ - tcg_gen_mul_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); - gen_op_mov_reg_v(tcg_ctx, MO_16, R_EAX, *cpu_T[0]); - tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0]); - tcg_gen_ext16s_tl(tcg_ctx, cpu_tmp0, *cpu_T[0]); - tcg_gen_sub_tl(tcg_ctx, cpu_cc_src, *cpu_T[0], cpu_tmp0); - tcg_gen_shri_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], 16); - gen_op_mov_reg_v(tcg_ctx, MO_16, R_EDX, *cpu_T[0]); + tcg_gen_mul_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); + gen_op_mov_reg_v(tcg_ctx, MO_16, R_EAX, cpu_T0); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, cpu_T0); + tcg_gen_ext16s_tl(tcg_ctx, cpu_tmp0, cpu_T0); + tcg_gen_sub_tl(tcg_ctx, cpu_cc_src, cpu_T0, cpu_tmp0); + tcg_gen_shri_tl(tcg_ctx, cpu_T0, cpu_T0, 16); + gen_op_mov_reg_v(tcg_ctx, MO_16, R_EDX, cpu_T0); set_cc_op(s, CC_OP_MULW); break; default: case MO_32: - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp3_i32, *cpu_regs[R_EAX]); tcg_gen_muls2_i32(tcg_ctx, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp2_i32, cpu_tmp3_i32); @@ -5291,7 +5303,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, #ifdef TARGET_X86_64 case MO_64: tcg_gen_muls2_i64(tcg_ctx, *cpu_regs[R_EAX], *cpu_regs[R_EDX], - *cpu_T[0], *cpu_regs[R_EAX]); + cpu_T0, *cpu_regs[R_EAX]); tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, *cpu_regs[R_EAX]); tcg_gen_sari_tl(tcg_ctx, cpu_cc_src, *cpu_regs[R_EAX], 63); tcg_gen_sub_tl(tcg_ctx, cpu_cc_src, cpu_cc_src, *cpu_regs[R_EDX]); @@ -5303,18 +5315,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 6: /* div */ switch(ot) { case MO_8: - gen_helper_divb_AL(tcg_ctx, cpu_env, *cpu_T[0]); + gen_helper_divb_AL(tcg_ctx, cpu_env, cpu_T0); break; case MO_16: - gen_helper_divw_AX(tcg_ctx, cpu_env, *cpu_T[0]); + gen_helper_divw_AX(tcg_ctx, cpu_env, cpu_T0); break; default: case MO_32: - gen_helper_divl_EAX(tcg_ctx, cpu_env, *cpu_T[0]); + gen_helper_divl_EAX(tcg_ctx, cpu_env, cpu_T0); break; #ifdef TARGET_X86_64 case MO_64: - gen_helper_divq_EAX(tcg_ctx, cpu_env, *cpu_T[0]); + gen_helper_divq_EAX(tcg_ctx, cpu_env, cpu_T0); break; #endif } @@ -5322,18 +5334,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 7: /* idiv */ switch(ot) { case MO_8: - gen_helper_idivb_AL(tcg_ctx, cpu_env, *cpu_T[0]); + gen_helper_idivb_AL(tcg_ctx, cpu_env, cpu_T0); break; case MO_16: - gen_helper_idivw_AX(tcg_ctx, cpu_env, *cpu_T[0]); + gen_helper_idivw_AX(tcg_ctx, cpu_env, cpu_T0); break; default: case MO_32: - gen_helper_idivl_EAX(tcg_ctx, cpu_env, *cpu_T[0]); + gen_helper_idivl_EAX(tcg_ctx, cpu_env, cpu_T0); break; #ifdef TARGET_X86_64 case MO_64: - gen_helper_idivq_EAX(tcg_ctx, cpu_env, *cpu_T[0]); + gen_helper_idivq_EAX(tcg_ctx, cpu_env, cpu_T0); break; #endif } @@ -5368,9 +5380,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (mod != 3) { gen_lea_modrm(env, s, modrm); if (op >= 2 && op != 3 && op != 5) - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); } else { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], rm); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, rm); } switch(op) { @@ -5391,27 +5403,27 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 2: /* call Ev */ /* XXX: optimize if memory (no 'and' is necessary) */ if (dflag == MO_16) { - tcg_gen_ext16u_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); + tcg_gen_ext16u_tl(tcg_ctx, cpu_T0, cpu_T0); } next_eip = s->pc - s->cs_base; - tcg_gen_movi_tl(tcg_ctx, *cpu_T[1], next_eip); - gen_push_v(s, *cpu_T[1]); - gen_op_jmp_v(tcg_ctx, *cpu_T[0]); + tcg_gen_movi_tl(tcg_ctx, cpu_T1, next_eip); + gen_push_v(s, cpu_T1); + gen_op_jmp_v(tcg_ctx, cpu_T0); gen_eob(s); break; case 3: /* lcall Ev */ - gen_op_ld_v(s, ot, *cpu_T[1], cpu_A0); + gen_op_ld_v(s, ot, cpu_T1, cpu_A0); gen_add_A0_im(s, 1 << ot); - gen_op_ld_v(s, MO_16, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, MO_16, cpu_T0, cpu_A0); do_lcall: if (s->pe && !s->vm86) { - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); - gen_helper_lcall_protected(tcg_ctx, cpu_env, cpu_tmp2_i32, *cpu_T[1], + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); + gen_helper_lcall_protected(tcg_ctx, cpu_env, cpu_tmp2_i32, cpu_T1, tcg_const_i32(tcg_ctx, dflag - 1), tcg_const_tl(tcg_ctx, s->pc - s->cs_base)); } else { - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); - gen_helper_lcall_real(tcg_ctx, cpu_env, cpu_tmp2_i32, *cpu_T[1], + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); + gen_helper_lcall_real(tcg_ctx, cpu_env, cpu_tmp2_i32, cpu_T1, tcg_const_i32(tcg_ctx, dflag - 1), tcg_const_i32(tcg_ctx, s->pc - s->cs_base)); } @@ -5419,28 +5431,28 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 4: /* jmp Ev */ if (dflag == MO_16) { - tcg_gen_ext16u_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); + tcg_gen_ext16u_tl(tcg_ctx, cpu_T0, cpu_T0); } - gen_op_jmp_v(tcg_ctx, *cpu_T[0]); + gen_op_jmp_v(tcg_ctx, cpu_T0); gen_eob(s); break; case 5: /* ljmp Ev */ - gen_op_ld_v(s, ot, *cpu_T[1], cpu_A0); + gen_op_ld_v(s, ot, cpu_T1, cpu_A0); gen_add_A0_im(s, 1 << ot); - gen_op_ld_v(s, MO_16, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, MO_16, cpu_T0, cpu_A0); do_ljmp: if (s->pe && !s->vm86) { - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); - gen_helper_ljmp_protected(tcg_ctx, cpu_env, cpu_tmp2_i32, *cpu_T[1], + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); + gen_helper_ljmp_protected(tcg_ctx, cpu_env, cpu_tmp2_i32, cpu_T1, tcg_const_tl(tcg_ctx, s->pc - s->cs_base)); } else { gen_op_movl_seg_T0_vm(tcg_ctx, R_CS); - gen_op_jmp_v(tcg_ctx, *cpu_T[1]); + gen_op_jmp_v(tcg_ctx, cpu_T1); } gen_eob(s); break; case 6: /* push Ev */ - gen_push_v(s, *cpu_T[0]); + gen_push_v(s, cpu_T0); break; default: goto illegal_op; @@ -5455,7 +5467,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, reg = ((modrm >> 3) & 7) | rex_r; gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[1], reg); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T1, reg); gen_op_testl_T0_T1_cc(tcg_ctx); set_cc_op(s, CC_OP_LOGICB + ot); break; @@ -5465,8 +5477,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = mo_b_d(b, dflag); val = insn_get(env, s, ot); - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], OR_EAX); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[1], val); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, OR_EAX); + tcg_gen_movi_tl(tcg_ctx, cpu_T1, val); gen_op_testl_T0_T1_cc(tcg_ctx); set_cc_op(s, CC_OP_LOGICB + ot); break; @@ -5475,20 +5487,20 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, switch (dflag) { #ifdef TARGET_X86_64 case MO_64: - gen_op_mov_v_reg(tcg_ctx, MO_32, *cpu_T[0], R_EAX); - tcg_gen_ext32s_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); - gen_op_mov_reg_v(tcg_ctx, MO_64, R_EAX, *cpu_T[0]); + gen_op_mov_v_reg(tcg_ctx, MO_32, cpu_T0, R_EAX); + tcg_gen_ext32s_tl(tcg_ctx, cpu_T0, cpu_T0); + gen_op_mov_reg_v(tcg_ctx, MO_64, R_EAX, cpu_T0); break; #endif case MO_32: - gen_op_mov_v_reg(tcg_ctx, MO_16, *cpu_T[0], R_EAX); - tcg_gen_ext16s_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); - gen_op_mov_reg_v(tcg_ctx, MO_32, R_EAX, *cpu_T[0]); + gen_op_mov_v_reg(tcg_ctx, MO_16, cpu_T0, R_EAX); + tcg_gen_ext16s_tl(tcg_ctx, cpu_T0, cpu_T0); + gen_op_mov_reg_v(tcg_ctx, MO_32, R_EAX, cpu_T0); break; case MO_16: - gen_op_mov_v_reg(tcg_ctx, MO_8, *cpu_T[0], R_EAX); - tcg_gen_ext8s_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); - gen_op_mov_reg_v(tcg_ctx, MO_16, R_EAX, *cpu_T[0]); + gen_op_mov_v_reg(tcg_ctx, MO_8, cpu_T0, R_EAX); + tcg_gen_ext8s_tl(tcg_ctx, cpu_T0, cpu_T0); + gen_op_mov_reg_v(tcg_ctx, MO_16, R_EAX, cpu_T0); break; default: tcg_abort(); @@ -5498,22 +5510,22 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, switch (dflag) { #ifdef TARGET_X86_64 case MO_64: - gen_op_mov_v_reg(tcg_ctx, MO_64, *cpu_T[0], R_EAX); - tcg_gen_sari_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], 63); - gen_op_mov_reg_v(tcg_ctx, MO_64, R_EDX, *cpu_T[0]); + gen_op_mov_v_reg(tcg_ctx, MO_64, cpu_T0, R_EAX); + tcg_gen_sari_tl(tcg_ctx, cpu_T0, cpu_T0, 63); + gen_op_mov_reg_v(tcg_ctx, MO_64, R_EDX, cpu_T0); break; #endif case MO_32: - gen_op_mov_v_reg(tcg_ctx, MO_32, *cpu_T[0], R_EAX); - tcg_gen_ext32s_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); - tcg_gen_sari_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], 31); - gen_op_mov_reg_v(tcg_ctx, MO_32, R_EDX, *cpu_T[0]); + gen_op_mov_v_reg(tcg_ctx, MO_32, cpu_T0, R_EAX); + tcg_gen_ext32s_tl(tcg_ctx, cpu_T0, cpu_T0); + tcg_gen_sari_tl(tcg_ctx, cpu_T0, cpu_T0, 31); + gen_op_mov_reg_v(tcg_ctx, MO_32, R_EDX, cpu_T0); break; case MO_16: - gen_op_mov_v_reg(tcg_ctx, MO_16, *cpu_T[0], R_EAX); - tcg_gen_ext16s_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); - tcg_gen_sari_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], 15); - gen_op_mov_reg_v(tcg_ctx, MO_16, R_EDX, *cpu_T[0]); + gen_op_mov_v_reg(tcg_ctx, MO_16, cpu_T0, R_EAX); + tcg_gen_ext16s_tl(tcg_ctx, cpu_T0, cpu_T0); + tcg_gen_sari_tl(tcg_ctx, cpu_T0, cpu_T0, 15); + gen_op_mov_reg_v(tcg_ctx, MO_16, R_EDX, cpu_T0); break; default: tcg_abort(); @@ -5532,25 +5544,25 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); if (b == 0x69) { val = insn_get(env, s, ot); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[1], val); + tcg_gen_movi_tl(tcg_ctx, cpu_T1, val); } else if (b == 0x6b) { val = (int8_t)insn_get(env, s, MO_8); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[1], val); + tcg_gen_movi_tl(tcg_ctx, cpu_T1, val); } else { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[1], reg); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T1, reg); } switch (ot) { #ifdef TARGET_X86_64 case MO_64: - tcg_gen_muls2_i64(tcg_ctx, *cpu_regs[reg], *cpu_T[1], *cpu_T[0], *cpu_T[1]); + tcg_gen_muls2_i64(tcg_ctx, *cpu_regs[reg], cpu_T1, cpu_T0, cpu_T1); tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, *cpu_regs[reg]); tcg_gen_sari_tl(tcg_ctx, cpu_cc_src, cpu_cc_dst, 63); - tcg_gen_sub_tl(tcg_ctx, cpu_cc_src, cpu_cc_src, *cpu_T[1]); + tcg_gen_sub_tl(tcg_ctx, cpu_cc_src, cpu_cc_src, cpu_T1); break; #endif case MO_32: - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp3_i32, *cpu_T[1]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp3_i32, cpu_T1); tcg_gen_muls2_i32(tcg_ctx, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp2_i32, cpu_tmp3_i32); tcg_gen_extu_i32_tl(tcg_ctx, *cpu_regs[reg], cpu_tmp2_i32); @@ -5560,14 +5572,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_extu_i32_tl(tcg_ctx, cpu_cc_src, cpu_tmp2_i32); break; default: - tcg_gen_ext16s_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); - tcg_gen_ext16s_tl(tcg_ctx, *cpu_T[1], *cpu_T[1]); + tcg_gen_ext16s_tl(tcg_ctx, cpu_T0, cpu_T0); + tcg_gen_ext16s_tl(tcg_ctx, cpu_T1, cpu_T1); /* XXX: use 32 bit mul which could be faster */ - tcg_gen_mul_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); - tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0]); - tcg_gen_ext16s_tl(tcg_ctx, cpu_tmp0, *cpu_T[0]); - tcg_gen_sub_tl(tcg_ctx, cpu_cc_src, *cpu_T[0], cpu_tmp0); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + tcg_gen_mul_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, cpu_T0); + tcg_gen_ext16s_tl(tcg_ctx, cpu_tmp0, cpu_T0); + tcg_gen_sub_tl(tcg_ctx, cpu_cc_src, cpu_T0, cpu_tmp0); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); break; } set_cc_op(s, CC_OP_MULB + ot); @@ -5580,18 +5592,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, mod = (modrm >> 6) & 3; if (mod == 3) { rm = (modrm & 7) | REX_B(s); - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], reg); - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[1], rm); - tcg_gen_add_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[1]); - gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, reg); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T1, rm); + tcg_gen_add_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T1); + gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0); } else { gen_lea_modrm(env, s, modrm); - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], reg); - gen_op_ld_v(s, ot, *cpu_T[1], cpu_A0); - tcg_gen_add_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], *cpu_T[1]); - gen_op_st_v(s, ot, *cpu_T[0], cpu_A0); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[1]); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, reg); + gen_op_ld_v(s, ot, cpu_T1, cpu_A0); + tcg_gen_add_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1); + gen_op_st_v(s, ot, cpu_T0, cpu_A0); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T1); } gen_op_update2_cc(tcg_ctx); set_cc_op(s, CC_OP_ADDB + ot); @@ -5678,15 +5690,15 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* push/pop */ case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57: //case 0x50 ... 0x57: /* push */ - gen_op_mov_v_reg(tcg_ctx, MO_32, *cpu_T[0], (b & 7) | REX_B(s)); - gen_push_v(s, *cpu_T[0]); + gen_op_mov_v_reg(tcg_ctx, MO_32, cpu_T0, (b & 7) | REX_B(s)); + gen_push_v(s, cpu_T0); break; case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f: //case 0x58 ... 0x5f: /* pop */ ot = gen_pop_T0(s); /* NOTE: order is important for pop %sp */ gen_pop_update(s, ot); - gen_op_mov_reg_v(tcg_ctx, ot, (b & 7) | REX_B(s), *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, (b & 7) | REX_B(s), cpu_T0); break; case 0x60: /* pusha */ if (CODE64(s)) @@ -5705,8 +5717,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, val = insn_get(env, s, ot); else val = (int8_t)insn_get(env, s, MO_8); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], val); - gen_push_v(s, *cpu_T[0]); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, val); + gen_push_v(s, cpu_T0); break; case 0x8f: /* pop Ev */ modrm = cpu_ldub_code(env, s->pc++); @@ -5716,7 +5728,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* NOTE: order is important for pop %sp */ gen_pop_update(s, ot); rm = (modrm & 7) | REX_B(s); - gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0); } else { /* NOTE: order is important too for MMU exceptions */ s->popl_esp_hack = 1 << ot; @@ -5744,12 +5756,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (CODE64(s)) goto illegal_op; gen_op_movl_T0_seg(tcg_ctx, b >> 3); - gen_push_v(s, *cpu_T[0]); + gen_push_v(s, cpu_T0); break; case 0x1a0: /* push fs */ case 0x1a8: /* push gs */ gen_op_movl_T0_seg(tcg_ctx, (b >> 3) & 7); - gen_push_v(s, *cpu_T[0]); + gen_push_v(s, cpu_T0); break; case 0x07: /* pop es */ case 0x17: /* pop ss */ @@ -5811,11 +5823,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, goto illegal_op; } val = insn_get(env, s, ot); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], val); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, val); if (mod != 3) { - gen_op_st_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_st_v(s, ot, cpu_T0, cpu_A0); } else { - gen_op_mov_reg_v(tcg_ctx, ot, (modrm & 7) | REX_B(s), *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, (modrm & 7) | REX_B(s), cpu_T0); } break; case 0x8a: @@ -5825,7 +5837,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, reg = ((modrm >> 3) & 7) | rex_r; gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); break; case 0x8e: /* mov seg, Gv */ modrm = cpu_ldub_code(env, s->pc++); @@ -5879,27 +5891,27 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, rm = (modrm & 7) | REX_B(s); if (mod == 3) { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], rm); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, rm); switch (s_ot) { case MO_UB: - tcg_gen_ext8u_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); + tcg_gen_ext8u_tl(tcg_ctx, cpu_T0, cpu_T0); break; case MO_SB: - tcg_gen_ext8s_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); + tcg_gen_ext8s_tl(tcg_ctx, cpu_T0, cpu_T0); break; case MO_UW: - tcg_gen_ext16u_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); + tcg_gen_ext16u_tl(tcg_ctx, cpu_T0, cpu_T0); break; default: case MO_SW: - tcg_gen_ext16s_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); + tcg_gen_ext16s_tl(tcg_ctx, cpu_T0, cpu_T0); break; } - gen_op_mov_reg_v(tcg_ctx, d_ot, reg, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, d_ot, reg, cpu_T0); } else { gen_lea_modrm(env, s, modrm); - gen_op_ld_v(s, s_ot, *cpu_T[0], cpu_A0); - gen_op_mov_reg_v(tcg_ctx, d_ot, reg, *cpu_T[0]); + gen_op_ld_v(s, s_ot, cpu_T0, cpu_A0); + gen_op_mov_reg_v(tcg_ctx, d_ot, reg, cpu_T0); } } break; @@ -5942,28 +5954,28 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_movi_tl(tcg_ctx, cpu_A0, offset_addr); gen_add_A0_ds_seg(s); if ((b & 2) == 0) { - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); - gen_op_mov_reg_v(tcg_ctx, ot, R_EAX, *cpu_T[0]); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); + gen_op_mov_reg_v(tcg_ctx, ot, R_EAX, cpu_T0); } else { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], R_EAX); - gen_op_st_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, R_EAX); + gen_op_st_v(s, ot, cpu_T0, cpu_A0); } } break; case 0xd7: /* xlat */ tcg_gen_mov_tl(tcg_ctx, cpu_A0, *cpu_regs[R_EBX]); - tcg_gen_ext8u_tl(tcg_ctx, *cpu_T[0], *cpu_regs[R_EAX]); - tcg_gen_add_tl(tcg_ctx, cpu_A0, cpu_A0, *cpu_T[0]); + tcg_gen_ext8u_tl(tcg_ctx, cpu_T0, *cpu_regs[R_EAX]); + tcg_gen_add_tl(tcg_ctx, cpu_A0, cpu_A0, cpu_T0); gen_extu(tcg_ctx, s->aflag, cpu_A0); gen_add_A0_ds_seg(s); - gen_op_ld_v(s, MO_8, *cpu_T[0], cpu_A0); - gen_op_mov_reg_v(tcg_ctx, MO_8, R_EAX, *cpu_T[0]); + gen_op_ld_v(s, MO_8, cpu_T0, cpu_A0); + gen_op_mov_reg_v(tcg_ctx, MO_8, R_EAX, cpu_T0); break; case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7: //case 0xb0 ... 0xb7: /* mov R, Ib */ val = insn_get(env, s, MO_8); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], val); - gen_op_mov_reg_v(tcg_ctx, MO_8, (b & 7) | REX_B(s), *cpu_T[0]); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, val); + gen_op_mov_reg_v(tcg_ctx, MO_8, (b & 7) | REX_B(s), cpu_T0); break; case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf: //case 0xb8 ... 0xbf: /* mov R, Iv */ @@ -5974,16 +5986,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tmp = cpu_ldq_code(env, s->pc); s->pc += 8; reg = (b & 7) | REX_B(s); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], tmp); - gen_op_mov_reg_v(tcg_ctx, MO_64, reg, *cpu_T[0]); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, tmp); + gen_op_mov_reg_v(tcg_ctx, MO_64, reg, cpu_T0); } else #endif { ot = dflag; val = insn_get(env, s, ot); reg = (b & 7) | REX_B(s); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], val); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, val); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); } break; @@ -6003,21 +6015,21 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (mod == 3) { rm = (modrm & 7) | REX_B(s); do_xchg_reg: - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], reg); - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[1], rm); - gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[1]); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, reg); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T1, rm); + gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T1); } else { gen_lea_modrm(env, s, modrm); - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], reg); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, reg); /* for xchg, lock is implicit */ if (!(prefixes & PREFIX_LOCK)) gen_helper_lock(tcg_ctx, cpu_env); - gen_op_ld_v(s, ot, *cpu_T[1], cpu_A0); - gen_op_st_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T1, cpu_A0); + gen_op_st_v(s, ot, cpu_T0, cpu_A0); if (!(prefixes & PREFIX_LOCK)) gen_helper_unlock(tcg_ctx, cpu_env); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[1]); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T1); } break; case 0xc4: /* les Gv */ @@ -6044,13 +6056,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (mod == 3) goto illegal_op; gen_lea_modrm(env, s, modrm); - gen_op_ld_v(s, ot, *cpu_T[1], cpu_A0); + gen_op_ld_v(s, ot, cpu_T1, cpu_A0); gen_add_A0_im(s, 1 << ot); /* load the segment first to handle exceptions properly */ - gen_op_ld_v(s, MO_16, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, MO_16, cpu_T0, cpu_A0); gen_movl_seg_T0(s, op); /* then put the data */ - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[1]); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T1); if (s->is_jmp) { gen_jmp_im(s, s->pc - s->cs_base); gen_eob(s); @@ -6129,7 +6141,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { opreg = rm; } - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[1], reg); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T1, reg); if (shift) { TCGv imm = tcg_const_tl(tcg_ctx, cpu_ldub_code(env, s->pc++)); @@ -6630,8 +6642,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, switch(rm) { case 0: gen_helper_fnstsw(tcg_ctx, cpu_tmp2_i32, cpu_env); - tcg_gen_extu_i32_tl(tcg_ctx, *cpu_T[0], cpu_tmp2_i32); - gen_op_mov_reg_v(tcg_ctx, MO_16, R_EAX, *cpu_T[0]); + tcg_gen_extu_i32_tl(tcg_ctx, cpu_T0, cpu_tmp2_i32); + gen_op_mov_reg_v(tcg_ctx, MO_16, R_EAX, cpu_T0); break; default: goto illegal_op; @@ -6742,7 +6754,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0x6c: /* insS */ // qq case 0x6d: ot = mo_b_d32(b, dflag); - tcg_gen_ext16u_tl(tcg_ctx, *cpu_T[0], *cpu_regs[R_EDX]); + tcg_gen_ext16u_tl(tcg_ctx, cpu_T0, *cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { @@ -6754,7 +6766,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0x6e: /* outsS */ // qq case 0x6f: ot = mo_b_d32(b, dflag); - tcg_gen_ext16u_tl(tcg_ctx, *cpu_T[0], *cpu_regs[R_EDX]); + tcg_gen_ext16u_tl(tcg_ctx, cpu_T0, *cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, svm_is_rep(prefixes) | 4); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { @@ -6771,49 +6783,49 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0xe5: // out ot = mo_b_d32(b, dflag); val = cpu_ldub_code(env, s->pc++); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], val); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); tcg_gen_movi_i32(tcg_ctx, cpu_tmp2_i32, val); - gen_helper_in_func(tcg_ctx, ot, *cpu_T[1], cpu_tmp2_i32); - gen_op_mov_reg_v(tcg_ctx, ot, R_EAX, *cpu_T[1]); + gen_helper_in_func(tcg_ctx, ot, cpu_T1, cpu_tmp2_i32); + gen_op_mov_reg_v(tcg_ctx, ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); break; case 0xe6: case 0xe7: ot = mo_b_d32(b, dflag); val = cpu_ldub_code(env, s->pc++); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], val); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, val); gen_check_io(s, ot, pc_start - s->cs_base, svm_is_rep(prefixes)); - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[1], R_EAX); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T1, R_EAX); tcg_gen_movi_i32(tcg_ctx, cpu_tmp2_i32, val); - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp3_i32, *cpu_T[1]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp3_i32, cpu_T1); gen_helper_out_func(tcg_ctx, ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); break; case 0xec: case 0xed: ot = mo_b_d32(b, dflag); - tcg_gen_ext16u_tl(tcg_ctx, *cpu_T[0], *cpu_regs[R_EDX]); + tcg_gen_ext16u_tl(tcg_ctx, cpu_T0, *cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); - gen_helper_in_func(tcg_ctx, ot, *cpu_T[1], cpu_tmp2_i32); - gen_op_mov_reg_v(tcg_ctx, ot, R_EAX, *cpu_T[1]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); + gen_helper_in_func(tcg_ctx, ot, cpu_T1, cpu_tmp2_i32); + gen_op_mov_reg_v(tcg_ctx, ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); break; case 0xee: case 0xef: ot = mo_b_d32(b, dflag); - tcg_gen_ext16u_tl(tcg_ctx, *cpu_T[0], *cpu_regs[R_EDX]); + tcg_gen_ext16u_tl(tcg_ctx, cpu_T0, *cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, svm_is_rep(prefixes)); - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[1], R_EAX); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T1, R_EAX); - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp3_i32, *cpu_T[1]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp3_i32, cpu_T1); gen_helper_out_func(tcg_ctx, ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); break; @@ -6826,14 +6838,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = gen_pop_T0(s); gen_stack_update(s, val + (1 << ot)); /* Note that gen_pop_T0 uses a zero-extending load. */ - gen_op_jmp_v(tcg_ctx, *cpu_T[0]); + gen_op_jmp_v(tcg_ctx, cpu_T0); gen_eob(s); break; case 0xc3: /* ret */ ot = gen_pop_T0(s); gen_pop_update(s, ot); /* Note that gen_pop_T0 uses a zero-extending load. */ - gen_op_jmp_v(tcg_ctx, *cpu_T[0]); + gen_op_jmp_v(tcg_ctx, cpu_T0); gen_eob(s); break; case 0xca: /* lret im */ @@ -6848,13 +6860,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_stack_A0(s); /* pop offset */ - gen_op_ld_v(s, dflag, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, dflag, cpu_T0, cpu_A0); /* NOTE: keeping EIP updated is not a problem in case of exception */ - gen_op_jmp_v(tcg_ctx, *cpu_T[0]); + gen_op_jmp_v(tcg_ctx, cpu_T0); /* pop selector */ gen_add_A0_im(s, 1 << dflag); - gen_op_ld_v(s, dflag, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, dflag, cpu_T0, cpu_A0); gen_op_movl_seg_T0_vm(tcg_ctx, R_CS); /* add stack offset */ gen_stack_update(s, val + (2 << dflag)); @@ -6898,8 +6910,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else if (!CODE64(s)) { tval &= 0xffffffff; } - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], next_eip); - gen_push_v(s, *cpu_T[0]); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, next_eip); + gen_push_v(s, cpu_T0); gen_jmp(s, tval); } break; @@ -6913,8 +6925,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, offset = insn_get(env, s, ot); selector = insn_get(env, s, MO_16); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], selector); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[1], offset); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, selector); + tcg_gen_movi_tl(tcg_ctx, cpu_T1, offset); } goto do_lcall; case 0xe9: /* jmp im */ @@ -6941,8 +6953,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, offset = insn_get(env, s, ot); selector = insn_get(env, s, MO_16); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], selector); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[1], offset); + tcg_gen_movi_tl(tcg_ctx, cpu_T0, selector); + tcg_gen_movi_tl(tcg_ctx, cpu_T1, offset); } goto do_ljmp; case 0xeb: /* jmp Jb */ @@ -6979,7 +6991,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0x190: case 0x191: case 0x192: case 0x193: case 0x194: case 0x195: case 0x196: case 0x197: case 0x198: case 0x199: case 0x19a: case 0x19b: case 0x19c: case 0x19d: case 0x19e: case 0x19f: modrm = cpu_ldub_code(env, s->pc++); - gen_setcc1(s, b, *cpu_T[0]); + gen_setcc1(s, b, cpu_T0); gen_ldst_modrm(env, s, modrm, MO_8, OR_TMP0, 1); break; //case 0x140 ... 0x14f: /* cmov Gv, Ev */ @@ -7002,8 +7014,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { gen_update_cc_op(s); - gen_helper_read_eflags(tcg_ctx, *cpu_T[0], cpu_env); - gen_push_v(s, *cpu_T[0]); + gen_helper_read_eflags(tcg_ctx, cpu_T0, cpu_env); + gen_push_v(s, cpu_T0); } break; case 0x9d: /* popf */ @@ -7014,13 +7026,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = gen_pop_T0(s); if (s->cpl == 0) { if (dflag != MO_16) { - gen_helper_write_eflags(tcg_ctx, cpu_env, *cpu_T[0], + gen_helper_write_eflags(tcg_ctx, cpu_env, cpu_T0, tcg_const_i32(tcg_ctx, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK))); } else { - gen_helper_write_eflags(tcg_ctx, cpu_env, *cpu_T[0], + gen_helper_write_eflags(tcg_ctx, cpu_env, cpu_T0, tcg_const_i32(tcg_ctx, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) @@ -7029,14 +7041,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { if (s->cpl <= s->iopl) { if (dflag != MO_16) { - gen_helper_write_eflags(tcg_ctx, cpu_env, *cpu_T[0], + gen_helper_write_eflags(tcg_ctx, cpu_env, cpu_T0, tcg_const_i32(tcg_ctx, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK))); } else { - gen_helper_write_eflags(tcg_ctx, cpu_env, *cpu_T[0], + gen_helper_write_eflags(tcg_ctx, cpu_env, cpu_T0, tcg_const_i32(tcg_ctx, (TF_MASK | AC_MASK | ID_MASK | @@ -7046,11 +7058,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } } else { if (dflag != MO_16) { - gen_helper_write_eflags(tcg_ctx, cpu_env, *cpu_T[0], + gen_helper_write_eflags(tcg_ctx, cpu_env, cpu_T0, tcg_const_i32(tcg_ctx, (TF_MASK | AC_MASK | ID_MASK | NT_MASK))); } else { - gen_helper_write_eflags(tcg_ctx, cpu_env, *cpu_T[0], + gen_helper_write_eflags(tcg_ctx, cpu_env, cpu_T0, tcg_const_i32(tcg_ctx, (TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff)); @@ -7067,19 +7079,19 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0x9e: /* sahf */ if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) goto illegal_op; - gen_op_mov_v_reg(tcg_ctx, MO_8, *cpu_T[0], R_AH); + gen_op_mov_v_reg(tcg_ctx, MO_8, cpu_T0, R_AH); gen_compute_eflags(s); tcg_gen_andi_tl(tcg_ctx, cpu_cc_src, cpu_cc_src, CC_O); - tcg_gen_andi_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C); - tcg_gen_or_tl(tcg_ctx, cpu_cc_src, cpu_cc_src, *cpu_T[0]); + tcg_gen_andi_tl(tcg_ctx, cpu_T0, cpu_T0, CC_S | CC_Z | CC_A | CC_P | CC_C); + tcg_gen_or_tl(tcg_ctx, cpu_cc_src, cpu_cc_src, cpu_T0); break; case 0x9f: /* lahf */ if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) goto illegal_op; gen_compute_eflags(s); /* Note: gen_compute_eflags() only gives the condition codes */ - tcg_gen_ori_tl(tcg_ctx, *cpu_T[0], cpu_cc_src, 0x02); - gen_op_mov_reg_v(tcg_ctx, MO_8, R_AH, *cpu_T[0]); + tcg_gen_ori_tl(tcg_ctx, cpu_T0, cpu_cc_src, 0x02); + gen_op_mov_reg_v(tcg_ctx, MO_8, R_AH, cpu_T0); break; case 0xf5: /* cmc */ gen_compute_eflags(s); @@ -7113,13 +7125,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (mod != 3) { s->rip_offset = 1; gen_lea_modrm(env, s, modrm); - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); } else { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], rm); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, rm); } /* load shift */ val = cpu_ldub_code(env, s->pc++); - tcg_gen_movi_tl(tcg_ctx, *cpu_T[1], val); + tcg_gen_movi_tl(tcg_ctx, cpu_T1, val); if (op < 4) goto illegal_op; op -= 4; @@ -7141,46 +7153,46 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); - gen_op_mov_v_reg(tcg_ctx, MO_32, *cpu_T[1], reg); + gen_op_mov_v_reg(tcg_ctx, MO_32, cpu_T1, reg); if (mod != 3) { gen_lea_modrm(env, s, modrm); /* specific case: we need to add a displacement */ - gen_exts(tcg_ctx, ot, *cpu_T[1]); - tcg_gen_sari_tl(tcg_ctx, cpu_tmp0, *cpu_T[1], 3 + ot); + gen_exts(tcg_ctx, ot, cpu_T1); + tcg_gen_sari_tl(tcg_ctx, cpu_tmp0, cpu_T1, 3 + ot); tcg_gen_shli_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, ot); tcg_gen_add_tl(tcg_ctx, cpu_A0, cpu_A0, cpu_tmp0); - gen_op_ld_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); } else { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], rm); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, rm); } bt_op: - tcg_gen_andi_tl(tcg_ctx, *cpu_T[1], *cpu_T[1], (1 << (3 + ot)) - 1); - tcg_gen_shr_tl(tcg_ctx, cpu_tmp4, *cpu_T[0], *cpu_T[1]); + tcg_gen_andi_tl(tcg_ctx, cpu_T1, cpu_T1, (1 << (3 + ot)) - 1); + tcg_gen_shr_tl(tcg_ctx, cpu_tmp4, cpu_T0, cpu_T1); switch(op) { case 0: break; case 1: tcg_gen_movi_tl(tcg_ctx, cpu_tmp0, 1); - tcg_gen_shl_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, *cpu_T[1]); - tcg_gen_or_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], cpu_tmp0); + tcg_gen_shl_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, cpu_T1); + tcg_gen_or_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp0); break; case 2: tcg_gen_movi_tl(tcg_ctx, cpu_tmp0, 1); - tcg_gen_shl_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, *cpu_T[1]); - tcg_gen_andc_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], cpu_tmp0); + tcg_gen_shl_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, cpu_T1); + tcg_gen_andc_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp0); break; default: case 3: tcg_gen_movi_tl(tcg_ctx, cpu_tmp0, 1); - tcg_gen_shl_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, *cpu_T[1]); - tcg_gen_xor_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], cpu_tmp0); + tcg_gen_shl_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, cpu_T1); + tcg_gen_xor_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_tmp0); break; } if (op != 0) { if (mod != 3) { - gen_op_st_v(s, ot, *cpu_T[0], cpu_A0); + gen_op_st_v(s, ot, cpu_T0, cpu_A0); } else { - gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0); } } @@ -7220,7 +7232,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); - gen_extu(tcg_ctx, ot, *cpu_T[0]); + gen_extu(tcg_ctx, ot, cpu_T0); /* Note that lzcnt and tzcnt are in different extensions. */ if ((prefixes & PREFIX_REPZ) @@ -7228,18 +7240,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ? s->cpuid_ext3_features & CPUID_EXT3_ABM : s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)) { int size = 8 << ot; - tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, *cpu_T[0]); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, cpu_T0); if (b & 1) { /* For lzcnt, reduce the target_ulong result by the number of zeros that we expect to find at the top. */ - gen_helper_clz(tcg_ctx, *cpu_T[0], *cpu_T[0]); - tcg_gen_subi_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], TARGET_LONG_BITS - size); + gen_helper_clz(tcg_ctx, cpu_T0, cpu_T0); + tcg_gen_subi_tl(tcg_ctx, cpu_T0, cpu_T0, TARGET_LONG_BITS - size); } else { /* For tzcnt, a zero input must return the operand size: force all bits outside the operand size to 1. */ target_ulong mask = (target_ulong)-2 << (size - 1); - tcg_gen_ori_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], mask); - gen_helper_ctz(tcg_ctx, *cpu_T[0], *cpu_T[0]); + tcg_gen_ori_tl(tcg_ctx, cpu_T0, cpu_T0, mask); + gen_helper_ctz(tcg_ctx, cpu_T0, cpu_T0); } /* For lzcnt/tzcnt, C and Z bits are defined and are related to the result. */ @@ -7248,24 +7260,24 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { /* For bsr/bsf, only the Z bit is defined and it is related to the input and not the result. */ - tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, *cpu_T[0]); + tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, cpu_T0); set_cc_op(s, CC_OP_LOGICB + ot); if (b & 1) { /* For bsr, return the bit index of the first 1 bit, not the count of leading zeros. */ - gen_helper_clz(tcg_ctx, *cpu_T[0], *cpu_T[0]); - tcg_gen_xori_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], TARGET_LONG_BITS - 1); + gen_helper_clz(tcg_ctx, cpu_T0, cpu_T0); + tcg_gen_xori_tl(tcg_ctx, cpu_T0, cpu_T0, TARGET_LONG_BITS - 1); } else { - gen_helper_ctz(tcg_ctx, *cpu_T[0], *cpu_T[0]); + gen_helper_ctz(tcg_ctx, cpu_T0, cpu_T0); } /* ??? The manual says that the output is undefined when the input is zero, but real hardware leaves it unchanged, and real programs appear to depend on that. */ tcg_gen_movi_tl(tcg_ctx, cpu_tmp0, 0); - tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, *cpu_T[0], cpu_cc_dst, cpu_tmp0, - *cpu_regs[reg], *cpu_T[0]); + tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, cpu_T0, cpu_cc_dst, cpu_tmp0, + *cpu_regs[reg], cpu_T0); } - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); break; /************************/ /* bcd */ @@ -7421,9 +7433,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, mod = (modrm >> 6) & 3; if (mod == 3) goto illegal_op; - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], reg); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, reg); gen_lea_modrm(env, s, modrm); - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); if (ot == MO_16) { gen_helper_boundw(tcg_ctx, cpu_env, cpu_A0, cpu_tmp2_i32); } else { @@ -7435,24 +7447,24 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, reg = (b & 7) | REX_B(s); #ifdef TARGET_X86_64 if (dflag == MO_64) { - gen_op_mov_v_reg(tcg_ctx, MO_64, *cpu_T[0], reg); - tcg_gen_bswap64_i64(tcg_ctx, *cpu_T[0], *cpu_T[0]); - gen_op_mov_reg_v(tcg_ctx, MO_64, reg, *cpu_T[0]); + gen_op_mov_v_reg(tcg_ctx, MO_64, cpu_T0, reg); + tcg_gen_bswap64_i64(tcg_ctx, cpu_T0, cpu_T0); + gen_op_mov_reg_v(tcg_ctx, MO_64, reg, cpu_T0); } else #endif { - gen_op_mov_v_reg(tcg_ctx, MO_32, *cpu_T[0], reg); - tcg_gen_ext32u_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); - tcg_gen_bswap32_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); - gen_op_mov_reg_v(tcg_ctx, MO_32, reg, *cpu_T[0]); + gen_op_mov_v_reg(tcg_ctx, MO_32, cpu_T0, reg); + tcg_gen_ext32u_tl(tcg_ctx, cpu_T0, cpu_T0); + tcg_gen_bswap32_tl(tcg_ctx, cpu_T0, cpu_T0); + gen_op_mov_reg_v(tcg_ctx, MO_32, reg, cpu_T0); } break; case 0xd6: /* salc */ if (CODE64(s)) goto illegal_op; - gen_compute_eflags_c(s, *cpu_T[0]); - tcg_gen_neg_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); - gen_op_mov_reg_v(tcg_ctx, MO_8, R_EAX, *cpu_T[0]); + gen_compute_eflags_c(s, cpu_T0); + tcg_gen_neg_tl(tcg_ctx, cpu_T0, cpu_T0); + gen_op_mov_reg_v(tcg_ctx, MO_8, R_EAX, cpu_T0); break; case 0xe0: /* loopnz */ case 0xe1: /* loopz */ @@ -7589,7 +7601,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (!s->pe || s->vm86) goto illegal_op; gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); - tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector)); + tcg_gen_ld32u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,ldt.selector)); ot = mod == 3 ? dflag : MO_16; gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; @@ -7601,7 +7613,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); gen_helper_lldt(tcg_ctx, cpu_env, cpu_tmp2_i32); } break; @@ -7609,7 +7621,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (!s->pe || s->vm86) goto illegal_op; gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); - tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector)); + tcg_gen_ld32u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,tr.selector)); ot = mod == 3 ? dflag : MO_16; gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; @@ -7621,7 +7633,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); - tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, *cpu_T[0]); + tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0); gen_helper_ltr(tcg_ctx, cpu_env, cpu_tmp2_i32); } break; @@ -7632,9 +7644,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_update_cc_op(s); if (op == 4) { - gen_helper_verr(tcg_ctx, cpu_env, *cpu_T[0]); + gen_helper_verr(tcg_ctx, cpu_env, cpu_T0); } else { - gen_helper_verw(tcg_ctx, cpu_env, *cpu_T[0]); + gen_helper_verw(tcg_ctx, cpu_env, cpu_T0); } set_cc_op(s, CC_OP_EFLAGS); break; @@ -7653,14 +7665,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, goto illegal_op; gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); gen_lea_modrm(env, s, modrm); - tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)); - gen_op_st_v(s, MO_16, *cpu_T[0], cpu_A0); + tcg_gen_ld32u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, gdt.limit)); + gen_op_st_v(s, MO_16, cpu_T0, cpu_A0); gen_add_A0_im(s, 2); - tcg_gen_ld_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); + tcg_gen_ld_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, gdt.base)); if (dflag == MO_16) { - tcg_gen_andi_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], 0xffffff); + tcg_gen_andi_tl(tcg_ctx, cpu_T0, cpu_T0, 0xffffff); } - gen_op_st_v(s, CODE64(s) + MO_32, *cpu_T[0], cpu_A0); + gen_op_st_v(s, CODE64(s) + MO_32, cpu_T0, cpu_A0); break; case 1: if (mod == 3) { @@ -7709,14 +7721,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { /* sidt */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); gen_lea_modrm(env, s, modrm); - tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)); - gen_op_st_v(s, MO_16, *cpu_T[0], cpu_A0); + tcg_gen_ld32u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, idt.limit)); + gen_op_st_v(s, MO_16, cpu_T0, cpu_A0); gen_add_A0_im(s, 2); - tcg_gen_ld_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); + tcg_gen_ld_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, idt.base)); if (dflag == MO_16) { - tcg_gen_andi_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], 0xffffff); + tcg_gen_andi_tl(tcg_ctx, cpu_T0, cpu_T0, 0xffffff); } - gen_op_st_v(s, CODE64(s) + MO_32, *cpu_T[0], cpu_A0); + gen_op_st_v(s, CODE64(s) + MO_32, cpu_T0, cpu_A0); } break; case 2: /* lgdt */ @@ -7812,27 +7824,27 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_svm_check_intercept(s, pc_start, op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE); gen_lea_modrm(env, s, modrm); - gen_op_ld_v(s, MO_16, *cpu_T[1], cpu_A0); + gen_op_ld_v(s, MO_16, cpu_T1, cpu_A0); gen_add_A0_im(s, 2); - gen_op_ld_v(s, CODE64(s) + MO_32, *cpu_T[0], cpu_A0); + gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T0, cpu_A0); if (dflag == MO_16) { - tcg_gen_andi_tl(tcg_ctx, *cpu_T[0], *cpu_T[0], 0xffffff); + tcg_gen_andi_tl(tcg_ctx, cpu_T0, cpu_T0, 0xffffff); } if (op == 2) { - tcg_gen_st_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base)); - tcg_gen_st32_tl(tcg_ctx, *cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit)); + tcg_gen_st_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,gdt.base)); + tcg_gen_st32_tl(tcg_ctx, cpu_T1, cpu_env, offsetof(CPUX86State,gdt.limit)); } else { - tcg_gen_st_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base)); - tcg_gen_st32_tl(tcg_ctx, *cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit)); + tcg_gen_st_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,idt.base)); + tcg_gen_st32_tl(tcg_ctx, cpu_T1, cpu_env, offsetof(CPUX86State,idt.limit)); } } break; case 4: /* smsw */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN - tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4); + tcg_gen_ld32u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,cr[0]) + 4); #else - tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])); + tcg_gen_ld32u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,cr[0])); #endif gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 1); break; @@ -7842,7 +7854,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); - gen_helper_lmsw(tcg_ctx, cpu_env, *cpu_T[0]); + gen_helper_lmsw(tcg_ctx, cpu_env, cpu_T0); gen_jmp_im(s, s->pc - s->cs_base); gen_eob(s); } @@ -7869,10 +7881,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { TCGv **cpu_seg_base = (TCGv **)tcg_ctx->cpu_seg_base; - tcg_gen_mov_tl(tcg_ctx, *cpu_T[0], *cpu_seg_base[R_GS]); + tcg_gen_mov_tl(tcg_ctx, cpu_T0, *cpu_seg_base[R_GS]); tcg_gen_ld_tl(tcg_ctx, *cpu_seg_base[R_GS], cpu_env, offsetof(CPUX86State, kernelgsbase)); - tcg_gen_st_tl(tcg_ctx, *cpu_T[0], cpu_env, + tcg_gen_st_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, kernelgsbase)); } break; @@ -7917,16 +7929,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, rm = (modrm & 7) | REX_B(s); if (mod == 3) { - gen_op_mov_v_reg(tcg_ctx, MO_32, *cpu_T[0], rm); + gen_op_mov_v_reg(tcg_ctx, MO_32, cpu_T0, rm); /* sign extend */ if (d_ot == MO_64) { - tcg_gen_ext32s_tl(tcg_ctx, *cpu_T[0], *cpu_T[0]); + tcg_gen_ext32s_tl(tcg_ctx, cpu_T0, cpu_T0); } - gen_op_mov_reg_v(tcg_ctx, d_ot, reg, *cpu_T[0]); + gen_op_mov_reg_v(tcg_ctx, d_ot, reg, cpu_T0); } else { gen_lea_modrm(env, s, modrm); - gen_op_ld_v(s, MO_32 | MO_SIGN, *cpu_T[0], cpu_A0); - gen_op_mov_reg_v(tcg_ctx, d_ot, reg, *cpu_T[0]); + gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T0, cpu_A0); + gen_op_mov_reg_v(tcg_ctx, d_ot, reg, cpu_T0); } } else #endif @@ -7991,9 +8003,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, t0 = tcg_temp_local_new(tcg_ctx); gen_update_cc_op(s); if (b == 0x102) { - gen_helper_lar(tcg_ctx, t0, cpu_env, *cpu_T[0]); + gen_helper_lar(tcg_ctx, t0, cpu_env, cpu_T0); } else { - gen_helper_lsl(tcg_ctx, t0, cpu_env, *cpu_T[0]); + gen_helper_lsl(tcg_ctx, t0, cpu_env, cpu_T0); } tcg_gen_andi_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, CC_Z); label1 = gen_new_label(tcg_ctx); @@ -8058,14 +8070,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); if (b & 2) { - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], rm); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, rm); gen_helper_write_crN(tcg_ctx, cpu_env, tcg_const_i32(tcg_ctx, reg), - *cpu_T[0]); + cpu_T0); gen_jmp_im(s, s->pc - s->cs_base); gen_eob(s); } else { - gen_helper_read_crN(tcg_ctx, *cpu_T[0], cpu_env, tcg_const_i32(tcg_ctx, reg)); - gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]); + gen_helper_read_crN(tcg_ctx, cpu_T0, cpu_env, tcg_const_i32(tcg_ctx, reg)); + gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0); } break; default: @@ -8095,16 +8107,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } if (b & 2) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); - gen_op_mov_v_reg(tcg_ctx, ot, *cpu_T[0], rm); + gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, rm); tcg_gen_movi_i32(tcg_ctx, cpu_tmp2_i32, reg); - gen_helper_set_dr(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp2_i32, *cpu_T[0]); + gen_helper_set_dr(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp2_i32, cpu_T0); gen_jmp_im(s, s->pc - s->cs_base); gen_eob(s); } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg); tcg_gen_movi_i32(tcg_ctx, cpu_tmp2_i32, reg); - gen_helper_get_dr(tcg_ctx, *cpu_T[0], tcg_ctx->cpu_env, cpu_tmp2_i32); - gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]); + gen_helper_get_dr(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_tmp2_i32); + gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0); } } break; @@ -8178,8 +8190,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, s->mem_index, MO_LEUL); gen_helper_ldmxcsr(tcg_ctx, cpu_env, cpu_tmp2_i32); } else { - tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); - gen_op_st_v(s, MO_32, *cpu_T[0], cpu_A0); + tcg_gen_ld32u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, mxcsr)); + gen_op_st_v(s, MO_32, cpu_T0, cpu_A0); } break; case 5: /* lfence */ @@ -8261,8 +8273,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); - gen_helper_popcnt(tcg_ctx, *cpu_T[0], cpu_env, *cpu_T[0], tcg_const_i32(tcg_ctx, ot)); - gen_op_mov_reg_v(tcg_ctx, ot, reg, *cpu_T[0]); + gen_helper_popcnt(tcg_ctx, cpu_T0, cpu_env, cpu_T0, tcg_const_i32(tcg_ctx, ot)); + gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0); set_cc_op(s, CC_OP_EFLAGS); break; @@ -8478,12 +8490,12 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) #endif if (!env->uc->init_tcg) - tcg_ctx->cpu_T[0] = g_malloc0(sizeof(TCGv)); - *(TCGv *)tcg_ctx->cpu_T[0] = tcg_temp_new(tcg_ctx); + tcg_ctx->cpu_T0 = g_malloc0(sizeof(TCGv)); + *((TCGv *)tcg_ctx->cpu_T0) = tcg_temp_new(tcg_ctx); if (!env->uc->init_tcg) - tcg_ctx->cpu_T[1] = g_malloc0(sizeof(TCGv)); - *(TCGv *)tcg_ctx->cpu_T[1] = tcg_temp_new(tcg_ctx); + tcg_ctx->cpu_T1 = g_malloc0(sizeof(TCGv)); + *((TCGv *)tcg_ctx->cpu_T1) = tcg_temp_new(tcg_ctx); if (!env->uc->init_tcg) tcg_ctx->cpu_A0 = g_malloc0(sizeof(TCGv)); diff --git a/qemu/target-i386/unicorn.c b/qemu/target-i386/unicorn.c index 4b47bd26..8322992c 100644 --- a/qemu/target-i386/unicorn.c +++ b/qemu/target-i386/unicorn.c @@ -39,8 +39,8 @@ void x86_release(void *ctx) // arch specific g_free(s->cpu_A0); - g_free(s->cpu_T[0]); - g_free(s->cpu_T[1]); + g_free(s->cpu_T0); + g_free(s->cpu_T1); g_free(s->cpu_tmp0); g_free(s->cpu_tmp4); g_free(s->cpu_cc_srcT); diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h index 5035d09e..8d9868c8 100644 --- a/qemu/tcg/tcg.h +++ b/qemu/tcg/tcg.h @@ -728,7 +728,8 @@ struct TCGContext { void *cpu_cc_dst, *cpu_cc_src, *cpu_cc_src2, *cpu_cc_srcT; /* qemu/target-i386/translate.c: local temps */ - void *cpu_T[2]; + void *cpu_T0; // Actually a TCGv + void *cpu_T1; // Actually a TCGv /* qemu/target-i386/translate.c: local register indexes (only used inside old micro ops) */ void *cpu_tmp0, *cpu_tmp4;